From 82d30a310c69a9a374f45a571b551b0d0a838777 Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 11 Nov 2016 10:16:33 +0100
Subject: score: Move CPU_PER_CPU_CONTROL_SIZE

Move CPU_PER_CPU_CONTROL_SIZE and the optional CPU_Per_CPU_control to
<rtems/score/cpuimpl.h> to hide it from <rtems.h>.
---
 cpukit/score/cpu/sparc/rtems/score/cpu.h     | 41 --------------------------
 cpukit/score/cpu/sparc/rtems/score/cpuimpl.h | 44 +++++++++++++++++++++++++++-
 2 files changed, 43 insertions(+), 42 deletions(-)

(limited to 'cpukit/score/cpu/sparc/rtems/score')

diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h
index 6339a79f59..a4d3eef3dc 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h
@@ -347,28 +347,8 @@ typedef struct {
 /** This defines the size of the minimum stack frame. */
 #define CPU_MINIMUM_STACK_FRAME_SIZE          0x60
 
-#if ( SPARC_HAS_FPU == 1 )
-  #define CPU_PER_CPU_CONTROL_SIZE 8
-#else
-  #define CPU_PER_CPU_CONTROL_SIZE 4
-#endif
-
 #define CPU_MAXIMUM_PROCESSORS 32
 
-/**
- * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field
- * relative to the Per_CPU_Control begin.
- */
-#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0
-
-#if ( SPARC_HAS_FPU == 1 )
-  /**
-   * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
-   * Per_CPU_Control begin.
-   */
-  #define SPARC_PER_CPU_FSR_OFFSET 4
-#endif
-
 /**
  * @defgroup Contexts SPARC Context Structures
  *
@@ -392,27 +372,6 @@ typedef struct {
 
 #ifndef ASM
 
-typedef struct {
-  /**
-   * This flag is context switched with each thread.  It indicates
-   * that THIS thread has an _ISR_Dispatch stack frame on its stack.
-   * By using this flag, we can avoid nesting more interrupt dispatching
-   * attempts on a previously interrupted thread's stack.
-   */
-  uint32_t isr_dispatch_disable;
-
-#if ( SPARC_HAS_FPU == 1 )
-  /**
-   * @brief Memory location to store the FSR register during interrupt
-   * processing.
-   *
-   * This is a write-only field.  The FSR is written to force a completion of
-   * floating point operations in progress.
-   */
-  uint32_t fsr;
-#endif
-} CPU_Per_CPU_control;
-
 /**
  * @brief SPARC basic context.
  *
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h b/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
index bb53bf996f..27a8d776b8 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpuimpl.h
@@ -5,7 +5,8 @@
  */
 
 /*
- * Copyright (c) 2015, 2016 embedded brains GmbH
+ * Copyright (c) 2007 On-Line Applications Research Corporation (OAR)
+ * Copyright (c) 2013, 2016 embedded brains GmbH
  *
  * The license and distribution terms for this file may be
  * found in the file LICENSE in this distribution or at
@@ -17,12 +18,53 @@
 
 #include <rtems/score/cpu.h>
 
+#if ( SPARC_HAS_FPU == 1 )
+  #define CPU_PER_CPU_CONTROL_SIZE 8
+#else
+  #define CPU_PER_CPU_CONTROL_SIZE 4
+#endif
+
+/**
+ * @brief Offset of the CPU_Per_CPU_control::isr_dispatch_disable field
+ * relative to the Per_CPU_Control begin.
+ */
+#define SPARC_PER_CPU_ISR_DISPATCH_DISABLE 0
+
+#if ( SPARC_HAS_FPU == 1 )
+  /**
+   * @brief Offset of the CPU_Per_CPU_control::fsr field relative to the
+   * Per_CPU_Control begin.
+   */
+  #define SPARC_PER_CPU_FSR_OFFSET 4
+#endif
+
 #ifndef ASM
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
+typedef struct {
+  /**
+   * This flag is context switched with each thread.  It indicates
+   * that THIS thread has an _ISR_Dispatch stack frame on its stack.
+   * By using this flag, we can avoid nesting more interrupt dispatching
+   * attempts on a previously interrupted thread's stack.
+   */
+  uint32_t isr_dispatch_disable;
+
+#if ( SPARC_HAS_FPU == 1 )
+  /**
+   * @brief Memory location to store the FSR register during interrupt
+   * processing.
+   *
+   * This is a write-only field.  The FSR is written to force a completion of
+   * floating point operations in progress.
+   */
+  uint32_t fsr;
+#endif
+} CPU_Per_CPU_control;
+
 /**
  * @brief The pointer to the current per-CPU control is available via register
  * g6.
-- 
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