From f8ad6c6f7f8b591e54db77b1fae81ab5e143f8e3 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 2 Aug 2013 14:12:55 +0200 Subject: sparc: Make _CPU_ISR_Dispatch_disable per-CPU This variable must be available for each processor in the system. --- cpukit/score/cpu/sparc/cpu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) (limited to 'cpukit/score/cpu/sparc/cpu.c') diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c index baa15c0cbb..1865a21ee8 100644 --- a/cpukit/score/cpu/sparc/cpu.c +++ b/cpukit/score/cpu/sparc/cpu.c @@ -19,8 +19,15 @@ #include #include +#include #include +RTEMS_STATIC_ASSERT( + offsetof( Per_CPU_Control, cpu_per_cpu.isr_dispatch_disable) + == SPARC_PER_CPU_ISR_DISPATCH_DISABLE, + SPARC_PER_CPU_ISR_DISPATCH_DISABLE +); + /* * This initializes the set of opcodes placed in each trap * table entry. The routine which installs a handler is responsible @@ -65,13 +72,6 @@ void _CPU_Initialize(void) pointer = &_CPU_Null_fp_context; _CPU_Context_save_fp( &pointer ); #endif - - /* - * Since no tasks have been created yet and no interrupts have occurred, - * there is no way that the currently executing thread can have an - * _ISR_Dispatch stack frame on its stack. - */ - _CPU_ISR_Dispatch_disable = 0; } uint32_t _CPU_ISR_Get_level( void ) -- cgit v1.2.3