From b2ec2d15971503466e1debf596dc84b6af0f9b13 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 22 Apr 2014 07:46:56 +0200 Subject: sparc: Optimize context switch The registers g2 through g4 are reserved for applications. GCC uses them as volatile registers by default. So they are treated like volatile registers in RTEMS as well. --- cpukit/score/cpu/sparc/cpu.c | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) (limited to 'cpukit/score/cpu/sparc/cpu.c') diff --git a/cpukit/score/cpu/sparc/cpu.c b/cpukit/score/cpu/sparc/cpu.c index 73ed4fdd78..463ff4736c 100644 --- a/cpukit/score/cpu/sparc/cpu.c +++ b/cpukit/score/cpu/sparc/cpu.c @@ -35,13 +35,20 @@ RTEMS_STATIC_ASSERT( Context_Control_offset_ ## field \ ) -SPARC_ASSERT_OFFSET(g2_g3, G2); -SPARC_ASSERT_OFFSET(g4, G4); SPARC_ASSERT_OFFSET(g5, G5); SPARC_ASSERT_OFFSET(g6, G6); SPARC_ASSERT_OFFSET(g7, G7); -SPARC_ASSERT_OFFSET(l0, L0); -SPARC_ASSERT_OFFSET(l1, L1); + +RTEMS_STATIC_ASSERT( + offsetof(Context_Control, l0_and_l1) == L0_OFFSET, + Context_Control_offset_L0 +); + +RTEMS_STATIC_ASSERT( + offsetof(Context_Control, l0_and_l1) + 4 == L1_OFFSET, + Context_Control_offset_L1 +); + SPARC_ASSERT_OFFSET(l2, L2); SPARC_ASSERT_OFFSET(l3, L3); SPARC_ASSERT_OFFSET(l4, L4); @@ -61,12 +68,6 @@ SPARC_ASSERT_OFFSET(o7, O7); SPARC_ASSERT_OFFSET(psr, PSR); SPARC_ASSERT_OFFSET(isr_dispatch_disable, ISR_DISPATCH_DISABLE_STACK); -RTEMS_STATIC_ASSERT( - (offsetof(Context_Control, g2_g3) - + offsetof(Context_Control, g4)) / 2 == G3_OFFSET, - Context_Control_offset_G3 -); - /* * This initializes the set of opcodes placed in each trap * table entry. The routine which installs a handler is responsible -- cgit v1.2.3