From 2bc49cf764d1dfcbd9cd42dd03698e0c70933383 Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Fri, 25 Oct 2002 05:02:43 +0000 Subject: 2002-10-25 Ralf Corsepius * rtems/score/sh.h: Fix typo in comment (Starus->Status). --- cpukit/score/cpu/sh/ChangeLog | 4 ++++ cpukit/score/cpu/sh/rtems/score/sh.h | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-) (limited to 'cpukit/score/cpu/sh') diff --git a/cpukit/score/cpu/sh/ChangeLog b/cpukit/score/cpu/sh/ChangeLog index baa2234331..46462179d6 100644 --- a/cpukit/score/cpu/sh/ChangeLog +++ b/cpukit/score/cpu/sh/ChangeLog @@ -1,3 +1,7 @@ +2002-10-25 Ralf Corsepius + + * rtems/score/sh.h: Fix typo in comment (Starus->Status). + 2002-10-21 Ralf Corsepius * .cvsignore: Reformat. diff --git a/cpukit/score/cpu/sh/rtems/score/sh.h b/cpukit/score/cpu/sh/rtems/score/sh.h index a48dea97f0..7d98e19f60 100644 --- a/cpukit/score/cpu/sh/rtems/score/sh.h +++ b/cpukit/score/cpu/sh/rtems/score/sh.h @@ -243,7 +243,7 @@ extern unsigned int sh_set_irq_priority( #define SH4_SR_T 0x00000001 /* 1 if last condiyion was true */ #define SH4_SR_RESERV 0x8fff7d0d /* Reserved bits, read/write as 0 */ -/* FPSCR -- FPU Starus/Control Register */ +/* FPSCR -- FPU Status/Control Register */ #define SH4_FPSCR_FR 0x00200000 /* FPU register bank specifier */ #define SH4_FPSCR_SZ 0x00100000 /* FMOV 64-bit transfer mode */ #define SH4_FPSCR_PR 0x00080000 /* Double-percision floating-point -- cgit v1.2.3