From faaffbd913c0e4e39444b2b4b0e0bfb93cc1a0a2 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 25 Feb 2022 17:45:06 +0100 Subject: riscv: Use zicsr architecture extension This is required for ISA 2.0 support, see chapter "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 in RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA --- cpukit/score/cpu/riscv/riscv-exception-handler.S | 1 + 1 file changed, 1 insertion(+) (limited to 'cpukit/score/cpu/riscv/riscv-exception-handler.S') diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index 9330f246b1..87a69652a4 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -45,6 +45,7 @@ PUBLIC(_RISCV_Exception_handler) .section .text, "ax", @progbits .align 2 + .option arch, +zicsr TYPE_FUNC(_RISCV_Exception_handler) SYM(_RISCV_Exception_handler): -- cgit v1.2.3