From faaffbd913c0e4e39444b2b4b0e0bfb93cc1a0a2 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 25 Feb 2022 17:45:06 +0100 Subject: riscv: Use zicsr architecture extension This is required for ISA 2.0 support, see chapter "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0 in RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA --- .../score/cpu/riscv/include/rtems/score/riscv-utility.h | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) (limited to 'cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h') diff --git a/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h b/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h index dc4836bee2..1cfcf8dbad 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/riscv-utility.h @@ -247,22 +247,27 @@ typedef enum { #ifdef __GNUC__ #define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ + asm volatile (".option push\n.option arch, +zicsr\n" \ + "csrr %0, " #reg "\n.option pop ": "=r"(__tmp)); \ __tmp; }) #define write_csr(reg, val) ({ \ - asm volatile ("csrw " #reg ", %0" :: "rK"(val)); }) + asm volatile (".option push\n.option arch, +zicsr\n" \ + "csrw " #reg ", %0\n.option pop" :: "rK"(val)); }) #define swap_csr(reg, val) ({ unsigned long __tmp; \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \ + asm volatile (".option push\n.option arch, +zicsr\n" \ + "csrrw %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(val)); \ __tmp; }) #define set_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + asm volatile (".option push\n.option arch, +zicsr\nc" \ + "srrs %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) #define clear_csr(reg, bit) ({ unsigned long __tmp; \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \ + asm volatile (".option push\n.option arch, +zicsr\n" \ + "csrrc %0, " #reg ", %1\n.option pop" : "=r"(__tmp) : "rK"(bit)); \ __tmp; }) #define rdtime() read_csr(time) -- cgit v1.2.3