From 5018894ee176d1b05daf156a8b858b3db0d457f4 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Mon, 20 Nov 2017 07:45:15 +0100 Subject: bsps/powerpc: Fix PPC_EXC_CONFIG_USE_FIXED_HANDLER For the SPE support we must store the upper half of r3 as well. Update #3085. --- cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpukit/score/cpu/powerpc/rtems/score') diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h b/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h index c292feb6fd..792a8111ad 100644 --- a/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/powerpc/rtems/score/cpuimpl.h @@ -42,7 +42,7 @@ #ifndef __SPE__ #define PPC_EXC_GPR_OFFSET(gpr) \ ((gpr) * PPC_GPR_SIZE + PPC_EXC_INTERRUPT_FRAME_OFFSET + PPC_REG_SIZE) - #define PPC_EXC_VECTOR_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(4) + #define PPC_EXC_GPR3_PROLOGUE_OFFSET PPC_EXC_GPR_OFFSET(3) #if defined(PPC_MULTILIB_ALTIVEC) && defined(PPC_MULTILIB_FPU) #define PPC_EXC_VRSAVE_OFFSET PPC_EXC_GPR_OFFSET(33) #define PPC_EXC_VSCR_OFFSET (PPC_EXC_VRSAVE_OFFSET + 28) @@ -82,7 +82,7 @@ #define PPC_EXC_SPEFSCR_OFFSET 44 #define PPC_EXC_ACC_OFFSET 48 #define PPC_EXC_GPR_OFFSET(gpr) ((gpr) * PPC_GPR_SIZE + 56) - #define PPC_EXC_VECTOR_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(4) + 4) + #define PPC_EXC_GPR3_PROLOGUE_OFFSET (PPC_EXC_GPR_OFFSET(3) + 4) #define CPU_INTERRUPT_FRAME_SIZE (160 + PPC_STACK_RED_ZONE_SIZE) #define PPC_EXC_FRAME_SIZE 320 #endif -- cgit v1.2.3