From 58847845eb2e598f3e1a2b5ec153dd7b13e08ea3 Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Tue, 15 Feb 2005 15:10:52 +0000 Subject: (PPC_Get_timebase_register, PPC_Set_timebase_register): New. --- cpukit/score/cpu/powerpc/rtems/score/cpu.h | 37 ++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) (limited to 'cpukit/score/cpu/powerpc/rtems/score/cpu.h') diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h index 25ad5d627e..23fd4a3906 100644 --- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h +++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h @@ -160,5 +160,42 @@ static inline uint32_t CPU_swap_u32( #endif /* ASM */ +#ifndef ASM +/* + * Routines to access the time base register + */ + +static inline uint64_t PPC_Get_timebase_register( void ) +{ + uint32_t tbr_low; + uint32_t tbr_high; + uint32_t tbr_high_old; + uint64_t tbr; + + do { + asm volatile( "mftbu %0" : "=r" (tbr_high_old)); + asm volatile( "mftb %0" : "=r" (tbr_low)); + asm volatile( "mftbu %0" : "=r" (tbr_high)); + } while ( tbr_high_old != tbr_high ); + + tbr = tbr_high; + tbr <<= 32; + tbr |= tbr_low; + return tbr; +} + +static inline void PPC_Set_timebase_register (uint64_t tbr) +{ + uint32_t tbr_low; + uint32_t tbr_high; + + tbr_low = (tbr & 0xffffffff) ; + tbr_high = (tbr >> 32) & 0xffffffff; + asm volatile( "mtspr 284, %0" : : "r" (tbr_low)); + asm volatile( "mtspr 285, %0" : : "r" (tbr_high)); + +} +#endif /* ASM */ + #endif /* _RTEMS_SCORE_CPU_H */ -- cgit v1.2.3