From 3662a9afc90ce534a2936f44e46e10f83a757283 Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Fri, 18 Feb 2005 06:24:27 +0000 Subject: (Context_Control, Context_Control_fp, CPU_Interrupt_frame): Remove. --- .../score/cpu/powerpc/rtems/new-exceptions/cpu.h | 110 --------------------- 1 file changed, 110 deletions(-) (limited to 'cpukit/score/cpu/powerpc/rtems/new-exceptions') diff --git a/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h b/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h index 27f4353285..1493cd5e17 100644 --- a/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h +++ b/cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h @@ -267,117 +267,7 @@ extern "C" { * Processor defined structures required for cpukit/score. */ -/* may need to put some structures here. */ - -/* - * Contexts - * - * Generally there are 2 types of context to save. - * 1. Interrupt registers to save - * 2. Task level registers to save - * - * This means we have the following 3 context items: - * 1. task level context stuff:: Context_Control - * 2. floating point task stuff:: Context_Control_fp - * 3. special interrupt level context :: Context_Control_interrupt - * - * On some processors, it is cost-effective to save only the callee - * preserved registers during a task context switch. This means - * that the ISR code needs to save those registers which do not - * persist across function calls. It is not mandatory to make this - * distinctions between the caller/callee saves registers for the - * purpose of minimizing context saved during task switch and on interrupts. - * If the cost of saving extra registers is minimal, simplicity is the - * choice. Save the same context on interrupt entry as for tasks in - * this case. - * - * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then - * care should be used in designing the context area. - * - * On some CPUs with hardware floating point support, the Context_Control_fp - * structure will not be used or it simply consist of an array of a - * fixed number of bytes. This is done when the floating point context - * is dumped by a "FP save context" type instruction and the format - * is not really defined by the CPU. In this case, there is no need - * to figure out the exact format -- only the size. Of course, although - * this is enough information for RTEMS, it is probably not enough for - * a debugger such as gdb. But that is another problem. - */ - #ifndef ASM - -typedef struct { - uint32_t gpr1; /* Stack pointer for all */ - uint32_t gpr2; /* TOC in PowerOpen, reserved SVR4, section ptr EABI + */ - uint32_t gpr13; /* First non volatile PowerOpen, section ptr SVR4/EABI */ - uint32_t gpr14; /* Non volatile for all */ - uint32_t gpr15; /* Non volatile for all */ - uint32_t gpr16; /* Non volatile for all */ - uint32_t gpr17; /* Non volatile for all */ - uint32_t gpr18; /* Non volatile for all */ - uint32_t gpr19; /* Non volatile for all */ - uint32_t gpr20; /* Non volatile for all */ - uint32_t gpr21; /* Non volatile for all */ - uint32_t gpr22; /* Non volatile for all */ - uint32_t gpr23; /* Non volatile for all */ - uint32_t gpr24; /* Non volatile for all */ - uint32_t gpr25; /* Non volatile for all */ - uint32_t gpr26; /* Non volatile for all */ - uint32_t gpr27; /* Non volatile for all */ - uint32_t gpr28; /* Non volatile for all */ - uint32_t gpr29; /* Non volatile for all */ - uint32_t gpr30; /* Non volatile for all */ - uint32_t gpr31; /* Non volatile for all */ - uint32_t cr; /* PART of the CR is non volatile for all */ - uint32_t pc; /* Program counter/Link register */ - uint32_t msr; /* Initial interrupt level */ -} Context_Control; - -typedef struct { - /* The ABIs (PowerOpen/SVR4/EABI) only require saving f14-f31 over - * procedure calls. However, this would mean that the interrupt - * frame had to hold f0-f13, and the fpscr. And as the majority - * of tasks will not have an FP context, we will save the whole - * context here. - */ -#if (PPC_HAS_DOUBLE == 1) - double f[32]; - double fpscr; -#else - float f[32]; - float fpscr; -#endif -} Context_Control_fp; - -typedef struct CPU_Interrupt_frame { - uint32_t stacklink; /* Ensure this is a real frame (also reg1 save) */ - uint32_t calleeLr; /* link register used by callees: SVR4/EABI */ - /* This is what is left out of the primary contexts */ - uint32_t gpr0; - uint32_t gpr2; /* play safe */ - uint32_t gpr3; - uint32_t gpr4; - uint32_t gpr5; - uint32_t gpr6; - uint32_t gpr7; - uint32_t gpr8; - uint32_t gpr9; - uint32_t gpr10; - uint32_t gpr11; - uint32_t gpr12; - uint32_t gpr13; /* Play safe */ - uint32_t gpr28; /* For internal use by the IRQ handler */ - uint32_t gpr29; /* For internal use by the IRQ handler */ - uint32_t gpr30; /* For internal use by the IRQ handler */ - uint32_t gpr31; /* For internal use by the IRQ handler */ - uint32_t cr; /* Bits of this are volatile, so no-one may save */ - uint32_t ctr; - uint32_t xer; - uint32_t lr; - uint32_t pc; - uint32_t msr; - uint32_t pad[3]; -} CPU_Interrupt_frame; /* * The following table contains the information required to configure -- cgit v1.2.3