From 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 12 Jun 2000 19:57:02 +0000 Subject: Patch from John Cotton , Charles-Antoine Gauthier , and Darlene A. Stewart to add support for a number of very significant things: + BSPs for many variations on the Motorola MBX8xx board series + Cache Manager including initial support for m68040 and PowerPC + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use same code base. + Rework of eth_comm BSP to utiltize above. John reports this works on the 821 and 860 --- cpukit/score/cpu/powerpc/rtems/asm.h | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'cpukit/score/cpu/powerpc/rtems/asm.h') diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h index af14c95665..3c2e28ad5c 100644 --- a/cpukit/score/cpu/powerpc/rtems/asm.h +++ b/cpukit/score/cpu/powerpc/rtems/asm.h @@ -164,14 +164,20 @@ */ #define srr0 0x01a #define srr1 0x01b +#ifdef ppc403 #define srr2 0x3de /* IBM 400 series only */ #define srr3 0x3df /* IBM 400 series only */ +#endif /* ppc403 */ + #define sprg0 0x110 #define sprg1 0x111 #define sprg2 0x112 #define sprg3 0x113 +#define dar 0x013 /* Data Address Register */ +#define dec 0x016 /* Decrementer Register */ +#if defined(ppc403) /* the following SPR/DCR registers exist only in IBM 400 series */ #define dear 0x3d5 #define evpr 0x3d6 /* SPR: exception vector prefix register */ @@ -190,9 +196,13 @@ #define br7 0x087 /* DCR: memory bank register 7 */ /* end of IBM400 series register definitions */ +#elif defined(mpc860) || defined(mpc821) /* The following registers are for the MPC8x0 */ #define der 0x095 /* Debug Enable Register */ +#define ictrl 0x09E /* Instruction Support Control Register */ +#define immr 0x27E /* Internal Memory Map Register */ /* end of MPC8x0 registers */ +#endif /* * Following must be tailor for a particular flavor of the C compiler. -- cgit v1.2.3