From 4c89fbcd316ca99fa16a0acc31f88fb80cb3060f Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Tue, 27 Sep 2022 07:43:37 +0200 Subject: score: Add CPU_THREAD_LOCAL_STORAGE_VARIANT Update #3835. --- cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) (limited to 'cpukit/score/cpu/no_cpu/include') diff --git a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h index d5082383e8..72d223de24 100644 --- a/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h +++ b/cpukit/score/cpu/no_cpu/include/rtems/score/cpuimpl.h @@ -54,6 +54,24 @@ */ #define CPU_PER_CPU_CONTROL_SIZE 0 +/** + * @brief Defines the thread-local storage (TLS) variant. + * + * Use one of the following values: + * + * 10: The architecture uses Variant I and the TLS offsets emitted by the + * linker neglect the TCB (examples: nios2, m68k, microblaze, powerpc, + * riscv). The thread pointer directly references the thread-local data + * area. + * + * 11: The architecture uses Variant I and the TLS offsets emitted by the + * linker take the TCB into account (examples: arm, aarch64). + * The thread pointer references the TCB. + * + * 20: The architecture uses Variant II (examples: i386, sparc). + */ +#define CPU_THREAD_LOCAL_STORAGE_VARIANT 10 + #ifndef ASM #ifdef __cplusplus -- cgit v1.2.3