From 80f77327f3fbd95710cb44e308b3a3fe062ce220 Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Wed, 2 Dec 2009 09:48:25 +0000 Subject: Whitespace removal. --- cpukit/score/cpu/nios2/rtems/score/cpu.h | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) (limited to 'cpukit/score/cpu/nios2/rtems/score/cpu.h') diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h index 0bdc44a3fd..c4e113e783 100644 --- a/cpukit/score/cpu/nios2/rtems/score/cpu.h +++ b/cpukit/score/cpu/nios2/rtems/score/cpu.h @@ -13,7 +13,7 @@ * * + Anywhere there is an XXX, it should be replaced * with information about the CPU family being ported to. - * + * * + At the end of each comment section, there is a heading which * says "Port Specific Information:". When porting to RTEMS, * add CPU family specific information in this section @@ -168,7 +168,7 @@ extern "C" { /** * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector + * a pointer to the saved interrupt frame (1) or just the vector * number (0)? * * Port Specific Information: @@ -194,7 +194,7 @@ extern "C" { * an i387 and wish to leave floating point support out of RTEMS. */ -/** +/** * @def CPU_SOFTWARE_FP * * Does the CPU have no hardware floating point and GCC provides a @@ -202,7 +202,7 @@ extern "C" { * switched? * * This feature conditional is used to indicate whether or not there - * is software implemented floating point that must be context + * is software implemented floating point that must be context * switched. The determination of whether or not this applies * is very tool specific and the state saved/restored is also * compiler specific. @@ -519,7 +519,7 @@ typedef struct { /** * @ingroup CPUContext Management - * This defines the set of integer and processor state registers that are + * This defines the set of integer and processor state registers that are * saved during a software exception. */ typedef struct { @@ -592,14 +592,14 @@ SCORE_EXTERN Context_Control_fp _CPU_Null_fp_context; /** * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt + * This variable points to the lowest physical address of the interrupt * stack. */ SCORE_EXTERN void *_CPU_Interrupt_stack_low; /** * @ingroup CPUInterrupt - * This variable points to the lowest physical address of the interrupt + * This variable points to the lowest physical address of the interrupt * stack. */ SCORE_EXTERN void *_CPU_Interrupt_stack_high; @@ -694,7 +694,7 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; * * @note This does not have to be a power of 2 although it should be * a multiple of 2 greater than or equal to 2. The requirement - * to be a multiple of 2 is because the heap uses the least + * to be a multiple of 2 is because the heap uses the least * significant field of the front and back flags to indicate * that a block is in use or free. So you do not want any odd * length blocks really putting length data in that bit. @@ -990,7 +990,7 @@ uint32_t _CPU_ISR_Get_level( void ); /** * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation * - * This set of routines are used to implement fast searches for + * This set of routines are used to implement fast searches for * the most important ready task. */ @@ -1015,7 +1015,7 @@ uint32_t _CPU_ISR_Get_level( void ); /** * @ingroup CPUBitfield * This routine sets @a _output to the bit number of the first bit - * set in @a _value. @a _value is of CPU dependent type + * set in @a _value. @a _value is of CPU dependent type * @a Priority_Bit_map_control. This type may be either 16 or 32 bits * wide although only the 16 least significant bits will be used. * @@ -1058,14 +1058,14 @@ uint32_t _CPU_ISR_Get_level( void ); if _value > 0x00ff _value >>=8 _number = 8; - + if _value > 0x0000f _value >=8 _number += 4 - + _number += bit_set_table[ _value ] @endverbatim - + * where bit_set_table[ 16 ] has values which indicate the first * bit set * @@ -1137,7 +1137,7 @@ void _CPU_Initialize(void); /** * @ingroup CPUInterrupt - * This routine installs a "raw" interrupt handler directly into the + * This routine installs a "raw" interrupt handler directly into the * processor's vector table. * * @param vector (in) is the vector number @@ -1299,12 +1299,12 @@ static inline uint32_t CPU_swap_u32( ) { uint32_t byte1, byte2, byte3, byte4, swapped; - + byte4 = (value >> 24) & 0xff; byte3 = (value >> 16) & 0xff; byte2 = (value >> 8) & 0xff; byte1 = value & 0xff; - + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; return( swapped ); } -- cgit v1.2.3