From 8264d230a9f2f0312aec4c0fa6503139cea61d7c Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Fri, 8 Mar 2002 16:24:48 +0000 Subject: 2002-03-05 Greg Menke * cpu_asm.S: Added support for the debug exception vector, cleaned up the exception processing & exception return stuff. Re-added EPC in the task context structure so the gdb stub will know where a thread is executing. Should've left it there in the first place... * idtcpu.h: Added support for the debug exception vector. * cpu.c: Added ___exceptionTaskStack to hold a pointer to the stack frame in an interrupt so context switch code can get the userspace EPC when scheduling. * rtems/score/cpu.h: Re-added EPC to the task context. --- cpukit/score/cpu/mips/rtems/mips/idtcpu.h | 29 ++++++++++++- cpukit/score/cpu/mips/rtems/score/cpu.h | 2 +- cpukit/score/cpu/mips/rtems/score/mips.h | 72 +++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+), 2 deletions(-) (limited to 'cpukit/score/cpu/mips/rtems') diff --git a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h index 2f450b21b1..3ff31aa8c8 100644 --- a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h +++ b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h @@ -58,7 +58,8 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT */ #if __mips == 1 #define UT_VEC K0BASE /* utlbmiss vector */ -#define E_VEC (K0BASE+0x80) /* exception vevtor */ +#define DB_VEC (K0BASE+0x40) /* debug vector */ +#define E_VEC (K0BASE+0x80) /* exception vector */ #elif __mips == 3 #define T_VEC (K0BASE+0x000) /* tlbmiss vector */ #define X_VEC (K0BASE+0x080) /* xtlbmiss vector */ @@ -253,6 +254,32 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT #endif #if __mips == 1 + + +/* definitions for Debug and Cache Invalidate control (DCIC) register bits */ +#define DCIC_TR 0x80000000 /* Trap enable */ +#define DCIC_UD 0x40000000 /* User debug enable */ +#define DCIC_KD 0x20000000 /* Kernel debug enable */ +#define DCIC_TE 0x10000000 /* Trace enable */ +#define DCIC_DW 0x08000000 /* Enable data breakpoints on write */ +#define DCIC_DR 0x04000000 /* Enable data breakpoints on read */ +#define DCIC_DAE 0x02000000 /* Enable data addresss breakpoints */ +#define DCIC_PCE 0x01000000 /* Enable instruction breakpoints */ +#define DCIC_DE 0x00800000 /* Debug enable */ +#define DCIC_DL 0x00008000 /* Data cache line invalidate */ +#define DCIC_IL 0x00004000 /* Instruction cache line invalidate */ +#define DCIC_D 0x00002000 /* Data cache invalidate enable */ +#define DCIC_I 0x00001000 /* Instr. cache invalidate enable */ +#define DCIC_T 0x00000020 /* Trace, set by CPU */ +#define DCIC_W 0x00000010 /* Write reference, set by CPU */ +#define DCIC_R 0x00000008 /* Read reference, set by CPU */ +#define DCIC_DA 0x00000004 /* Data address, set by CPU */ +#define DCIC_PC 0x00000002 /* Program counter, set by CPU */ +#define DCIC_DB 0x00000001 /* Debug, set by CPU */ + + + + #define SR_CUMASK 0xf0000000 /* coproc usable bits */ #define SR_CU3 0x80000000 /* Coprocessor 3 usable */ #define SR_CU2 0x40000000 /* Coprocessor 2 usable */ diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index d2a29ed4f0..ed87991c3c 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -385,7 +385,7 @@ typedef struct { __MIPS_REGISTER_TYPE fp; __MIPS_REGISTER_TYPE ra; __MIPS_REGISTER_TYPE c0_sr; -/* __MIPS_REGISTER_TYPE c0_epc; */ + __MIPS_REGISTER_TYPE c0_epc; } Context_Control; /* WARNING: If this structure is modified, the constants in cpu.h diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h index 216e307ff7..ea5a4b545d 100644 --- a/cpukit/score/cpu/mips/rtems/score/mips.h +++ b/cpukit/score/cpu/mips/rtems/score/mips.h @@ -140,6 +140,78 @@ extern "C" { } while (0) + + +/* + * Access the Debug Cache Invalidate Control register + */ + +#define mips_get_dcic( _x ) \ + do { \ + asm volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \ + } while (0) + + +#define mips_set_dcic( _x ) \ + do { \ + register unsigned int __x = (_x); \ + asm volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \ + } while (0) + + + + +/* + * Access the Breakpoint Program Counter & Mask registers + * (_x for BPC, _y for mask) + */ + +#define mips_get_bpcrm( _x, _y ) \ + do { \ + asm volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \ + asm volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \ + } while (0) + + +#define mips_set_bpcrm( _x, _y ) \ + do { \ + register unsigned int __x = (_x); \ + register unsigned int __y = (_y); \ + asm volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \ + asm volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \ + } while (0) + + + + + + +/* + * Access the Breakpoint Data Address & Mask registers + * (_x for BDA, _y for mask) + */ + +#define mips_get_bdarm( _x, _y ) \ + do { \ + asm volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \ + asm volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \ + } while (0) + + +#define mips_set_bdarm( _x, _y ) \ + do { \ + register unsigned int __x = (_x); \ + register unsigned int __y = (_y); \ + asm volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \ + asm volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \ + } while (0) + + + + + + + /* * Access FCR31 */ -- cgit v1.2.3