From aa7f8a1f5d815ff836c3dc6c9af4bf01a163ce2b Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 14 Mar 2001 16:43:35 +0000 Subject: 2001-03-14 Joel Sherrill * cpu.c, rtems/score/cpu.h, rtems/score/mipstypes.h: Removed unused variable _CPU_Thread_dispatch_pointer and cleaned numerous comments. --- cpukit/score/cpu/mips/rtems/score/cpu.h | 47 +++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 20 deletions(-) (limited to 'cpukit/score/cpu/mips/rtems/score/cpu.h') diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h index baff16886c..03906e96b0 100644 --- a/cpukit/score/cpu/mips/rtems/score/cpu.h +++ b/cpukit/score/cpu/mips/rtems/score/cpu.h @@ -1,14 +1,22 @@ -/* cpu.h - * - * This include file contains information pertaining to the IDT 4650 - * processor. - * - * Author: Craig Lebakken - * - * COPYRIGHT (c) 1996 by Transition Networks Inc. - * - * To anyone who acknowledges that this file is provided "AS IS" - * without any express or implied warranty: +/* + * Mips CPU Dependent Header File + * + * Conversion to MIPS port by Alan Cudmore and + * Joel Sherrill . + * + * These changes made the code conditional on standard cpp predefines, + * merged the mips1 and mips3 code sequences as much as possible, + * and moved some of the assembly code to C. Alan did much of the + * initial analysis and rework. Joel took over from there and + * wrote the JMR3904 BSP so this could be tested. Joel also + * added the new interrupt vectoring support in libcpu and + * tried to better support the various interrupt controllers. + * + * Original MIP64ORION port by Craig Lebakken + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: * permission to use, copy, modify, and distribute this file * for any purpose is hereby granted without fee, provided that * the above copyright notice and this notice appears in all @@ -18,9 +26,7 @@ * Transition Networks makes no representations about the suitability * of this software for any purpose. * - * Derived from c/src/exec/score/cpu/no_cpu/cpu.h: - * - * COPYRIGHT (c) 1989-1999. + * COPYRIGHT (c) 1989-2001. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be @@ -29,7 +35,6 @@ * * $Id$ */ -/* @(#)cpu.h 08/29/96 1.7 */ #ifndef __CPU_h #define __CPU_h @@ -490,9 +495,12 @@ SCORE_EXTERN void *_CPU_Interrupt_stack_high; * and contains the address of the routine _Thread_Dispatch. This * can make it easier to invoke that routine at the end of the interrupt * sequence (if a dispatch is necessary). - */ + * SCORE_EXTERN void (*_CPU_Thread_dispatch_pointer)(); + * + * NOTE: Not needed on this port. + */ /* * Nothing prevents the porter from declaring more CPU specific variables. @@ -740,16 +748,15 @@ void _CPU_ISR_Set_level( unsigned32 ); /* in cpu.c */ * halts/stops the CPU. */ -void mips_fatal_error ( int error ); - #define _CPU_Fatal_halt( _error ) \ do { \ unsigned int _level; \ _CPU_ISR_Disable(_level); \ - mips_fatal_error(_error); \ + loop: goto loop; \ } while (0) -/* end of Fatal Error manager macros */ + +extern void mips_break( int error ); /* Bitfield handler macros */ -- cgit v1.2.3