From 18a5db205c296b9e3d83a1c7d107e29a996fb12f Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Wed, 3 Feb 2016 11:48:31 +0100
Subject: m68k: Avoid SCORE_EXTERN

Update #2559.
---
 cpukit/score/cpu/m68k/cpu.c             | 33 +++++++++++++++++++++++++++++++++
 cpukit/score/cpu/m68k/rtems/score/cpu.h | 29 +----------------------------
 2 files changed, 34 insertions(+), 28 deletions(-)

(limited to 'cpukit/score/cpu/m68k')

diff --git a/cpukit/score/cpu/m68k/cpu.c b/cpukit/score/cpu/m68k/cpu.c
index ad46c10e78..c50a63fda1 100644
--- a/cpukit/score/cpu/m68k/cpu.c
+++ b/cpukit/score/cpu/m68k/cpu.c
@@ -21,6 +21,39 @@
 #include <rtems/score/percpu.h>
 #include <rtems/score/tls.h>
 
+#if ( M68K_HAS_VBR == 0 )
+
+/*
+ * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
+ * pushed onto the stack. This is not is the same order as VBR processors.
+ * The ISR handler takes the format and uses it for dispatching the user
+ * handler.
+ */
+
+typedef struct {
+  uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
+  uint16_t   format_id;
+  uint16_t   jmp;                /* jmp  _ISR_Handlers */
+  uint32_t   isr_handler;
+} _CPU_ISR_handler_entry;
+
+#define M68K_MOVE_A7 0x3F3C
+#define M68K_JMP     0x4EF9
+
+/* points to jsr-exception-table in targets wo/ VBR register */
+static _CPU_ISR_handler_entry
+_CPU_ISR_jump_table[ CPU_INTERRUPT_NUMBER_OF_VECTORS ];
+
+#endif /* M68K_HAS_VBR */
+
+#if (M68K_HAS_FPSP_PACKAGE == 1)
+int (*_FPSP_install_raw_handler)(
+  uint32_t   vector,
+  proc_ptr new_handler,
+  proc_ptr *old_handler
+);
+#endif
+
 #if defined( __mcoldfire__ ) && ( M68K_HAS_FPU == 1 )
   uint32_t _CPU_cacr_shadow;
 #endif
diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h
index 8e0efa161f..06d711af48 100644
--- a/cpukit/score/cpu/m68k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h
@@ -313,33 +313,6 @@ typedef struct {
 
 extern void*                     _VBR;
 
-#if ( M68K_HAS_VBR == 0 )
-
-/*
- * Table of ISR handler entries that resides in RAM. The FORMAT/ID is
- * pushed onto the stack. This is not is the same order as VBR processors.
- * The ISR handler takes the format and uses it for dispatching the user
- * handler.
- *
- * FIXME : should be moved to below CPU_INTERRUPT_NUMBER_OF_VECTORS
- *
- */
-
-typedef struct {
-  uint16_t   move_a7;            /* move #FORMAT_ID,%a7@- */
-  uint16_t   format_id;
-  uint16_t   jmp;                /* jmp  _ISR_Handlers */
-  uint32_t   isr_handler;
-} _CPU_ISR_handler_entry;
-
-#define M68K_MOVE_A7 0x3F3C
-#define M68K_JMP     0x4EF9
-
-      /* points to jsr-exception-table in targets wo/ VBR register */
-SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256];
-
-#endif /* M68K_HAS_VBR */
-
 #endif /* ASM */
 
 /* constants */
@@ -764,7 +737,7 @@ static inline CPU_Counter_ticks _CPU_Counter_difference(
 
 void M68KFPSPInstallExceptionHandlers (void);
 
-SCORE_EXTERN int (*_FPSP_install_raw_handler)(
+extern int (*_FPSP_install_raw_handler)(
   uint32_t   vector,
   proc_ptr new_handler,
   proc_ptr *old_handler
-- 
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