From 5bb38e15667c03ef44420cdeb7889db42649ece3 Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Fri, 4 Dec 2009 05:25:30 +0000 Subject: Whitespace removal. --- cpukit/score/cpu/m68k/rtems/m68k/m68302.h | 4 +-- cpukit/score/cpu/m68k/rtems/m68k/qsm.h | 6 ++-- cpukit/score/cpu/m68k/rtems/m68k/sim.h | 8 +++--- cpukit/score/cpu/m68k/rtems/score/cpu.h | 12 ++++---- cpukit/score/cpu/m68k/rtems/score/m68k.h | 48 +++++++++++++++---------------- 5 files changed, 39 insertions(+), 39 deletions(-) (limited to 'cpukit/score/cpu/m68k/rtems') diff --git a/cpukit/score/cpu/m68k/rtems/m68k/m68302.h b/cpukit/score/cpu/m68k/rtems/m68k/m68302.h index d1d828e352..58abf1bdfc 100644 --- a/cpukit/score/cpu/m68k/rtems/m68k/m68302.h +++ b/cpukit/score/cpu/m68k/rtems/m68k/m68302.h @@ -227,7 +227,7 @@ enum m68302_ivec_e { * The DRAM refresh memory map replaces the SCC2 Tx BD 6 and Tx BD 7 * structures in the parameter RAM. * - * Access to the DRAM registers can be accomplished by + * Access to the DRAM registers can be accomplished by * the following approach: * * volatile m302_DRAM_refresh_t *dram; @@ -599,7 +599,7 @@ typedef struct { } m302_dualPortRAM_t; /* some useful defines the some of the registers above */ - + /* ---- MC68302 Chip Select Registers diff --git a/cpukit/score/cpu/m68k/rtems/m68k/qsm.h b/cpukit/score/cpu/m68k/rtems/m68k/qsm.h index b6bd8e0cf7..4ddf2a55ff 100644 --- a/cpukit/score/cpu/m68k/rtems/m68k/qsm.h +++ b/cpukit/score/cpu/m68k/rtems/m68k/qsm.h @@ -14,10 +14,10 @@ * * For more information, refer to Motorola's "Modular Microcontroller * Family Queued Serial Module Reference Manual" (Motorola document - * QSMRM/AD). + * QSMRM/AD). * * This file was created by John S. Gwynne to support Motorola's 68332 MCU. - * + * * Redistribution and use in source and binary forms are permitted * provided that the following conditions are met: * 1. Redistribution of source code and documentation must retain @@ -53,7 +53,7 @@ #undef SIM_MM #define SIM_MM 1 #define QSM_CRB 0xfffc00 -#endif +#endif #define QSMCR (volatile unsigned short int * const)(0x00 + QSM_CRB) diff --git a/cpukit/score/cpu/m68k/rtems/m68k/sim.h b/cpukit/score/cpu/m68k/rtems/m68k/sim.h index 8ca58d8b6b..5b60a3cefb 100644 --- a/cpukit/score/cpu/m68k/rtems/m68k/sim.h +++ b/cpukit/score/cpu/m68k/rtems/m68k/sim.h @@ -12,7 +12,7 @@ * () Clock signal generation for other intermodule bus (IMB) members * and external devices. * - * () The generation of chip-select signals that simplify external + * () The generation of chip-select signals that simplify external * circuitry interface. * * () Data ports that are available for general purpose input and @@ -22,10 +22,10 @@ * * For more information, refer to Motorola's "Modular Microcontroller * Family System Integration Module Reference Manual" (Motorola document - * SIMRM/AD). + * SIMRM/AD). * * This file was created by John S. Gwynne to support Motorola's 68332 MCU. - * + * * Redistribution and use in source and binary forms are permitted * provided that the following conditions are met: * 1. Redistribution of source code and documentation must retain @@ -215,7 +215,7 @@ used. These bits always read zero; write have no effect. CSPAR0 bit 1 always reads one; writes to CSPAR0 bit 1 have no effect. */ #define CSPAR1 SIM_VOLATILE_USHORT_POINTER(0x46 + SIM_CRB) - /* Chip Select Pin Assignment + /* Chip Select Pin Assignment Register 1 */ /* CSPAR1 contains five two-bit fields that determine the finctions of corresponding chip-select pins. CSPAR1[15:10] are not used. These diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h index 2cd8df062b..9b004ccfc6 100644 --- a/cpukit/score/cpu/m68k/rtems/score/cpu.h +++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h @@ -66,7 +66,7 @@ extern "C" { /* * Does the RTEMS invoke the user's ISR with the vector number and - * a pointer to the saved interrupt frame (1) or just the vector + * a pointer to the saved interrupt frame (1) or just the vector * number (0)? */ @@ -311,7 +311,7 @@ typedef struct { SCORE_EXTERN void *_CPU_Interrupt_stack_low; SCORE_EXTERN void *_CPU_Interrupt_stack_high; -extern void* _VBR; +extern void* _VBR; #if ( M68K_HAS_VBR == 0 ) @@ -336,7 +336,7 @@ typedef struct { #define M68K_JMP 0x4EF9 /* points to jsr-exception-table in targets wo/ VBR register */ -SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; +SCORE_EXTERN _CPU_ISR_handler_entry _CPU_ISR_jump_table[256]; #endif /* M68K_HAS_VBR */ @@ -659,10 +659,10 @@ void _CPU_Initialize(void); /* * _CPU_ISR_install_raw_handler * - * This routine installs a "raw" interrupt handler directly into the + * This routine installs a "raw" interrupt handler directly into the * processor's vector table. */ - + void _CPU_ISR_install_raw_handler( uint32_t vector, proc_ptr new_handler, @@ -724,7 +724,7 @@ void _CPU_Context_restore_fp( /* * Hooks for the Floating Point Support Package (FPSP) provided by Motorola * - * NOTES: + * NOTES: * * Motorola 68k family CPU's before the 68040 used a coprocessor * (68881 or 68882) to handle floating point. The 68040 has internal diff --git a/cpukit/score/cpu/m68k/rtems/score/m68k.h b/cpukit/score/cpu/m68k/rtems/score/m68k.h index b051d8405a..17af5fd92c 100644 --- a/cpukit/score/cpu/m68k/rtems/score/m68k.h +++ b/cpukit/score/cpu/m68k/rtems/score/m68k.h @@ -71,9 +71,9 @@ extern "C" { * implement the output buffer impedance selection mode of operation." * * M68K_HAS_EXTB_L is used to enable/disable usage of the extb.l instruction - * which is not available for 68000 or 68ec000 cores (68000, 68001, 68008, + * which is not available for 68000 or 68ec000 cores (68000, 68001, 68008, * 68010, 68302, 68306, 68307). This instruction is available on the 68020 - * up and the cpu32 based models. + * up and the cpu32 based models. * * M68K_HAS_MISALIGNED is non-zero if the CPU allows byte-misaligned * data access (68020, 68030, 68040, 68060, CPU32+). @@ -91,7 +91,7 @@ extern "C" { # define CPU_NAME "Motorola ColdFire" # if defined(__mcfisaa__) -/* Motorola ColdFire ISA A */ +/* Motorola ColdFire ISA A */ # define CPU_MODEL_NAME "mcfisaa" # define M68K_HAS_VBR 1 # define M68K_HAS_BFFFO 0 @@ -101,7 +101,7 @@ extern "C" { # define M68K_HAS_MISALIGNED 1 # elif defined(__mcfisaaplus__) -/* Motorola ColdFire ISA A+ */ +/* Motorola ColdFire ISA A+ */ # define CPU_MODEL_NAME "mcfisaaplus" # define M68K_HAS_VBR 1 # define M68K_HAS_BFFFO 0 @@ -111,7 +111,7 @@ extern "C" { # define M68K_HAS_MISALIGNED 1 # elif defined(__mcfisab__) -/* Motorola ColdFire ISA B */ +/* Motorola ColdFire ISA B */ # define CPU_MODEL_NAME "mcfisab" # define M68K_HAS_VBR 1 # define M68K_HAS_BFFFO 0 @@ -169,8 +169,8 @@ extern "C" { #else /* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. Notice the only exception to this is that + * Figure out all CPU Model Feature Flags based upon compiler + * predefines. Notice the only exception to this is that * gcc does not distinguish between CPU32 and CPU32+. This * feature selection logic is setup such that if RTEMS__mcpu32p__ * is defined, then CPU32+ rules are used. Otherwise, the safe @@ -181,7 +181,7 @@ extern "C" { /* * One stack size fits all 68000 processors. - */ + */ # define M68K_CPU_STACK_MINIMUM_SIZE 4096 # if (defined(__mc68020__) && !defined(__mcpu32__)) @@ -200,9 +200,9 @@ extern "C" { # define M68K_HAS_FPU 0 # define M68K_HAS_FPSP_PACKAGE 0 # endif - + # elif defined(__mc68030__) - + # define CPU_MODEL_NAME "m68030" # define M68K_HAS_VBR 1 # define M68K_HAS_SEPARATE_STACKS 1 @@ -217,7 +217,7 @@ extern "C" { # define M68K_HAS_FPU 0 # define M68K_HAS_FPSP_PACKAGE 0 # endif - + # elif defined(__mc68040__) # define CPU_MODEL_NAME "m68040" @@ -234,7 +234,7 @@ extern "C" { # define M68K_HAS_FPU 0 # define M68K_HAS_FPSP_PACKAGE 0 # endif - + # elif defined(__mc68060__) # define CPU_MODEL_NAME "m68060" @@ -251,7 +251,7 @@ extern "C" { # define M68K_HAS_FPU 0 # define M68K_HAS_FPSP_PACKAGE 0 # endif - + # elif defined(__mc68302__) # define CPU_MODEL_NAME "m68302" @@ -266,7 +266,7 @@ extern "C" { /* gcc and egcs do not distinguish between CPU32 and CPU32+ */ # elif defined(RTEMS__mcpu32p__) - + # define CPU_MODEL_NAME "mcpu32+" # define M68K_HAS_VBR 1 # define M68K_HAS_SEPARATE_STACKS 0 @@ -278,7 +278,7 @@ extern "C" { # define M68K_HAS_FPSP_PACKAGE 0 # elif defined(__mcpu32__) - + # define CPU_MODEL_NAME "mcpu32" # define M68K_HAS_VBR 1 # define M68K_HAS_SEPARATE_STACKS 0 @@ -290,7 +290,7 @@ extern "C" { # define M68K_HAS_FPSP_PACKAGE 0 # elif defined(__mc68000__) - + # define CPU_MODEL_NAME "m68000" # define M68K_HAS_VBR 0 # define M68K_HAS_SEPARATE_STACKS 0 @@ -376,7 +376,7 @@ extern "C" { asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ _level = (_tmpsr & 0x0700) >> 8; \ } while (0) - + #define m68k_set_interrupt_level( _newlevel ) \ do { \ register uint32_t _tmpsr; \ @@ -394,7 +394,7 @@ extern "C" { asm volatile ( "movec %0,%%vbr " : : "r" (vbr)) #elif ( defined(__mcoldfire__) ) -extern void* _VBR; +extern void* _VBR; #define m68k_get_vbr( _vbr ) _vbr = &_VBR #define m68k_set_vbr( _vbr ) \ @@ -402,7 +402,7 @@ extern void* _VBR; asm volatile ( "movec %0,%%vbr " : : "r" (_vbr)); \ _VBR = (void *)_vbr; \ } while(0) - + #else #define m68k_get_vbr( _vbr ) _vbr = (void *)_VBR #define m68k_set_vbr( _vbr ) @@ -429,23 +429,23 @@ static inline uint32_t m68k_swap_u32( ) { uint32_t byte1, byte2, byte3, byte4, swapped; - + byte4 = (value >> 24) & 0xff; byte3 = (value >> 16) & 0xff; byte2 = (value >> 8) & 0xff; byte1 = value & 0xff; - + swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4; return( swapped ); } - + static inline uint16_t m68k_swap_u16( uint16_t value ) { return (((value & 0xff) << 8) | ((value >> 8) & 0xff)); } - + #else static inline uint32_t m68k_swap_u32( @@ -484,7 +484,7 @@ static inline uint16_t m68k_swap_u16( * * This function is used to map virtual addresses to physical * addresses. - * + * * FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE * PHYSICAL ADDRESSES */ -- cgit v1.2.3