From bc85fd5a6df8753543ba55c98a588e255471752b Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Tue, 11 Jul 2000 19:31:04 +0000 Subject: Reworked score/cpu/i960 so it can be safely compiled multilib. All routines and structures that require CPU model specific information are now in libcpu. This required significant rework of the score/cpu header files and the creation of multiple header files and subdirectories in libcpu/i960. --- cpukit/score/cpu/i960/rtems/score/i960.h | 408 ++----------------------------- 1 file changed, 26 insertions(+), 382 deletions(-) (limited to 'cpukit/score/cpu/i960/rtems/score/i960.h') diff --git a/cpukit/score/cpu/i960/rtems/score/i960.h b/cpukit/score/cpu/i960/rtems/score/i960.h index de7b635869..799d493279 100644 --- a/cpukit/score/cpu/i960/rtems/score/i960.h +++ b/cpukit/score/cpu/i960/rtems/score/i960.h @@ -33,314 +33,60 @@ extern "C" { * NOTE: RTEMS defines a canonical name for each cpu model. */ -#if defined(rtems_multilib) /* - * Figure out all CPU Model Feature Flags based upon compiler - * predefines. + * Define the name of the CPU family. */ -#define CPU_MODEL_NAME "rtems_multilib" -#define I960_HAS_FPU 0 -#define I960_CPU_ALIGNMENT 4 -#define I960_SOFT_RESET_COMMAND 0x30000 - -#elif defined(__i960CA__) || defined(__i960_CA__) || defined(__i960CA) - -#define CPU_MODEL_NAME "i960ca" -#define __RTEMS_I960CA__ - -#elif defined(__i960KA__) -#define CPU_MODEL_NAME "i960ka" - -#elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA) - -#define CPU_MODEL_NAME "i960ha" -#define __RTEMS_I960HA__ - -#elif defined(__i960RP__) - -#include -#define CPU_MODEL_NAME "i960rp" -#define __RTEMS_I960RP__ -#define I960_CPU_ALIGNMENT 8 -#define I960_SOFT_RESET_COMMAND 0x300 - -#else - -#error "Unsupported CPU Model" - -#endif +#define CPU_NAME "Intel i960" /* - * Now default some CPU model variation parameters + * This should work since most i960 models do not have FPUs. The logic is: + * + * + If the user specifically asks for soft-float, give it to them + * regardless of hardware availability. + * + If the CPU has hardware FPU, then use it. + * + Otherwise, we have to use soft float. */ -#ifndef I960_HAS_FPU +#if defined(_SOFT_FLOAT) +#define I960_HAS_FPU 0 +#elif defined(_i960_KB__) || defined(_i960_SB__) || defined(_i960_SB__) || \ + defined(_i960_JF__) || defined(_i960_MC__) || defined(_i960_CC__) +#define I960_HAS_FPU 1 +#else #define I960_HAS_FPU 0 -#endif - -#ifndef I960_CPU_ALIGNMENT -#define I960_CPU_ALIGNMENT 4 -#endif - -#ifndef I960_SOFT_RESET_COMMAND -#define I960_SOFT_RESET_COMMAND 0x30000 #endif /* - * Define the name of the CPU family. + * Some of the CPU models may have better performance with + * alignment of 8 or 16 but we don't know what model we are + * being compiled for based solely on the information provided + * when multilibbing. */ -#define CPU_NAME "Intel i960" - -#ifndef ASM +#define I960_CPU_ALIGNMENT 4 /* - * XXX should have an ifdef here and have stuff for the other - * XXX family members... - */ - -#if defined(__RTEMS_I960CA__) -/* - * Now default some CPU model variation parameters + * This is not the perfect CPU model name but it is adequate and + * reflects what we know from multilib. */ -#ifndef I960_HAS_FPU -#define I960_HAS_FPU 0 -#endif - -#ifndef I960_CPU_ALIGNMENT -#define I960_CPU_ALIGNMENT 4 -#endif - - -/* i960CA control structures */ - -/* Intel i960CA Control Table */ - -typedef struct { - /* Control Group 0 */ - unsigned int ipb0; /* IP breakpoint 0 */ - unsigned int ipb1; /* IP breakpoint 1 */ - unsigned int dab0; /* data address breakpoint 0 */ - unsigned int dab1; /* data address breakpoint 1 */ - /* Control Group 1 */ - unsigned int imap0; /* interrupt map 0 */ - unsigned int imap1; /* interrupt map 1 */ - unsigned int imap2; /* interrupt map 2 */ - unsigned int icon; /* interrupt control */ - /* Control Group 2 */ - unsigned int mcon0; /* memory region 0 configuration */ - unsigned int mcon1; /* memory region 1 configuration */ - unsigned int mcon2; /* memory region 2 configuration */ - unsigned int mcon3; /* memory region 3 configuration */ - /* Control Group 3 */ - unsigned int mcon4; /* memory region 4 configuration */ - unsigned int mcon5; /* memory region 5 configuration */ - unsigned int mcon6; /* memory region 6 configuration */ - unsigned int mcon7; /* memory region 7 configuration */ - /* Control Group 4 */ - unsigned int mcon8; /* memory region 8 configuration */ - unsigned int mcon9; /* memory region 9 configuration */ - unsigned int mcon10; /* memory region 10 configuration */ - unsigned int mcon11; /* memory region 11 configuration */ - /* Control Group 5 */ - unsigned int mcon12; /* memory region 12 configuration */ - unsigned int mcon13; /* memory region 13 configuration */ - unsigned int mcon14; /* memory region 14 configuration */ - unsigned int mcon15; /* memory region 15 configuration */ - /* Control Group 6 */ - unsigned int reserved; /* reserved */ - unsigned int bpcon; /* breakpoint control */ - unsigned int tc; /* trace control */ - unsigned int bcon; /* bus configuration control */ -} i960ca_control_table; - -/* Intel i960CA Processor Control Block */ - -typedef struct { - unsigned int *fault_tbl; /* fault table base address */ - i960ca_control_table - *control_tbl; /* control table base address */ - unsigned int initial_ac; /* AC register initial value */ - unsigned int fault_config; /* fault configuration word */ - void **intr_tbl; /* interrupt table base address */ - void *sys_proc_tbl; /* system procedure table - base address */ - unsigned int reserved; /* reserved */ - unsigned int *intr_stack; /* interrupt stack pointer */ - unsigned int ins_cache_cfg; /* instruction cache - configuration word */ - unsigned int reg_cache_cfg; /* register cache configuration word */ -} i960ca_PRCB; - -typedef i960ca_control_table i960_control_table; -typedef i960ca_PRCB i960_PRCB; - -#elif defined(__RTEMS_I960HA__) - -/* i960HA control structures */ - -/* Intel i960HA Control Table */ - -typedef struct { - /* Control Group 0 */ - unsigned int ipb0; /* IP breakpoint 0 */ - unsigned int ipb1; /* IP breakpoint 1 */ - unsigned int dab0; /* data address breakpoint 0 */ - unsigned int dab1; /* data address breakpoint 1 */ - /* Control Group 1 */ - unsigned int imap0; /* interrupt map 0 */ - unsigned int imap1; /* interrupt map 1 */ - unsigned int imap2; /* interrupt map 2 */ - unsigned int icon; /* interrupt control */ - /* Control Group 2 */ - unsigned int mcon0; /* memory region 0 configuration */ - unsigned int mcon1; /* memory region 1 configuration */ - unsigned int mcon2; /* memory region 2 configuration */ - unsigned int mcon3; /* memory region 3 configuration */ - /* Control Group 3 */ - unsigned int mcon4; /* memory region 4 configuration */ - unsigned int mcon5; /* memory region 5 configuration */ - unsigned int mcon6; /* memory region 6 configuration */ - unsigned int mcon7; /* memory region 7 configuration */ - /* Control Group 4 */ - unsigned int mcon8; /* memory region 8 configuration */ - unsigned int mcon9; /* memory region 9 configuration */ - unsigned int mcon10; /* memory region 10 configuration */ - unsigned int mcon11; /* memory region 11 configuration */ - /* Control Group 5 */ - unsigned int mcon12; /* memory region 12 configuration */ - unsigned int mcon13; /* memory region 13 configuration */ - unsigned int mcon14; /* memory region 14 configuration */ - unsigned int mcon15; /* memory region 15 configuration */ - /* Control Group 6 */ - unsigned int reserved; /* reserved */ - unsigned int bpcon; /* breakpoint control */ - unsigned int tc; /* trace control */ - unsigned int bcon; /* bus configuration control */ -} i960ha_control_table; - -/* Intel i960HA Processor Control Block */ - -typedef struct { - unsigned int *fault_tbl; /* fault table base address */ - i960ha_control_table - *control_tbl; /* control table base address */ - unsigned int initial_ac; /* AC register initial value */ - unsigned int fault_config; /* fault configuration word */ - void **intr_tbl; /* interrupt table base address */ - void *sys_proc_tbl; /* system procedure table - base address */ - unsigned int reserved; /* reserved */ - unsigned int *intr_stack; /* interrupt stack pointer */ - unsigned int ins_cache_cfg; /* instruction cache - configuration word */ - unsigned int reg_cache_cfg; /* register cache configuration word */ -} i960ha_PRCB; - -typedef i960ha_control_table i960_control_table; -typedef i960ha_PRCB i960_PRCB; - -#elif defined(__RTEMS_I960RP__) - -/* i960RP control structures */ - -/* Intel i960RP Control Table */ - -typedef struct { - /* Control Group 0 */ - unsigned int rsvd00; - unsigned int rsvd01; - unsigned int rsvd02; - unsigned int rsvd03; - /* Control Group 1 */ - unsigned int imap0; /* interrupt map 0 */ - unsigned int imap1; /* interrupt map 1 */ - unsigned int imap2; /* interrupt map 2 */ - unsigned int icon; /* interrupt control */ - /* Control Group 2 */ - unsigned int pmcon0; /* memory region 0 configuration */ - unsigned int rsvd1; - unsigned int pmcon2; /* memory region 2 configuration */ - unsigned int rsvd2; - /* Control Group 3 */ - unsigned int pmcon4; /* memory region 4 configuration */ - unsigned int rsvd3; - unsigned int pmcon6; /* memory region 6 configuration */ - unsigned int rsvd4; - /* Control Group 4 */ - unsigned int pmcon8; /* memory region 8 configuration */ - unsigned int rsvd5; - unsigned int pmcon10; /* memory region 10 configuration */ - unsigned int rsvd6; - /* Control Group 5 */ - unsigned int pmcon12; /* memory region 12 configuration */ - unsigned int rsvd7; - unsigned int pmcon14; /* memory region 14 configuration */ - unsigned int rsvd8; - /* Control Group 6 */ - unsigned int rsvd9; - unsigned int rsvd10; - unsigned int tc; /* trace control */ - unsigned int bcon; /* bus configuration control */ -} i960rp_control_table; - -/* Intel i960RP Processor Control Block */ - -typedef struct { - unsigned int *fault_tbl; /* fault table base address */ - i960rp_control_table - *control_tbl; /* control table base address */ - unsigned int initial_ac; /* AC register initial value */ - unsigned int fault_config; /* fault configuration word */ - void **intr_tbl; /* interrupt table base address */ - void *sys_proc_tbl; /* system procedure table - base address */ - unsigned int reserved; /* reserved */ - unsigned int *intr_stack; /* interrupt stack pointer */ - unsigned int ins_cache_cfg; /* instruction cache - configuration word */ - unsigned int reg_cache_cfg; /* register cache configuration word */ -} i960rp_PRCB; - -typedef i960rp_control_table i960_control_table; -typedef i960rp_PRCB i960_PRCB; - -#elif defined(__i960KA__) - -/* i960KA control structures */ - -/* Intel i960KA Control Table */ - -typedef struct { -int pad0; -} i960ka_control_table; - -/* Intel i960KA Processor Control Block */ - -typedef struct { - void **intr_tbl; /* interrupt table base address */ - unsigned int *intr_stack; /* interrupt stack pointer */ -} i960ka_PRCB; - -typedef i960ka_control_table i960_control_table; -typedef i960ka_PRCB i960_PRCB; - +#if I960_HAS_FPU +#define CPU_MODEL_NAME "i960 w/FPU" #else -#error "invalid processor selection!" +#define CPU_MODEL_NAME "i960 w/soft-float" #endif +#ifndef ASM + /* * Miscellaneous Support Routines */ -#if !defined(__i960KA__) #define i960_reload_ctl_group( group ) \ { register int _cmd = ((group)|0x400) ; \ asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \ } -#endif #define i960_atomic_modify( mask, addr, prev ) \ { register unsigned int _mask = (mask); \ @@ -393,123 +139,21 @@ typedef i960ka_PRCB i960_PRCB; (_level) = ((_level) & 0x1f0000) >> 16; \ } while ( 0 ) -#if !defined(__i960KA__) #define i960_cause_intr( intr ) \ { register int _intr = (intr); \ asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \ } -#endif /* * Interrupt Masking Routines */ -#if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__) - -#define i960_unmask_intr( xint ) \ - { register unsigned int _mask= (1<<(xint)); \ - asm volatile( "or sf1,%0,sf1" : "=d" (_mask) : "0" (_mask) ); \ - } - -#define i960_mask_intr( xint ) \ - { register unsigned int _mask= (1<<(xint)); \ - asm volatile( "andnot %0,sf1,sf1" : "=d" (_mask) : "0" (_mask) ); \ - } - -#define i960_clear_intr( xint ) \ - { register unsigned int _xint=(xint); \ -asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \ - bbs %0,sf0, loop_til_cleared" \ - : "=d" (_xint) : "0" (_xint) ); \ - } - -static inline unsigned int i960_pend_intrs() -{ register unsigned int _intr=0; - asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) ); - return ( _intr ); -} - -static inline unsigned int i960_mask_intrs() -{ register unsigned int _intr=0; - asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) ); - return( _intr ); -} - -#elif defined(__RTEMS_I960RP__) - -#define i960_unmask_intr( xint ) \ - { register unsigned int _mask= (1<<(xint)); \ - register unsigned int *_imsk = (int * ) IMSK_ADDR; \ - register unsigned int _val= *_imsk; \ - asm volatile( "or %0,%2,%0; \ - st %0,(%1)" \ - : "=d" (_val), "=d" (_imsk), "=d" (_mask) \ - : "0" (_val), "1" (_imsk), "2" (_mask) ); \ - } - -#define i960_mask_intr( xint ) \ - { register unsigned int _mask= (1<<(xint)); \ - register unsigned int *_imsk = (int * ) IMSK_ADDR; \ - register unsigned int _val = *_imsk; \ - asm volatile( "andnot %2,%0,%0; \ - st %0,(%1)" \ - : "=d" (_val), "=d" (_imsk), "=d" (_mask) \ - : "0" (_val), "1" (_imsk), "2" (_mask) ); \ - } -#define i960_clear_intr( xint ) \ - { register unsigned int _xint=xint; \ - register unsigned int _mask=(1<<(xint)); \ - register unsigned int *_ipnd = (int * ) IPND_ADDR; \ - register unsigned int _rslt = 0; \ -asm volatile( "loop_til_cleared: mov 0, %0; \ - atmod %1, %2, %0; \ - bbs %3,%0, loop_til_cleared" \ - : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \ - : "0" (_rslt), "1" (_ipnd), "2" (_mask), "3" (_xint) ); \ - } - -static inline unsigned int i960_pend_intrs() -{ register unsigned int _intr= *(unsigned int *) IPND_ADDR; - /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \ - asm volatile( "mov (%0),%1" \ - : "=d" (_ipnd), "=d" (_mask) \ - : "0" (_ipnd), "1" (_mask) ); \ */ - return ( _intr ); -} - -static inline unsigned int i960_mask_intrs() -{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR; - /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/ - return( _intr ); -} -#endif - static inline unsigned int i960_get_fp() { register unsigned int _fp=0; asm volatile( "mov fp,%0" : "=d" (_fp) : "0" (_fp) ); return ( _fp ); } -/* - * Soft Reset - */ - -#if defined(I960_SOFT_RESET_COMMAND) -#define i960_soft_reset( prcb ) \ - { register i960_PRCB *_prcb = (prcb); \ - register unsigned int *_next=0; \ - register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \ - asm volatile( "lda next,%1; \ - sysctl %0,%1,%2; \ - next: mov g0,g0" \ - : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ - : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ - } - -#elif !defined(__i960KA__) -#warning "I960_SOFT_RESET_COMMAND is not defined" -#endif - /* * The following routine swaps the endian format of an unsigned int. * It must be static because it is referenced indirectly. -- cgit v1.2.3