From 702c5f5b42e975c35a94f1ae3d39a77815f36f70 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 27 Oct 1999 15:29:18 +0000 Subject: The rxgen960 BSP and i960 RPM support was submitted by Mark Bronson of RAMIX. --- cpukit/score/cpu/i960/rtems/score/i960.h | 241 ++++++++++++++++++++++++++----- 1 file changed, 205 insertions(+), 36 deletions(-) (limited to 'cpukit/score/cpu/i960/rtems/score/i960.h') diff --git a/cpukit/score/cpu/i960/rtems/score/i960.h b/cpukit/score/cpu/i960/rtems/score/i960.h index bb4884941a..3719d96496 100644 --- a/cpukit/score/cpu/i960/rtems/score/i960.h +++ b/cpukit/score/cpu/i960/rtems/score/i960.h @@ -38,13 +38,19 @@ extern "C" { #define CPU_MODEL_NAME "i960ca" #define __RTEMS_I960CA__ -#define I960_HAS_FPU 0 #elif defined(__i960HA__) || defined(__i960_HA__) || defined(__i960HA) #define CPU_MODEL_NAME "i960ha" #define __RTEMS_I960HA__ -#define I960_HAS_FPU 0 + +#elif defined(__i960RP__) + +#include +#define CPU_MODEL_NAME "i960rp" +#define __RTEMS_I960RP__ +#define I960_CPU_ALIGNMENT 8 +#define I960_SOFT_RESET_COMMAND 0x300 #else @@ -52,6 +58,22 @@ extern "C" { #endif +/* + * Now default some CPU model variation parameters + */ + +#ifndef I960_HAS_FPU +#define I960_HAS_FPU 0 +#endif + +#ifndef I960_CPU_ALIGNMENT +#define I960_CPU_ALIGNMENT 4 +#endif + +#ifndef I960_SOFT_RESET_COMMAND +#define I960_SOFT_RESET_COMMAND 0x30000 +#endif + /* * Define the name of the CPU family. */ @@ -66,6 +88,18 @@ extern "C" { */ #if defined(__RTEMS_I960CA__) +/* + * Now default some CPU model variation parameters + */ + +#ifndef I960_HAS_FPU +#define I960_HAS_FPU 0 +#endif + +#ifndef I960_CPU_ALIGNMENT +#define I960_CPU_ALIGNMENT 4 +#endif + /* i960CA control structures */ @@ -195,8 +229,101 @@ typedef struct { typedef i960ha_control_table i960_control_table; typedef i960ha_PRCB i960_PRCB; +#elif defined(__RTEMS_I960RP__) + +/* i960RP control structures */ + +/* Intel i960RP Control Table */ + +typedef struct { + /* Control Group 0 */ + unsigned int rsvd00; + unsigned int rsvd01; + unsigned int rsvd02; + unsigned int rsvd03; + /* Control Group 1 */ + unsigned int imap0; /* interrupt map 0 */ + unsigned int imap1; /* interrupt map 1 */ + unsigned int imap2; /* interrupt map 2 */ + unsigned int icon; /* interrupt control */ + /* Control Group 2 */ + unsigned int pmcon0; /* memory region 0 configuration */ + unsigned int rsvd1; + unsigned int pmcon2; /* memory region 2 configuration */ + unsigned int rsvd2; + /* Control Group 3 */ + unsigned int pmcon4; /* memory region 4 configuration */ + unsigned int rsvd3; + unsigned int pmcon6; /* memory region 6 configuration */ + unsigned int rsvd4; + /* Control Group 4 */ + unsigned int pmcon8; /* memory region 8 configuration */ + unsigned int rsvd5; + unsigned int pmcon10; /* memory region 10 configuration */ + unsigned int rsvd6; + /* Control Group 5 */ + unsigned int pmcon12; /* memory region 12 configuration */ + unsigned int rsvd7; + unsigned int pmcon14; /* memory region 14 configuration */ + unsigned int rsvd8; + /* Control Group 6 */ + unsigned int rsvd9; + unsigned int rsvd10; + unsigned int tc; /* trace control */ + unsigned int bcon; /* bus configuration control */ +} i960rp_control_table; + +/* Intel i960RP Processor Control Block */ + +typedef struct { + unsigned int *fault_tbl; /* fault table base address */ + i960rp_control_table + *control_tbl; /* control table base address */ + unsigned int initial_ac; /* AC register initial value */ + unsigned int fault_config; /* fault configuration word */ + void **intr_tbl; /* interrupt table base address */ + void *sys_proc_tbl; /* system procedure table + base address */ + unsigned int reserved; /* reserved */ + unsigned int *intr_stack; /* interrupt stack pointer */ + unsigned int ins_cache_cfg; /* instruction cache + configuration word */ + unsigned int reg_cache_cfg; /* register cache configuration word */ +} i960rp_PRCB; + +typedef i960rp_control_table i960_control_table; +typedef i960rp_PRCB i960_PRCB; + +#else +#error "invalid processor selection!" #endif +/* + * Miscellaneous Support Routines + */ + +#define i960_reload_ctl_group( group ) \ + { register int _cmd = ((group)|0x400) ; \ + asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \ + } + +#define i960_atomic_modify( mask, addr, prev ) \ + { register unsigned int _mask = (mask); \ + register unsigned int *_addr = (unsigned int *)(addr); \ + asm volatile( "atmod %0,%1,%1" \ + : "=d" (_addr), "=d" (_mask) \ + : "0" (_addr), "1" (_mask) ); \ + (prev) = _mask; \ + } + +#define atomic_modify( _mask, _address, _previous ) \ + i960_atomic_modify( _mask, _address, _previous ) + +#define i960_enable_tracing() \ + { register unsigned int _pc = 0x1; \ + asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \ + } + /* * Interrupt Level Routines */ @@ -231,23 +358,16 @@ typedef i960ha_PRCB i960_PRCB; (_level) = ((_level) & 0x1f0000) >> 16; \ } while ( 0 ) -#define i960_atomic_modify( mask, addr, prev ) \ - { register unsigned int _mask = (mask); \ - register unsigned int *_addr = (unsigned int *)(addr); \ - asm volatile( "atmod %0,%1,%1" \ - : "=d" (_addr), "=d" (_mask) \ - : "0" (_addr), "1" (_mask) ); \ - (prev) = _mask; \ +#define i960_cause_intr( intr ) \ + { register int _intr = (intr); \ + asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \ } +/* + * Interrupt Masking Routines + */ -#define atomic_modify( _mask, _address, _previous ) \ - i960_atomic_modify( _mask, _address, _previous ) - -#define i960_enable_tracing() \ - { register unsigned int _pc = 0x1; \ - asm volatile( "modpc 0,%0,%0" : "=d" (_pc) : "0" (_pc) ); \ - } +#if defined(__RTEMS_I960CA__) || defined(__RTEMS_I960HA__) #define i960_unmask_intr( xint ) \ { register unsigned int _mask= (1<<(xint)); \ @@ -266,38 +386,66 @@ asm volatile( "loop_til_cleared: clrbit %0,sf0,sf0 ; \ : "=d" (_xint) : "0" (_xint) ); \ } -#define i960_reload_ctl_group( group ) \ - { register int _cmd = ((group)|0x400) ; \ - asm volatile( "sysctl %0,%0,%0" : "=d" (_cmd) : "0" (_cmd) ); \ - } +static inline unsigned int i960_pend_intrs() +{ register unsigned int _intr=0; + asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) ); + return ( _intr ); +} -#define i960_cause_intr( intr ) \ - { register int _intr = (intr); \ - asm volatile( "sysctl %0,%0,%0" : "=d" (_intr) : "0" (_intr) ); \ +static inline unsigned int i960_mask_intrs() +{ register unsigned int _intr=0; + asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) ); + return( _intr ); +} + +#elif defined(__RTEMS_I960RP__) + +#define i960_unmask_intr( xint ) \ + { register unsigned int _mask= (1<<(xint)); \ + register unsigned int *_imsk = (int * ) IMSK_ADDR; \ + register unsigned int _val= *_imsk; \ + asm volatile( "or %0,%2,%0; \ + st %0,(%1)" \ + : "=d" (_val), "=d" (_imsk), "=d" (_mask) \ + : "0" (_val), "1" (_imsk), "2" (_mask) ); \ } -#define i960_soft_reset( prcb ) \ - { register i960ca_PRCB *_prcb = (prcb); \ - register unsigned int *_next=0; \ - register unsigned int _cmd = 0x30000; \ - asm volatile( "lda next,%1; \ - sysctl %0,%1,%2; \ - next: mov g0,g0" \ - : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ - : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ +#define i960_mask_intr( xint ) \ + { register unsigned int _mask= (1<<(xint)); \ + register unsigned int *_imsk = (int * ) IMSK_ADDR; \ + register unsigned int _val = *_imsk; \ + asm volatile( "andnot %2,%0,%0; \ + st %0,(%1)" \ + : "=d" (_val), "=d" (_imsk), "=d" (_mask) \ + : "0" (_val), "1" (_imsk), "2" (_mask) ); \ + } +#define i960_clear_intr( xint ) \ + { register unsigned int _xint=xint; \ + register unsigned int _mask=(1<<(xint)); \ + register unsigned int *_ipnd = (int * ) IPND_ADDR; \ + register unsigned int _rslt = 0; \ +asm volatile( "loop_til_cleared: mov 0, %0; \ + atmod %1, %2, %0; \ + bbs %3,%0, loop_til_cleared" \ + : "=d" (_rslt), "=d" (_ipnd), "=d" (_mask), "=d" (_xint) \ + : "0" (_rslt), "1" (_ipnd), "2" (_mask), "3" (_xint) ); \ } static inline unsigned int i960_pend_intrs() -{ register unsigned int _intr=0; - asm volatile( "mov sf0,%0" : "=d" (_intr) : "0" (_intr) ); +{ register unsigned int _intr= *(unsigned int *) IPND_ADDR; + /*register unsigned int *_ipnd = (int * ) IPND_ADDR; \ + asm volatile( "mov (%0),%1" \ + : "=d" (_ipnd), "=d" (_mask) \ + : "0" (_ipnd), "1" (_mask) ); \ */ return ( _intr ); } static inline unsigned int i960_mask_intrs() -{ register unsigned int _intr=0; - asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) ); +{ register unsigned int _intr= *(unsigned int *) IMSK_ADDR; + /*asm volatile( "mov sf1,%0" : "=d" (_intr) : "0" (_intr) );*/ return( _intr ); } +#endif static inline unsigned int i960_get_fp() { register unsigned int _fp=0; @@ -305,6 +453,27 @@ static inline unsigned int i960_get_fp() return ( _fp ); } +/* + * Soft Reset + */ + +#if defined(I960_SOFT_RESET_COMMAND) + +#define i960_soft_reset( prcb ) \ + { register i960_PRCB *_prcb = (prcb); \ + register unsigned int *_next=0; \ + register unsigned int _cmd = I960_SOFT_RESET_COMMAND; \ + asm volatile( "lda next,%1; \ + sysctl %0,%1,%2; \ + next: mov g0,g0" \ + : "=d" (_cmd), "=d" (_next), "=d" (_prcb) \ + : "0" (_cmd), "1" (_next), "2" (_prcb) ); \ + } + +#else +#warning "I960_SOFT_RESET_COMMAND is not defined" +#endif + /* * The following routine swaps the endian format of an unsigned int. * It must be static because it is referenced indirectly. -- cgit v1.2.3