From 20d82377a679e5207328943ff5d1b3ad253d1feb Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 4 Sep 2020 20:10:57 +0200 Subject: arm: Fix arm_cp15_set_translation_table_entries() In a multi-processor system we must broadcast the TLB maintenance operation to the Inner Shareable domain to ensure that the other processors update their TLB caches accordingly. Close #4068. --- cpukit/score/cpu/arm/include/libcpu/arm-cp15.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) (limited to 'cpukit/score/cpu/arm') diff --git a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h index 8d43ca0ac2..6097d60ba6 100644 --- a/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h +++ b/cpukit/score/cpu/arm/include/libcpu/arm-cp15.h @@ -646,6 +646,22 @@ arm_cp15_tlb_invalidate_entry_all_asids(const void *mva) ); } +ARM_CP15_TEXT_SECTION static inline void +arm_cp15_tlb_invalidate_entry_all_asids_inner_shareable(const void *mva) +{ + ARM_SWITCH_REGISTERS; + + mva = ARM_CP15_TLB_PREPARE_MVA(mva); + + __asm__ volatile ( + ARM_SWITCH_TO_ARM + "mcr p15, 0, %[mva], c8, c3, 3\n" + ARM_SWITCH_BACK + : ARM_SWITCH_OUTPUT + : [mva] "r" (mva) + ); +} + ARM_CP15_TEXT_SECTION static inline void arm_cp15_tlb_instruction_invalidate(void) { -- cgit v1.2.3