From bb9a4b816b7efaab4e1e45e4c1ea1d81f6c8a21e Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 24 Jun 2021 12:20:32 +0200 Subject: arm: For AArch32 use non-shareable memory The Cortex-R52 does not support cache coherency and the shareable memory attribute. If a region is configured to be shareable, then it falls back to use non-cacheable memory. Update #4202. --- cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h') diff --git a/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h b/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h index 825a057b03..a12bf994f1 100644 --- a/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h +++ b/cpukit/score/cpu/arm/include/rtems/score/aarch32-pmsa.h @@ -141,7 +141,7 @@ extern "C" { ( AARCH32_PMSA_ATTR_EN | \ AARCH32_PMSA_ATTR_XN | \ AARCH32_PMSA_ATTR_AP( AARCH32_PMSA_ATTR_AP_EL1_RO_EL0_NO ) | \ - AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_OUTER ) | \ + AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \ AARCH32_PMSA_ATTR_IDX( 0U ) ) #define AARCH32_PMSA_DATA_READ_ONLY_UNCACHED \ @@ -155,7 +155,7 @@ extern "C" { ( AARCH32_PMSA_ATTR_EN | \ AARCH32_PMSA_ATTR_XN | \ AARCH32_PMSA_ATTR_AP_EL1_RW_EL0_NO | \ - AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_OUTER ) | \ + AARCH32_PMSA_ATTR_SH( AARCH32_PMSA_ATTR_SH_NO ) | \ AARCH32_PMSA_ATTR_IDX( 0U ) ) #define AARCH32_PMSA_DATA_READ_WRITE_UNCACHED \ -- cgit v1.2.3