From 022851aba54d32831feaff13deb3d9943e130eee Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Tue, 28 Jan 2014 12:10:08 +0100
Subject: Add thread-local storage (TLS) support

Tested and implemented on ARM, m68k, PowerPC and SPARC.  Other
architectures need more work.
---
 cpukit/score/cpu/arm/cpu_asm.S | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'cpukit/score/cpu/arm/cpu_asm.S')

diff --git a/cpukit/score/cpu/arm/cpu_asm.S b/cpukit/score/cpu/arm/cpu_asm.S
index 7fb4062d50..1771ddd661 100644
--- a/cpukit/score/cpu/arm/cpu_asm.S
+++ b/cpukit/score/cpu/arm/cpu_asm.S
@@ -62,12 +62,22 @@ DEFINE_FUNCTION_ARM(_CPU_Context_switch)
 	vstm	r3, {d8-d15}
 #endif
 
+#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+	mrc	p15, 0, r3, c13, c0, 3
+	str	r3, [r0, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
+#endif
+
 /* Start restoring context */
 _restore:
 #ifdef ARM_MULTILIB_HAS_LOAD_STORE_EXCLUSIVE
 	clrex
 #endif
 
+#ifdef ARM_MULTILIB_HAS_THREAD_ID_REGISTER
+	ldr	r3, [r1, #ARM_CONTEXT_CONTROL_THREAD_ID_OFFSET]
+	mcr	p15, 0, r3, c13, c0, 3
+#endif
+
 #ifdef ARM_MULTILIB_VFP_D32
 	add	r3, r1, #ARM_CONTEXT_CONTROL_D8_OFFSET
 	vldm	r3, {d8-d15}
-- 
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