From 8d68773761b2f4a3f2d7102a6af01d61db33efec Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 4 Jan 2013 14:09:19 +0100 Subject: arm: Change CPU_Exception_frame Provide proper CPU_Exception_frame definition for ARMv4 and use it. Remove arm_cpu_context. --- cpukit/score/cpu/arm/arm_exc_abort.S | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) (limited to 'cpukit/score/cpu/arm/arm_exc_abort.S') diff --git a/cpukit/score/cpu/arm/arm_exc_abort.S b/cpukit/score/cpu/arm/arm_exc_abort.S index 183773d64e..fb1b985319 100644 --- a/cpukit/score/cpu/arm/arm_exc_abort.S +++ b/cpukit/score/cpu/arm/arm_exc_abort.S @@ -77,8 +77,9 @@ _ARMV4_Exception_prefetch_abort_set_handler: _ARMV4_Exception_prefetch_abort: /* Save context and load handler */ - sub sp, #16 + sub sp, #20 stmdb sp!, {r0-r12} + mov r4, #3 ldr r6, =prefetch_abort_handler b save_more_context @@ -86,8 +87,9 @@ _ARMV4_Exception_prefetch_abort: _ARMV4_Exception_data_abort: /* Save context and load handler */ - sub sp, #16 + sub sp, #20 stmdb sp!, {r0-r12} + mov r4, #4 ldr r6, =data_abort_handler save_more_context: @@ -95,15 +97,15 @@ save_more_context: /* Save more context */ mov r2, lr mrs r3, spsr - mrs r4, cpsr + mrs r7, cpsr orr r5, r3, #ARM_PSR_I bic r5, #ARM_PSR_T msr cpsr, r5 mov r0, sp mov r1, lr - msr cpsr, r4 - add r5, sp, #68 - stmdb r5!, {r0-r3} + msr cpsr, r7 + add r5, sp, #72 + stmdb r5!, {r0-r4} /* Call high level handler */ ldr r2, [r6] @@ -121,11 +123,11 @@ save_more_context: #endif /* __thumb__ */ /* Restore context */ - ldmia r5!, {r0-r3} + ldmia r5!, {r0-r4} mov lr, r2 msr spsr, r3 ldmia sp!, {r0-r12} - add sp, #16 + add sp, #20 /* Return from interrupt */ subs pc, lr, #8 -- cgit v1.2.3