From 15620f5b6b4d5de29512b3467af1dcb53b7b3057 Mon Sep 17 00:00:00 2001 From: Daniel Hellstrom Date: Wed, 8 Apr 2015 10:03:45 +0200 Subject: LIBPCI: use RTEMS_INLINE_ROUTINE --- cpukit/libpci/pci/access.h | 53 +++++++++++++++++++++++----------------------- cpukit/libpci/pci/irq.h | 22 +++++++++++-------- 2 files changed, 40 insertions(+), 35 deletions(-) (limited to 'cpukit/libpci') diff --git a/cpukit/libpci/pci/access.h b/cpukit/libpci/pci/access.h index 7755b7a475..f7df9e9e64 100644 --- a/cpukit/libpci/pci/access.h +++ b/cpukit/libpci/pci/access.h @@ -14,6 +14,7 @@ #include #include +#include #include /* Let BSP configure load/store from PCI */ @@ -129,32 +130,32 @@ extern int pci_access_drv_register(struct pci_access_drv *drv); extern void pci_modify_cmdsts(pci_dev_t dev, uint32_t mask, uint32_t val); /* Enable Memory in command register */ -static inline void pci_mem_enable(pci_dev_t dev) +RTEMS_INLINE_ROUTINE void pci_mem_enable(pci_dev_t dev) { pci_modify_cmdsts(dev, PCIM_CMD_MEMEN, PCIM_CMD_MEMEN); } -static inline void pci_mem_disable(pci_dev_t dev) +RTEMS_INLINE_ROUTINE void pci_mem_disable(pci_dev_t dev) { pci_modify_cmdsts(dev, PCIM_CMD_MEMEN, 0); } -static inline void pci_io_enable(pci_dev_t dev) +RTEMS_INLINE_ROUTINE void pci_io_enable(pci_dev_t dev) { pci_modify_cmdsts(dev, PCIM_CMD_PORTEN, PCIM_CMD_PORTEN); } -static inline void pci_io_disable(pci_dev_t dev) +RTEMS_INLINE_ROUTINE void pci_io_disable(pci_dev_t dev) { pci_modify_cmdsts(dev, PCIM_CMD_PORTEN, 0); } -static inline void pci_master_enable(pci_dev_t dev) +RTEMS_INLINE_ROUTINE void pci_master_enable(pci_dev_t dev) { pci_modify_cmdsts(dev, PCIM_CMD_BUSMASTEREN, PCIM_CMD_BUSMASTEREN); } -static inline void pci_master_disable(pci_dev_t dev) +RTEMS_INLINE_ROUTINE void pci_master_disable(pci_dev_t dev) { pci_modify_cmdsts(dev, PCIM_CMD_BUSMASTEREN, 0); } @@ -180,25 +181,25 @@ extern void pci_io_w16(uint32_t adr, uint16_t data); extern void pci_io_w32(uint32_t adr, uint32_t data); /* Translate PCI address into CPU accessible address */ -static inline int pci_pci2cpu(uint32_t *address, int type) +RTEMS_INLINE_ROUTINE int pci_pci2cpu(uint32_t *address, int type) { return pci_access_ops.translate(address, type, 0); } /* Translate CPU accessible address into PCI address (for DMA) */ -static inline int pci_cpu2pci(uint32_t *address, int type) +RTEMS_INLINE_ROUTINE int pci_cpu2pci(uint32_t *address, int type) { return pci_access_ops.translate(address, type, 1); } /*** Read/Write a register over PCI Memory Space ***/ -static inline uint8_t pci_ld8(volatile uint8_t *addr) +RTEMS_INLINE_ROUTINE uint8_t pci_ld8(volatile uint8_t *addr) { return *addr; } -static inline void pci_st8(volatile uint8_t *addr, uint8_t val) +RTEMS_INLINE_ROUTINE void pci_st8(volatile uint8_t *addr, uint8_t val) { *addr = val; } @@ -207,42 +208,42 @@ static inline void pci_st8(volatile uint8_t *addr, uint8_t val) /* BSP has decided Big Endian PCI Bus (non-standard) */ -static inline uint16_t pci_ld_le16(volatile uint16_t *addr) +RTEMS_INLINE_ROUTINE uint16_t pci_ld_le16(volatile uint16_t *addr) { return ld_be16(addr); } -static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val) +RTEMS_INLINE_ROUTINE void pci_st_le16(volatile uint16_t *addr, uint16_t val) { st_be16(addr, val); } -static inline uint32_t pci_ld_le32(volatile uint32_t *addr) +RTEMS_INLINE_ROUTINE uint32_t pci_ld_le32(volatile uint32_t *addr) { return ld_be32(addr); } -static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val) +RTEMS_INLINE_ROUTINE void pci_st_le32(volatile uint32_t *addr, uint32_t val) { st_be32(addr, val); } -static inline uint16_t pci_ld_be16(volatile uint16_t *addr) +RTEMS_INLINE_ROUTINE uint16_t pci_ld_be16(volatile uint16_t *addr) { return ld_le16(addr); } -static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val) +RTEMS_INLINE_ROUTINE void pci_st_be16(volatile uint16_t *addr, uint16_t val) { st_le16(addr, val); } -static inline uint32_t pci_ld_be32(volatile uint32_t *addr) +RTEMS_INLINE_ROUTINE uint32_t pci_ld_be32(volatile uint32_t *addr) { return ld_le32(addr); } -static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val) +RTEMS_INLINE_ROUTINE void pci_st_be32(volatile uint32_t *addr, uint32_t val) { st_le32(addr, val); } @@ -251,42 +252,42 @@ static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val) /* Little Endian PCI Bus */ -static inline uint16_t pci_ld_le16(volatile uint16_t *addr) +RTEMS_INLINE_ROUTINE uint16_t pci_ld_le16(volatile uint16_t *addr) { return ld_le16(addr); } -static inline void pci_st_le16(volatile uint16_t *addr, uint16_t val) +RTEMS_INLINE_ROUTINE void pci_st_le16(volatile uint16_t *addr, uint16_t val) { st_le16(addr, val); } -static inline uint32_t pci_ld_le32(volatile uint32_t *addr) +RTEMS_INLINE_ROUTINE uint32_t pci_ld_le32(volatile uint32_t *addr) { return ld_le32(addr); } -static inline void pci_st_le32(volatile uint32_t *addr, uint32_t val) +RTEMS_INLINE_ROUTINE void pci_st_le32(volatile uint32_t *addr, uint32_t val) { st_le32(addr, val); } -static inline uint16_t pci_ld_be16(volatile uint16_t *addr) +RTEMS_INLINE_ROUTINE uint16_t pci_ld_be16(volatile uint16_t *addr) { return ld_be16(addr); } -static inline void pci_st_be16(volatile uint16_t *addr, uint16_t val) +RTEMS_INLINE_ROUTINE void pci_st_be16(volatile uint16_t *addr, uint16_t val) { st_be16(addr, val); } -static inline uint32_t pci_ld_be32(volatile uint32_t *addr) +RTEMS_INLINE_ROUTINE uint32_t pci_ld_be32(volatile uint32_t *addr) { return ld_be32(addr); } -static inline void pci_st_be32(volatile uint32_t *addr, uint32_t val) +RTEMS_INLINE_ROUTINE void pci_st_be32(volatile uint32_t *addr, uint32_t val) { st_be32(addr, val); } diff --git a/cpukit/libpci/pci/irq.h b/cpukit/libpci/pci/irq.h index 3a7dfe4318..d8cb0a219b 100644 --- a/cpukit/libpci/pci/irq.h +++ b/cpukit/libpci/pci/irq.h @@ -1,7 +1,4 @@ /* PCI IRQ Library - * - * IRQ handling does not have so much with PCI to do, this library depends - * on the BSP to implement shared interrupts. * * COPYRIGHT (c) 2010 Cobham Gaisler AB. * @@ -10,13 +7,19 @@ * http://www.rtems.com/license/LICENSE. */ +/* IRQ handling does not have so much with PCI to do, this library depends + * on the BSP to implement shared interrupts. + */ + #ifndef __PCI_IRQ_H__ #define __PCI_IRQ_H__ #include +#include +#include /* PCI Handler (ISR) called when IRQ is generated by any of the PCI devices - * connected to the same PCI IRQ Pin. This is been defined the same way as + * connected to the same PCI IRQ Pin. This has been defined the same way as * rtems_interrupt_handler in order for BSPs to "direct-map" the register * and unregister functions rtems_interrupt_handler_install/remove */ @@ -37,7 +40,7 @@ extern int pci_dev_irq(pci_dev_t dev); * isr Function pointer to the ISR * arg Second argument to function isr */ -static inline int pci_interrupt_register(int irq, const char *info, +RTEMS_INLINE_ROUTINE int pci_interrupt_register(int irq, const char *info, pci_isr isr, void *arg) { return BSP_PCI_shared_interrupt_register(irq, info, isr, arg); @@ -50,7 +53,8 @@ static inline int pci_interrupt_register(int irq, const char *info, * isr Function pointer to the ISR * arg Second argument to function isr */ -static inline int pci_interrupt_unregister(int irq, pci_isr isr, void *arg) +RTEMS_INLINE_ROUTINE int pci_interrupt_unregister(int irq, pci_isr isr, + void *arg) { return BSP_PCI_shared_interrupt_unregister(irq, isr, arg); } @@ -66,7 +70,7 @@ static inline int pci_interrupt_unregister(int irq, pci_isr isr, void *arg) * isr Function pointer to the ISR * arg Second argument to function isr */ -static inline void pci_interrupt_unmask(int irq) +RTEMS_INLINE_ROUTINE void pci_interrupt_unmask(int irq) { BSP_PCI_shared_interrupt_unmask(irq); } @@ -82,7 +86,7 @@ static inline void pci_interrupt_unmask(int irq) * isr Function pointer to the ISR * arg Second argument to function isr */ -static inline void pci_interrupt_mask(int irq) +RTEMS_INLINE_ROUTINE void pci_interrupt_mask(int irq) { BSP_PCI_shared_interrupt_mask(irq); } @@ -96,7 +100,7 @@ static inline void pci_interrupt_mask(int irq) * isr Function pointer to the ISR * arg Second argument to function isr */ -static inline void pci_interrupt_clear(int irq) +RTEMS_INLINE_ROUTINE void pci_interrupt_clear(int irq) { BSP_PCI_shared_interrupt_clear(irq); } -- cgit v1.2.3