From d9af2ed4dd235b15b953f4743d8adbf971208851 Mon Sep 17 00:00:00 2001 From: Thomas Doerfler Date: Mon, 20 Aug 2012 10:15:20 +0200 Subject: bsp/gen83xx: Add br_uid BSP variant --- c/src/lib/libbsp/powerpc/gen83xx/Makefile.am | 1 + c/src/lib/libbsp/powerpc/gen83xx/configure.ac | 5 ++ .../libbsp/powerpc/gen83xx/include/hwreg_vals.h | 89 ++++++++++++++++++++++ .../libbsp/powerpc/gen83xx/make/custom/br_uid.cfg | 10 +++ c/src/lib/libbsp/powerpc/gen83xx/preinstall.am | 4 + c/src/lib/libbsp/powerpc/gen83xx/start/start.S | 1 + .../libbsp/powerpc/gen83xx/startup/linkcmds.br_uid | 14 ++++ c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h | 15 ++++ 8 files changed, 139 insertions(+) create mode 100644 c/src/lib/libbsp/powerpc/gen83xx/make/custom/br_uid.cfg create mode 100644 c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.br_uid (limited to 'c') diff --git a/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am b/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am index 7a42ebcbd3..4ee0d2464e 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am +++ b/c/src/lib/libbsp/powerpc/gen83xx/Makefile.am @@ -42,6 +42,7 @@ dist_project_lib_DATA += startup/linkcmds \ startup/linkcmds.base \ startup/linkcmds.mpc8309som \ startup/linkcmds.mpc8313erdb \ + startup/linkcmds.br_uid \ startup/linkcmds.mpc8349eamds \ startup/linkcmds.hsc_cm01 diff --git a/c/src/lib/libbsp/powerpc/gen83xx/configure.ac b/c/src/lib/libbsp/powerpc/gen83xx/configure.ac index 403a322c31..a187637d94 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/configure.ac +++ b/c/src/lib/libbsp/powerpc/gen83xx/configure.ac @@ -35,7 +35,12 @@ RTEMS_BSPOPTS_SET([MPC83XX_BOARD_MPC8309SOM],[mpc8309som],[1]) RTEMS_BSPOPTS_HELP([MPC83XX_BOARD_MPC8309SOM], [if defined, then use settings for the MPC8309SOM board]) +RTEMS_BSPOPTS_SET([MPC83XX_BOARD_BR_UID],[br_uid],[1]) +RTEMS_BSPOPTS_HELP([MPC83XX_BOARD_BR_UID], +[if defined, then use settings for the BR UID board]) + RTEMS_BSPOPTS_SET([MPC83XX_CHIP_TYPE],[mpc8309som],[8309]) +RTEMS_BSPOPTS_SET([MPC83XX_CHIP_TYPE],[br_uid],[8309]) RTEMS_BSPOPTS_SET([MPC83XX_CHIP_TYPE],[mpc8349eamds],[8349]) RTEMS_BSPOPTS_SET([MPC83XX_CHIP_TYPE],[hsc_cm01],[8349]) RTEMS_BSPOPTS_SET([MPC83XX_CHIP_TYPE],[*],[8313]) diff --git a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h index c97059b2c4..c7c3d2ac14 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h +++ b/c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h @@ -106,6 +106,46 @@ RCWHR_LALE_EARLY | \ RCWHR_LDP_SPC) +#elif defined(MPC83XX_BOARD_BR_UID) +/* + * for BR UID + */ +/* + * one DUART channel (UART1) supported + */ +#define GEN83xx_DUART_AVAIL_MASK 0x01 + +/* we need the low level initialization in start.S*/ +#define NEED_LOW_LEVEL_INIT +/* + * clocking infos + */ +#define BSP_CLKIN_FRQ 25000000L +#define RCFG_SYSPLL_MF 5 +#define RCFG_COREPLL_MF 5 +/* + * Reset configuration words + */ +#define RESET_CONF_WRD_L \ + (RCWLR_LBIUCM_1_1 \ + | RCWLR_DDRCM_2_1 \ + | RCWLR_SPMF(RCFG_SYSPLL_MF) \ + | RCWLR_COREPLL(RCFG_COREPLL_MF) \ + | RCWLR_CEVCOD_1_2 \ + | RCWLR_CEPMF(8) \ + ) + +#define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ + RCWHR_PCI_32 | \ + RCWHR_PCI1ARB_DIS | \ + RCWHR_CORE_EN | \ + RCWHR_BMS_LOW | \ + RCWHR_BOOTSEQ_NONE | \ + RCWHR_SW_DIS | \ + RCWHR_ROMLOC_LB16 | \ + RCWHR_RLEXT_LGCY | \ + RCWHR_ENDIAN_BIG) + #elif defined( HAS_UBOOT) /* TODO */ @@ -258,6 +298,55 @@ #define DDR_SDRAM_INIT_ADDR_VAL 0 #define DDR_SDRAM_INTERVAL_VAL 0x05080000 +#elif defined(MPC83XX_BOARD_BR_UID) +/************************** + * for BR UID + */ + +/* + * working values for various registers, used in start/start.S + */ + +/* + * Local Access Windows + * FIXME: decode bit settings + */ + +#define LBLAWBAR0_VAL bsp_rom_start +#define LBLAWAR0_VAL 0x80000018 +#define DDRLAWBAR0_VAL bsp_ram_start +#define DDRLAWAR0_VAL 0x8000001B + + +/* + * clocking for local bus: + * ALE active for 1 clock + * local bus clock = 1/2 csb clock + */ +#define LCRR_VAL 0x80010002 + +/* + * DDR-SDRAM registers + * FIXME: decode bit settings + */ +#define DDRCDR_VAL 0x00000001 +#define CS0_BNDS_VAL 0x0000000F +#define CS0_CONFIG_VAL 0x80014202 +#define TIMING_CFG_0_VAL 0x00220802 +#define TIMING_CFG_1_VAL 0x26259222 +#define TIMING_CFG_2_VAL 0x111048C7 +#define DDR_SDRAM_CFG_2_VAL 0x00401000 +#define DDR_SDRAM_MODE_VAL 0x200F1632 +#define DDR_SDRAM_MODE_2_VAL 0x40006000 +#define DDR_SDRAM_CLK_CNTL_VAL 0x01800000 +#define DDR_SDRAM_CFG_VAL 0x43100008 + +#define DDR_ERR_DISABLE_VAL 0x0000008D +#define DDR_ERR_DISABLE_VAL2 0x00000089 +#define DDR_SDRAM_DATA_INIT_VAL 0xC01DCAFE +#define DDR_SDRAM_INIT_ADDR_VAL 0 +#define DDR_SDRAM_INTERVAL_VAL 0x01E8222E + #elif defined( HAS_UBOOT) /* TODO */ diff --git a/c/src/lib/libbsp/powerpc/gen83xx/make/custom/br_uid.cfg b/c/src/lib/libbsp/powerpc/gen83xx/make/custom/br_uid.cfg new file mode 100644 index 0000000000..0db23d54dd --- /dev/null +++ b/c/src/lib/libbsp/powerpc/gen83xx/make/custom/br_uid.cfg @@ -0,0 +1,10 @@ +## +# +# @file +# +# @ingroup mpc83xx_config +# +# @brief Configuration file for the BR UID base board +# + +include $(RTEMS_ROOT)/make/custom/gen83xx.inc diff --git a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am index 51a3b1b9f1..13bed48cc6 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am +++ b/c/src/lib/libbsp/powerpc/gen83xx/preinstall.am @@ -125,6 +125,10 @@ $(PROJECT_LIB)/linkcmds.mpc8313erdb: startup/linkcmds.mpc8313erdb $(PROJECT_LIB) $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc8313erdb PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc8313erdb +$(PROJECT_LIB)/linkcmds.br_uid: startup/linkcmds.br_uid $(PROJECT_LIB)/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.br_uid +PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.br_uid + $(PROJECT_LIB)/linkcmds.mpc8349eamds: startup/linkcmds.mpc8349eamds $(PROJECT_LIB)/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc8349eamds PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc8349eamds diff --git a/c/src/lib/libbsp/powerpc/gen83xx/start/start.S b/c/src/lib/libbsp/powerpc/gen83xx/start/start.S index 8d2640e6da..df06d29cb6 100644 --- a/c/src/lib/libbsp/powerpc/gen83xx/start/start.S +++ b/c/src/lib/libbsp/powerpc/gen83xx/start/start.S @@ -368,6 +368,7 @@ start_rom_skip1: mtlr r29 blr /* now further execution RAM */ copy_rest_of_text: + LWI r31,IMMRBAR #ifdef LCRR_VAL SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL #endif diff --git a/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.br_uid b/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.br_uid new file mode 100644 index 0000000000..2764431fac --- /dev/null +++ b/c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.br_uid @@ -0,0 +1,14 @@ +/** + * @file + * + * MPC8309 System on Module. + */ + +MEMORY { + RAM : ORIGIN = 0x0, LENGTH = 256M + ROM : ORIGIN = 0xfe000000, LENGTH = 2M + MPC83XX_REGS : ORIGIN = 0xe0000000, LENGTH = 256k + NIRVANA : ORIGIN = 0x0, LENGTH = 0 +} + +INCLUDE linkcmds.base diff --git a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h index 591b362197..59214254e8 100644 --- a/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h +++ b/c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h @@ -920,6 +920,14 @@ extern m83xxRegisters_t mpc83xx; /* Core PLL mult. factor */ #define RCWLR_COREPLL(n) (((n)&0xff)<<(31-15)) +/* for MPC8309: */ +#define RCWLR_CEVCOD_1_4 (0<<(31-25)) /* QUICC internal PLL divider 1:4 */ +#define RCWLR_CEVCOD_1_2 (2<<(31-25)) /* QUICC internal PLL divider 1:2 */ + /* QUICC Engine PLL mult. factor */ +#define RCWLR_CEPDF_2 (1<<(31-26)) /* QUICC Engine divide PLL out by 2*/ + /* QUICC Engine PLL mult. factor */ +#define RCWLR_CEPMF(n) (((n)&0x1f)<<(31-31)) + /* PCI host mode */ #define RCWHR_PCI_AGENT (0 << (31- 0)) /* agent mode */ #define RCWHR_PCI_HOST (1 << (31- 0)) /* host mode */ @@ -974,4 +982,11 @@ extern m83xxRegisters_t mpc83xx; #define RCWHR_LDP_PAR (0 << (31-30)) /* LDP0-3 are parity pins */ #define RCWHR_LDP_SPC (1 << (31-30)) /* LDP0-3 are special pins */ +/* + * For MPC8309: + */ +#define RCWHR_RLEXT_LGCY (0 << (31-13)) /* Boot ROM loc. extension: Legacy */ +#define RCWHR_RLEXT_NAND (1 << (31-13)) /* Boot ROM loc. extension: NAND Fl.*/ +#define RCWHR_RLEXT_RSV2 (2 << (31-13)) /* Boot ROM loc. extension: resrvd */ +#define RCWHR_RLEXT_RSV3 (3 << (31-13)) /* Boot ROM loc. extension: resrvd */ #endif /* _MPC83XX_MPC83XX_H */ -- cgit v1.2.3