From c186f2ed9e1fb05e65f27523159a105212e031a9 Mon Sep 17 00:00:00 2001
From: Joel Sherrill <joel.sherrill@oarcorp.com>
Date: Wed, 15 Oct 2014 17:17:08 -0500
Subject: m68k/mvme162: Fix warnings

---
 c/src/lib/libbsp/m68k/gen68360/console/console.c   |  395 +++---
 c/src/lib/libbsp/m68k/gen68360/startup/init68360.c | 1315 ++++++++++----------
 c/src/lib/libbsp/m68k/mrm332/console/sci.c         |    4 -
 c/src/lib/libbsp/m68k/mvme162/console/console.c    |   98 +-
 c/src/lib/libbsp/m68k/mvme162/include/bsp.h        |   16 +-
 c/src/lib/libbsp/m68k/mvme162/startup/bspclean.c   |   26 +-
 c/src/lib/libbsp/m68k/mvme162/timer/timer.c        |    2 +-
 c/src/lib/libbsp/m68k/mvme167/console/console.c    |    3 +-
 c/src/lib/libbsp/m68k/shared/m68000spurious.c      |    6 +-
 9 files changed, 918 insertions(+), 947 deletions(-)

(limited to 'c')

diff --git a/c/src/lib/libbsp/m68k/gen68360/console/console.c b/c/src/lib/libbsp/m68k/gen68360/console/console.c
index e57853d66d..2d238102ac 100644
--- a/c/src/lib/libbsp/m68k/gen68360/console/console.c
+++ b/c/src/lib/libbsp/m68k/gen68360/console/console.c
@@ -5,7 +5,9 @@
  *
  *  To run with interrupt-driven I/O, ensure m360_smc1_interrupt
  *  is set before calling the initialization routine.
- *
+ */
+
+/*
  *  Author:
  *    W. Eric Norum
  *    Saskatchewan Accelerator Laboratory
@@ -30,7 +32,7 @@
 /*
  * Declare clock speed -- may be overwritten by downloader or debugger
  */
-int m360_clock_rate	= 25000000;
+int m360_clock_rate  = 25000000;
 
 /*
  * Interrupt-driven input buffer
@@ -40,7 +42,7 @@ int console_baud_rate = 9600;
 
 /*
  */
-#define RXBUFSIZE	16
+#define RXBUFSIZE  16
 
 /*
  * Interrupt-driven callback
@@ -64,15 +66,15 @@ static volatile m360BufferDescriptor_t *smcRxBd, *smcTxBd;
 static int
 smc1BRGC (int baud)
 {
-	int divisor;
-	int div16 = 0;
-
-	divisor = ((m360_clock_rate / 16) + (baud / 2)) / baud;
-	if (divisor > 4096) {
-		div16 = 1;
-		divisor = (divisor + 8) / 16;
-	}
-	return M360_BRG_EN | M360_BRG_EXTC_BRGCLK | ((divisor - 1) << 1) | div16;
+  int divisor;
+  int div16 = 0;
+
+  divisor = ((m360_clock_rate / 16) + (baud / 2)) / baud;
+  if (divisor > 4096) {
+    div16 = 1;
+    divisor = (divisor + 8) / 16;
+  }
+  return M360_BRG_EN | M360_BRG_EXTC_BRGCLK | ((divisor - 1) << 1) | div16;
 }
 
 /*
@@ -95,165 +97,164 @@ smc1SetAttributes (int minor, const struct termios *t)
 static rtems_isr
 smc1InterruptHandler (rtems_vector_number v)
 {
-	/*
-	 * Buffer received?
-	 */
-	if (m360.smc1.smce & 0x1) {
-		m360.smc1.smce = 0x1;
-		while ((smcRxBd->status & M360_BD_EMPTY) == 0) {
-			rtems_termios_enqueue_raw_characters (smc1ttyp,
-							(char *)smcRxBd->buffer,
-							smcRxBd->length);
-			smcRxBd->status = M360_BD_EMPTY | M360_BD_WRAP | M360_BD_INTERRUPT;
-		}
-	}
-
-	/*
-	 * Buffer transmitted?
-	 */
-	if (m360.smc1.smce & 0x2) {
-		m360.smc1.smce = 0x2;
-		if ((smcTxBd->status & M360_BD_READY) == 0)
-			rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length);
-	}
-	m360.cisr = 1UL << 4;	/* Clear SMC1 interrupt-in-service bit */
+  /*
+   * Buffer received?
+   */
+  if (m360.smc1.smce & 0x1) {
+    m360.smc1.smce = 0x1;
+    while ((smcRxBd->status & M360_BD_EMPTY) == 0) {
+      rtems_termios_enqueue_raw_characters (smc1ttyp,
+              (char *)smcRxBd->buffer,
+              smcRxBd->length);
+      smcRxBd->status = M360_BD_EMPTY | M360_BD_WRAP | M360_BD_INTERRUPT;
+    }
+  }
+
+  /*
+   * Buffer transmitted?
+   */
+  if (m360.smc1.smce & 0x2) {
+    m360.smc1.smce = 0x2;
+    if ((smcTxBd->status & M360_BD_READY) == 0)
+      rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length);
+  }
+  m360.cisr = 1UL << 4;  /* Clear SMC1 interrupt-in-service bit */
 }
 
 static int
 smc1Initialize (int major, int minor, void *arg)
 {
-	/*
-	 * Allocate buffer descriptors
-	 */
-	smcRxBd = M360AllocateBufferDescriptors (1);
-	smcTxBd = M360AllocateBufferDescriptors (1);
-
-	/*
-	 * Configure port B pins to enable SMTXD1 and SMRXD1 pins
-	 */
-	m360.pbpar |=  0xC0;
-	m360.pbdir &= ~0xC0;
-	m360.pbodr &= ~0xC0;
-
-	/*
-	 * Set up BRG1 (9,600 baud)
-	 */
-	m360.brgc1 = M360_BRG_RST;
-	m360.brgc1 = smc1BRGC (console_baud_rate);
-
-	/*
-	 * Put SMC1 in NMSI mode, connect SMC1 to BRG1
-	 */
-	m360.simode |= M360_SI_SMC1_BRG1;
-
-	/*
-	 * Set up SMC1 parameter RAM common to all protocols
-	 */
-	m360.smc1p.rbase = (char *)smcRxBd - (char *)&m360;
-	m360.smc1p.tbase = (char *)smcTxBd - (char *)&m360;
-	m360.smc1p.rfcr = M360_RFCR_MOT | M360_RFCR_DMA_SPACE;
-	m360.smc1p.tfcr = M360_TFCR_MOT | M360_TFCR_DMA_SPACE;
-	if (m360_smc1_interrupt)
-		m360.smc1p.mrblr = RXBUFSIZE;
-	else
-		m360.smc1p.mrblr = 1;
-
-	/*
-	 * Set up SMC1 parameter RAM UART-specific parameters
-	 */
-	m360.smc1p.un.uart.max_idl = 10;
-	m360.smc1p.un.uart.brklen = 0;
-	m360.smc1p.un.uart.brkec = 0;
-	m360.smc1p.un.uart.brkcr = 0;
-
-	/*
-	 * Set up the Receive Buffer Descriptor
-	 */
-	smcRxBd->status = M360_BD_EMPTY | M360_BD_WRAP | M360_BD_INTERRUPT;
-	smcRxBd->length = 0;
-	smcRxBd->buffer = rxBuf;
-
-	/*
-	 * Setup the Transmit Buffer Descriptor
-	 */
-	smcTxBd->status = M360_BD_WRAP;
-
-	/*
-	 * Set up SMC1 general and protocol-specific mode registers
-	 */
-	m360.smc1.smce = ~0;	/* Clear any pending events */
-	m360.smc1.smcm = 0;	/* Mask all interrupt/event sources */
-	m360.smc1.smcmr = M360_SMCMR_CLEN(9) | M360_SMCMR_SM_UART;
-
-	/*
-	 * Send "Init parameters" command
-	 */
-	M360ExecuteRISC (M360_CR_OP_INIT_RX_TX | M360_CR_CHAN_SMC1);
-
-	/*
-	 * Enable receiver and transmitter
-	 */
-	m360.smc1.smcmr |= M360_SMCMR_TEN | M360_SMCMR_REN;
-
-	if (m360_smc1_interrupt) {
-	rtems_isr_entry old_handler;
-	rtems_status_code sc;
-
-	sc = rtems_interrupt_catch (smc1InterruptHandler,
-						(m360.cicr & 0xE0) | 0x04,
-						&old_handler);
-	m360.smc1.smcm = 3;	/* Enable SMC1 TX and RX interrupts */
-	m360.cimr |= 1UL << 4;	/* Enable SMC1 interrupts */
-	}
-
-	return 0;
+  /*
+   * Allocate buffer descriptors
+   */
+  smcRxBd = M360AllocateBufferDescriptors (1);
+  smcTxBd = M360AllocateBufferDescriptors (1);
+
+  /*
+   * Configure port B pins to enable SMTXD1 and SMRXD1 pins
+   */
+  m360.pbpar |=  0xC0;
+  m360.pbdir &= ~0xC0;
+  m360.pbodr &= ~0xC0;
+
+  /*
+   * Set up BRG1 (9,600 baud)
+   */
+  m360.brgc1 = M360_BRG_RST;
+  m360.brgc1 = smc1BRGC (console_baud_rate);
+
+  /*
+   * Put SMC1 in NMSI mode, connect SMC1 to BRG1
+   */
+  m360.simode |= M360_SI_SMC1_BRG1;
+
+  /*
+   * Set up SMC1 parameter RAM common to all protocols
+   */
+  m360.smc1p.rbase = (char *)smcRxBd - (char *)&m360;
+  m360.smc1p.tbase = (char *)smcTxBd - (char *)&m360;
+  m360.smc1p.rfcr = M360_RFCR_MOT | M360_RFCR_DMA_SPACE;
+  m360.smc1p.tfcr = M360_TFCR_MOT | M360_TFCR_DMA_SPACE;
+  if (m360_smc1_interrupt)
+    m360.smc1p.mrblr = RXBUFSIZE;
+  else
+    m360.smc1p.mrblr = 1;
+
+  /*
+   * Set up SMC1 parameter RAM UART-specific parameters
+   */
+  m360.smc1p.un.uart.max_idl = 10;
+  m360.smc1p.un.uart.brklen = 0;
+  m360.smc1p.un.uart.brkec = 0;
+  m360.smc1p.un.uart.brkcr = 0;
+
+  /*
+   * Set up the Receive Buffer Descriptor
+   */
+  smcRxBd->status = M360_BD_EMPTY | M360_BD_WRAP | M360_BD_INTERRUPT;
+  smcRxBd->length = 0;
+  smcRxBd->buffer = rxBuf;
+
+  /*
+   * Setup the Transmit Buffer Descriptor
+   */
+  smcTxBd->status = M360_BD_WRAP;
+
+  /*
+   * Set up SMC1 general and protocol-specific mode registers
+   */
+  m360.smc1.smce = ~0;  /* Clear any pending events */
+  m360.smc1.smcm = 0;  /* Mask all interrupt/event sources */
+  m360.smc1.smcmr = M360_SMCMR_CLEN(9) | M360_SMCMR_SM_UART;
+
+  /*
+   * Send "Init parameters" command
+   */
+  M360ExecuteRISC (M360_CR_OP_INIT_RX_TX | M360_CR_CHAN_SMC1);
+
+  /*
+   * Enable receiver and transmitter
+   */
+  m360.smc1.smcmr |= M360_SMCMR_TEN | M360_SMCMR_REN;
+
+  if (m360_smc1_interrupt) {
+  rtems_isr_entry old_handler;
+
+  (void) rtems_interrupt_catch (smc1InterruptHandler,
+            (m360.cicr & 0xE0) | 0x04,
+            &old_handler);
+  m360.smc1.smcm = 3;  /* Enable SMC1 TX and RX interrupts */
+  m360.cimr |= 1UL << 4;  /* Enable SMC1 interrupts */
+  }
+
+  return 0;
 }
 
 static int
 smc1PollRead (int minor)
 {
-	unsigned char c;
+  unsigned char c;
 
-	if (smcRxBd->status & M360_BD_EMPTY)
-		return -1;
-	c = rxBuf[0];
-	smcRxBd->status = M360_BD_EMPTY | M360_BD_WRAP;
-	return c;
+  if (smcRxBd->status & M360_BD_EMPTY)
+    return -1;
+  c = rxBuf[0];
+  smcRxBd->status = M360_BD_EMPTY | M360_BD_WRAP;
+  return c;
 }
 
 /*
  * Device-dependent write routine
  * Interrupt-driven devices:
- *	Begin transmission of as many characters as possible (minimum is 1).
+ *  Begin transmission of as many characters as possible (minimum is 1).
  * Polling devices:
- *	Transmit all characters.
+ *  Transmit all characters.
  */
 static ssize_t
 smc1InterruptWrite (int minor, const char *buf, size_t len)
 {
-	if (len > 0) {
-		smcTxBd->buffer = (char *)buf;
-		smcTxBd->length = len;
-		smcTxBd->status = M360_BD_READY | M360_BD_WRAP | M360_BD_INTERRUPT;
-	}
+  if (len > 0) {
+    smcTxBd->buffer = (char *)buf;
+    smcTxBd->length = len;
+    smcTxBd->status = M360_BD_READY | M360_BD_WRAP | M360_BD_INTERRUPT;
+  }
 
-	return 0;
+  return 0;
 }
 
 static ssize_t
 smc1PollWrite (int minor, const char *buf, size_t len)
 {
-	size_t retval = len;
-	while (len--) {
-		static char txBuf;
-		while (smcTxBd->status & M360_BD_READY)
-			continue;
-		txBuf = *buf++;
-		smcTxBd->buffer = &txBuf;
-		smcTxBd->length = 1;
-		smcTxBd->status = M360_BD_READY | M360_BD_WRAP;
-	}
-	return retval;
+  size_t retval = len;
+  while (len--) {
+    static char txBuf;
+    while (smcTxBd->status & M360_BD_READY)
+      continue;
+    txBuf = *buf++;
+    smcTxBd->buffer = &txBuf;
+    smcTxBd->length = 1;
+    smcTxBd->status = M360_BD_READY | M360_BD_WRAP;
+  }
+  return retval;
 }
 
 /*
@@ -277,20 +278,20 @@ rtems_device_driver console_initialize(
   void                      *arg
 )
 {
-	rtems_status_code status;
-
-	/*
-	 * Set up TERMIOS
-	 */
-	rtems_termios_initialize ();
-
-	/*
-	 * Register the device
-	 */
-	status = rtems_io_register_name ("/dev/console", major, 0);
-	if (status != RTEMS_SUCCESSFUL)
-		rtems_fatal_error_occurred (status);
-	return RTEMS_SUCCESSFUL;
+  rtems_status_code status;
+
+  /*
+   * Set up TERMIOS
+   */
+  rtems_termios_initialize ();
+
+  /*
+   * Register the device
+   */
+  status = rtems_io_register_name ("/dev/console", major, 0);
+  if (status != RTEMS_SUCCESSFUL)
+    rtems_fatal_error_occurred (status);
+  return RTEMS_SUCCESSFUL;
 }
 
 /*
@@ -302,41 +303,41 @@ rtems_device_driver console_open(
   void                    * arg
 )
 {
-	rtems_status_code sc;
-	static const rtems_termios_callbacks intrCallbacks = {
-		smc1Initialize,		/* firstOpen */
-		NULL,			/* lastClose */
-		NULL,			/* pollRead */
-		smc1InterruptWrite,	/* write */
-		smc1SetAttributes,	/* setAttributes */
-		NULL,			/* stopRemoteTx */
-		NULL,			/* startRemoteTx */
-		1			/* outputUsesInterrupts */
-	};
-	static const rtems_termios_callbacks pollCallbacks = {
-		smc1Initialize,		/* firstOpen */
-		NULL,			/* lastClose */
-		smc1PollRead,		/* pollRead */
-		smc1PollWrite,		/* write */
-		smc1SetAttributes,	/* setAttributes */
-		NULL,			/* stopRemoteTx */
-		NULL,			/* startRemoteTx */
-		0			/* outputUsesInterrupts */
-	};
-
-	/*
-	 * Do generic termios initialization
-	 */
-	if (m360_smc1_interrupt) {
-		rtems_libio_open_close_args_t *args = arg;
-
-		sc = rtems_termios_open (major, minor, arg, &intrCallbacks);
-		smc1ttyp = args->iop->data1;
-	}
-	else {
-		sc = rtems_termios_open (major, minor, arg, &pollCallbacks);
-	}
-	return sc;
+  rtems_status_code sc;
+  static const rtems_termios_callbacks intrCallbacks = {
+    smc1Initialize,    /* firstOpen */
+    NULL,      /* lastClose */
+    NULL,      /* pollRead */
+    smc1InterruptWrite,  /* write */
+    smc1SetAttributes,  /* setAttributes */
+    NULL,      /* stopRemoteTx */
+    NULL,      /* startRemoteTx */
+    1      /* outputUsesInterrupts */
+  };
+  static const rtems_termios_callbacks pollCallbacks = {
+    smc1Initialize,    /* firstOpen */
+    NULL,      /* lastClose */
+    smc1PollRead,    /* pollRead */
+    smc1PollWrite,    /* write */
+    smc1SetAttributes,  /* setAttributes */
+    NULL,      /* stopRemoteTx */
+    NULL,      /* startRemoteTx */
+    0      /* outputUsesInterrupts */
+  };
+
+  /*
+   * Do generic termios initialization
+   */
+  if (m360_smc1_interrupt) {
+    rtems_libio_open_close_args_t *args = arg;
+
+    sc = rtems_termios_open (major, minor, arg, &intrCallbacks);
+    smc1ttyp = args->iop->data1;
+  }
+  else {
+    sc = rtems_termios_open (major, minor, arg, &pollCallbacks);
+  }
+  return sc;
 }
 
 /*
@@ -348,7 +349,7 @@ rtems_device_driver console_close(
   void                    * arg
 )
 {
-	return rtems_termios_close (arg);
+  return rtems_termios_close (arg);
 }
 
 /*
@@ -360,7 +361,7 @@ rtems_device_driver console_read(
   void                    * arg
 )
 {
-	return rtems_termios_read (arg);
+  return rtems_termios_read (arg);
 }
 
 /*
@@ -372,7 +373,7 @@ rtems_device_driver console_write(
   void                    * arg
 )
 {
-	return rtems_termios_write (arg);
+  return rtems_termios_write (arg);
 }
 
 /*
@@ -384,5 +385,5 @@ rtems_device_driver console_control(
   void                    * arg
 )
 {
-	return rtems_termios_ioctl (arg);
+  return rtems_termios_ioctl (arg);
 }
diff --git a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
index 75a179342f..b39a9e150f 100644
--- a/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
+++ b/c/src/lib/libbsp/m68k/gen68360/startup/init68360.c
@@ -14,7 +14,7 @@
 
 extern void _CopyDataClearBSSAndStart (unsigned long ramSize);
 extern void *RamBase;
-extern void *_RomBase;	/* From linkcmds */
+extern void *_RomBase;  /* From linkcmds */
 
 /*
  * Declare the m360 structure here for the benefit of the debugger
@@ -28,13 +28,13 @@ volatile m360_t m360;
 
 void M360ExecuteRISC(uint16_t         command)
 {
-	uint16_t         sr;
+  uint16_t         sr;
 
-	m68k_disable_interrupts (sr);
-	while (m360.cr & M360_CR_FLG)
-		continue;
-	m360.cr = command | M360_CR_FLG;
-	m68k_enable_interrupts (sr);
+  m68k_disable_interrupts (sr);
+  while (m360.cr & M360_CR_FLG)
+    continue;
+  m360.cr = command | M360_CR_FLG;
+  m68k_enable_interrupts (sr);
 }
 
 /*
@@ -42,474 +42,477 @@ void M360ExecuteRISC(uint16_t         command)
  */
 void _Init68360 (void)
 {
-	int i;
-	rtems_isr_entry *vbr;
-	unsigned long ramSize;
-	volatile unsigned long *RamBase_p;
+  int i;
+  rtems_isr_entry *vbr;
+  unsigned long ramSize;
+  volatile unsigned long *RamBase_p;
 
-	RamBase_p = (volatile unsigned long *)&RamBase;
+  RamBase_p = (volatile unsigned long *)&RamBase;
 
 #if (defined (__mc68040__))
-	/*
-	 *******************************************
-	 * Motorola 68040 and companion-mode 68360 *
-	 *******************************************
-	 */
-
-	/*
-	 * Step 6: Is this a power-up reset?
-	 * For now we just ignore this and do *all* the steps
-	 * Someday we might want to:
-	 *	if (Hard, Loss of Clock, Power-up)
-	 *		Do all steps
-	 *	else if (Double bus fault, watchdog or soft reset)
-	 *		Skip to step 12
-	 *	else (must be a reset command)
-	 *		Skip to step 14
-	 */
-
-	/*
-	 * Step 7: Deal with clock synthesizer
-	 * HARDWARE:
-	 *	Change if you're not using an external 25 MHz oscillator.
-	 */
-	m360.clkocr = 0x83;	/* No more writes, full-power CLKO2 */
-	m360.pllcr = 0xD000;	/* PLL, no writes, no prescale,
-				   no LPSTOP slowdown, PLL X1 */
-	m360.cdvcr = 0x8000;	/* No more writes, no clock division */
-
-	/*
-	 * Step 8: Initialize system protection
-	 *	Enable watchdog
-	 *	Watchdog causes system reset
-	 *	Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
-	 *	Enable double bus fault monitor
-	 *	Enable bus monitor for external cycles
-	 *	1024 clocks for external timeout
-	 */
-	m360.sypcr = 0xEC;
-
-	/*
-	 * Step 9: Clear parameter RAM and reset communication processor module
-	 */
-	for (i = 0 ; i < 192  ; i += sizeof (long)) {
-		*((long *)((char *)&m360 + 0xC00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xD00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xE00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xF00 + i)) = 0;
-	}
-	M360ExecuteRISC (M360_CR_RST);
-
-	/*
-	 * Step 10: Write PEPAR
-	 *	SINTOUT standard M68000 family interrupt level encoding
-	 *	CF1MODE=10 (BCLRO* output)
-	 *	No RAS1* double drive
-	 *	A31 - A28
-	 *	AMUX output
-	 *	CAS2* - CAS3*
-	 *	CAS0* - CAS1*
-	 *	CS7*
-	 *	AVEC*
-	 */
-	m360.pepar = 0x3440;
-
-	/*
-	 * Step 11: Remap Chip Select 0 (CS0*), set up GMR
-	 */
-	/*
-	 * 512 addresses per DRAM page (256K DRAM chips)
-	 * 70 nsec DRAM
-	 * 180 nsec ROM (3 wait states)
-	 */
-	m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
-				M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
-				M360_GMR_DPS_32BIT | M360_GMR_NCS |
-				M360_GMR_TSS40;
-	m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
-							M360_MEMC_BR_V;
-	m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
-						M360_MEMC_OR_32BIT;
-
-	/*
-	 * Step 12: Initialize the system RAM
-	 */
-	/*
-	 *	Set up option/base registers
-	 *		1M DRAM
-	 *		70 nsec DRAM
-	 *	Enable burst mode
-	 *	No parity checking
-	 *	Wait for chips to power up
-	 *	Perform 8 read cycles
-	 */
-	ramSize = 1 * 1024 * 1024;
-	m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
-					M360_MEMC_OR_1MB |
-					M360_MEMC_OR_DRAM;
-	m360.memc[1].br = (unsigned long)&RamBase |
-					M360_MEMC_BR_BACK40 |
-					M360_MEMC_BR_V;
-	for (i = 0; i < 50000; i++)
-		continue;
-	for (i = 0; i < 8; ++i)
-		*RamBase_p;
-
-	/*
-	 * Step 13: Copy  the exception vector table to system RAM
-	 */
-	m68k_get_vbr (vbr);
-	for (i = 0; i < 256; ++i)
-		M68Kvec[i] = vbr[i];
-	m68k_set_vbr (M68Kvec);
-
-	/*
-	 * Step 14: More system initialization
-	 * SDCR (Serial DMA configuration register)
-	 *	Enable SDMA during FREEZE
-	 *	Give SDMA priority over all interrupt handlers
-	 *	Set DMA arbiration level to 4
-	 * CICR (CPM interrupt configuration register):
-	 *	SCC1 requests at SCCa position
-	 *	SCC2 requests at SCCb position
-	 *	SCC3 requests at SCCc position
-	 *	SCC4 requests at SCCd position
-	 *	Interrupt request level 4
-	 *	Maintain original priority order
-	 *	Vector base 128
-	 *	SCCs priority grouped at top of table
-	 */
-	m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
-	m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
-						(4 << 13) | (0x1F << 8) | (128);
-
-	/*
-	 * Step 15: Set module configuration register
-	 *	Bus request MC68040 Arbitration ID 3
-	 *	Bus asynchronous timing mode (work around bug in Rev. B)
-	 *	Arbitration asynchronous timing mode
-	 *	Disable timers during FREEZE
-	 *	Disable bus monitor during FREEZE
-	 *	BCLRO* arbitration level 3
-	 *	No show cycles
-	 *	User/supervisor access
-	 *	Bus clear in arbitration ID level  3
-	 *	SIM60 interrupt sources higher priority than CPM
-	 */
-	m360.mcr = 0x6000EC3F;
+  /*
+   *******************************************
+   * Motorola 68040 and companion-mode 68360 *
+   *******************************************
+   */
+
+  /*
+   * Step 6: Is this a power-up reset?
+   * For now we just ignore this and do *all* the steps
+   * Someday we might want to:
+   *  if (Hard, Loss of Clock, Power-up)
+   *    Do all steps
+   *  else if (Double bus fault, watchdog or soft reset)
+   *    Skip to step 12
+   *  else (must be a reset command)
+   *    Skip to step 14
+   */
+
+  /*
+   * Step 7: Deal with clock synthesizer
+   * HARDWARE:
+   *  Change if you're not using an external 25 MHz oscillator.
+   */
+  m360.clkocr = 0x83;  /* No more writes, full-power CLKO2 */
+  m360.pllcr = 0xD000;  /* PLL, no writes, no prescale,
+           no LPSTOP slowdown, PLL X1 */
+  m360.cdvcr = 0x8000;  /* No more writes, no clock division */
+
+  /*
+   * Step 8: Initialize system protection
+   *  Enable watchdog
+   *  Watchdog causes system reset
+   *  Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
+   *  Enable double bus fault monitor
+   *  Enable bus monitor for external cycles
+   *  1024 clocks for external timeout
+   */
+  m360.sypcr = 0xEC;
+
+  /*
+   * Step 9: Clear parameter RAM and reset communication processor module
+   */
+  for (i = 0 ; i < 192  ; i += sizeof (long)) {
+    *((long *)((char *)&m360 + 0xC00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xD00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xE00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xF00 + i)) = 0;
+  }
+  M360ExecuteRISC (M360_CR_RST);
+
+  /*
+   * Step 10: Write PEPAR
+   *  SINTOUT standard M68000 family interrupt level encoding
+   *  CF1MODE=10 (BCLRO* output)
+   *  No RAS1* double drive
+   *  A31 - A28
+   *  AMUX output
+   *  CAS2* - CAS3*
+   *  CAS0* - CAS1*
+   *  CS7*
+   *  AVEC*
+   */
+  m360.pepar = 0x3440;
+
+  /*
+   * Step 11: Remap Chip Select 0 (CS0*), set up GMR
+   */
+  /*
+   * 512 addresses per DRAM page (256K DRAM chips)
+   * 70 nsec DRAM
+   * 180 nsec ROM (3 wait states)
+   */
+  m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN |
+        M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
+        M360_GMR_DPS_32BIT | M360_GMR_NCS |
+        M360_GMR_TSS40;
+  m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
+              M360_MEMC_BR_V;
+  m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
+            M360_MEMC_OR_32BIT;
+
+  /*
+   * Step 12: Initialize the system RAM
+   */
+  /*
+   *  Set up option/base registers
+   *    1M DRAM
+   *    70 nsec DRAM
+   *  Enable burst mode
+   *  No parity checking
+   *  Wait for chips to power up
+   *  Perform 8 read cycles
+   */
+  ramSize = 1 * 1024 * 1024;
+  m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
+          M360_MEMC_OR_1MB |
+          M360_MEMC_OR_DRAM;
+  m360.memc[1].br = (unsigned long)&RamBase |
+          M360_MEMC_BR_BACK40 |
+          M360_MEMC_BR_V;
+  for (i = 0; i < 50000; i++)
+    continue;
+  for (i = 0; i < 8; ++i) {
+    unsigned long rambase_value;
+    rambase_value = *RamBase_p;
+    (void) rambase_value; /* avoid set but not used warning */
+  }
+
+  /*
+   * Step 13: Copy  the exception vector table to system RAM
+   */
+  m68k_get_vbr (vbr);
+  for (i = 0; i < 256; ++i)
+    M68Kvec[i] = vbr[i];
+  m68k_set_vbr (M68Kvec);
+
+  /*
+   * Step 14: More system initialization
+   * SDCR (Serial DMA configuration register)
+   *  Enable SDMA during FREEZE
+   *  Give SDMA priority over all interrupt handlers
+   *  Set DMA arbiration level to 4
+   * CICR (CPM interrupt configuration register):
+   *  SCC1 requests at SCCa position
+   *  SCC2 requests at SCCb position
+   *  SCC3 requests at SCCc position
+   *  SCC4 requests at SCCd position
+   *  Interrupt request level 4
+   *  Maintain original priority order
+   *  Vector base 128
+   *  SCCs priority grouped at top of table
+   */
+  m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
+  m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
+            (4 << 13) | (0x1F << 8) | (128);
+
+  /*
+   * Step 15: Set module configuration register
+   *  Bus request MC68040 Arbitration ID 3
+   *  Bus asynchronous timing mode (work around bug in Rev. B)
+   *  Arbitration asynchronous timing mode
+   *  Disable timers during FREEZE
+   *  Disable bus monitor during FREEZE
+   *  BCLRO* arbitration level 3
+   *  No show cycles
+   *  User/supervisor access
+   *  Bus clear in arbitration ID level  3
+   *  SIM60 interrupt sources higher priority than CPM
+   */
+  m360.mcr = 0x6000EC3F;
 
 #elif (defined (M68360_ATLAS_HSB))
-	/*
-	 ******************************************
-	 * Standalone Motorola 68360 -- ATLAS HSB *
-	 ******************************************
-	 */
-
-	/*
-	 * Step 6: Is this a power-up reset?
-	 * For now we just ignore this and do *all* the steps
-	 * Someday we might want to:
-	 *	if (Hard, Loss of Clock, Power-up)
-	 *		Do all steps
-	 *	else if (Double bus fault, watchdog or soft reset)
-	 *		Skip to step 12
-	 *	else (must be a CPU32+ reset command)
-	 *		Skip to step 14
-	 */
-
-	/*
-	 * Step 7: Deal with clock synthesizer
-	 * HARDWARE:
-	 *	Change if you're not using an external 25 MHz oscillator.
-	 */
-	m360.clkocr = 0x8F;	/* No more writes, no clock outputs */
-	m360.pllcr = 0xD000;	/* PLL, no writes, no prescale,
-				   no LPSTOP slowdown, PLL X1 */
-	m360.cdvcr = 0x8000;	/* No more writes, no clock division */
-
-	/*
-	 * Step 8: Initialize system protection
-	 *	Enable watchdog
-	 *	Watchdog causes system reset
-	 *	Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
-	 *	Enable double bus fault monitor
-	 *	Enable bus monitor for external cycles
-	 *	1024 clocks for external timeout
-	 */
-	m360.sypcr = 0xEC;
-
-	/*
-	 * Step 9: Clear parameter RAM and reset communication processor module
-	 */
-	for (i = 0 ; i < 192  ; i += sizeof (long)) {
-		*((long *)((char *)&m360 + 0xC00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xD00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xE00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xF00 + i)) = 0;
-	}
-	M360ExecuteRISC (M360_CR_RST);
-
-	/*
-	 * Step 10: Write PEPAR
-	 *	SINTOUT not used (CPU32+ mode)
-	 *	CF1MODE=00 (CONFIG1 input)
-	 *	RAS1* double drive
-	 *	WE0* - WE3*
-	 *	OE* output
-	 *	CAS2* - CAS3*
-	 *	CAS0* - CAS1*
-	 *	CS7*
-	 *	AVEC*
-	 * HARDWARE:
-	 *	Change if you are using a different memory configuration
-	 *	(static RAM, external address multiplexing, etc).
-	 */
-	m360.pepar = 0x0180;
-
-	/*
-	 * Step 11: Remap Chip Select 0 (CS0*), set up GMR
-	 */
-	m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
-				M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
-				M360_GMR_DPS_32BIT | M360_GMR_DWQ |
-				M360_GMR_GAMX;
-	m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
-								M360_MEMC_BR_V;
-	m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
-							M360_MEMC_OR_8BIT;
-
-	/*
-	 * Step 12: Initialize the system RAM
-	 */
-	ramSize = 2 * 1024 * 1024;
-	/* first bank 1MByte DRAM */
-	m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
-					M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
-	m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
-
-	/* second bank 1MByte DRAM */
-	m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
-					M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
-	m360.memc[2].br = ((unsigned long)&RamBase + 0x100000) |
-					M360_MEMC_BR_V;
-
-	/* flash rom socket U6 on CS5 */
-	m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
-								M360_MEMC_BR_V;
-	m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
-								M360_MEMC_OR_8BIT;
-
-	/* CSRs on CS7 */
-	m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
-					M360_MEMC_OR_8BIT;
-	m360.memc[7].br = ATLASHSB_ESR | 0x01;
-	for (i = 0; i < 50000; i++)
-		continue;
-	for (i = 0; i < 8; ++i)
-		*((volatile unsigned long *)(unsigned long)&RamBase);
-
-	/*
-	 * Step 13: Copy  the exception vector table to system RAM
-	 */
-	m68k_get_vbr (vbr);
-	for (i = 0; i < 256; ++i)
-		M68Kvec[i] = vbr[i];
-	m68k_set_vbr (M68Kvec);
-
-	/*
-	 * Step 14: More system initialization
-	 * SDCR (Serial DMA configuration register)
-	 *	Enable SDMA during FREEZE
-	 *	Give SDMA priority over all interrupt handlers
-	 *	Set DMA arbiration level to 4
-	 * CICR (CPM interrupt configuration register):
-	 *	SCC1 requests at SCCa position
-	 *	SCC2 requests at SCCb position
-	 *	SCC3 requests at SCCc position
-	 *	SCC4 requests at SCCd position
-	 *	Interrupt request level 4
-	 *	Maintain original priority order
-	 *	Vector base 128
-	 *	SCCs priority grouped at top of table
-	 */
-	m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
-	m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
-						(4 << 13) | (0x1F << 8) | (128);
-
-	/*
-	 * Step 15: Set module configuration register
-	 *	Disable timers during FREEZE
-	 *	Enable bus monitor during FREEZE
-	 *	BCLRO* arbitration level 3
-	 */
+  /*
+   ******************************************
+   * Standalone Motorola 68360 -- ATLAS HSB *
+   ******************************************
+   */
+
+  /*
+   * Step 6: Is this a power-up reset?
+   * For now we just ignore this and do *all* the steps
+   * Someday we might want to:
+   *  if (Hard, Loss of Clock, Power-up)
+   *    Do all steps
+   *  else if (Double bus fault, watchdog or soft reset)
+   *    Skip to step 12
+   *  else (must be a CPU32+ reset command)
+   *    Skip to step 14
+   */
+
+  /*
+   * Step 7: Deal with clock synthesizer
+   * HARDWARE:
+   *  Change if you're not using an external 25 MHz oscillator.
+   */
+  m360.clkocr = 0x8F;  /* No more writes, no clock outputs */
+  m360.pllcr = 0xD000;  /* PLL, no writes, no prescale,
+           no LPSTOP slowdown, PLL X1 */
+  m360.cdvcr = 0x8000;  /* No more writes, no clock division */
+
+  /*
+   * Step 8: Initialize system protection
+   *  Enable watchdog
+   *  Watchdog causes system reset
+   *  Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
+   *  Enable double bus fault monitor
+   *  Enable bus monitor for external cycles
+   *  1024 clocks for external timeout
+   */
+  m360.sypcr = 0xEC;
+
+  /*
+   * Step 9: Clear parameter RAM and reset communication processor module
+   */
+  for (i = 0 ; i < 192  ; i += sizeof (long)) {
+    *((long *)((char *)&m360 + 0xC00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xD00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xE00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xF00 + i)) = 0;
+  }
+  M360ExecuteRISC (M360_CR_RST);
+
+  /*
+   * Step 10: Write PEPAR
+   *  SINTOUT not used (CPU32+ mode)
+   *  CF1MODE=00 (CONFIG1 input)
+   *  RAS1* double drive
+   *  WE0* - WE3*
+   *  OE* output
+   *  CAS2* - CAS3*
+   *  CAS0* - CAS1*
+   *  CS7*
+   *  AVEC*
+   * HARDWARE:
+   *  Change if you are using a different memory configuration
+   *  (static RAM, external address multiplexing, etc).
+   */
+  m360.pepar = 0x0180;
+
+  /*
+   * Step 11: Remap Chip Select 0 (CS0*), set up GMR
+   */
+  m360.gmr = M360_GMR_RCNT(12) | M360_GMR_RFEN |
+        M360_GMR_RCYC(0) | M360_GMR_PGS(1) |
+        M360_GMR_DPS_32BIT | M360_GMR_DWQ |
+        M360_GMR_GAMX;
+  m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
+                M360_MEMC_BR_V;
+  m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
+              M360_MEMC_OR_8BIT;
+
+  /*
+   * Step 12: Initialize the system RAM
+   */
+  ramSize = 2 * 1024 * 1024;
+  /* first bank 1MByte DRAM */
+  m360.memc[1].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
+          M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
+  m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
+
+  /* second bank 1MByte DRAM */
+  m360.memc[2].or = M360_MEMC_OR_TCYC(2) | M360_MEMC_OR_1MB |
+          M360_MEMC_OR_PGME | M360_MEMC_OR_DRAM;
+  m360.memc[2].br = ((unsigned long)&RamBase + 0x100000) |
+          M360_MEMC_BR_V;
+
+  /* flash rom socket U6 on CS5 */
+  m360.memc[5].br = (unsigned long)ATLASHSB_ROM_U6 | M360_MEMC_BR_WP |
+                M360_MEMC_BR_V;
+  m360.memc[5].or = M360_MEMC_OR_WAITS(2) | M360_MEMC_OR_512KB |
+                M360_MEMC_OR_8BIT;
+
+  /* CSRs on CS7 */
+  m360.memc[7].or = M360_MEMC_OR_TCYC(4) | M360_MEMC_OR_64KB |
+          M360_MEMC_OR_8BIT;
+  m360.memc[7].br = ATLASHSB_ESR | 0x01;
+  for (i = 0; i < 50000; i++)
+    continue;
+  for (i = 0; i < 8; ++i)
+    *((volatile unsigned long *)(unsigned long)&RamBase);
+
+  /*
+   * Step 13: Copy  the exception vector table to system RAM
+   */
+  m68k_get_vbr (vbr);
+  for (i = 0; i < 256; ++i)
+    M68Kvec[i] = vbr[i];
+  m68k_set_vbr (M68Kvec);
+
+  /*
+   * Step 14: More system initialization
+   * SDCR (Serial DMA configuration register)
+   *  Enable SDMA during FREEZE
+   *  Give SDMA priority over all interrupt handlers
+   *  Set DMA arbiration level to 4
+   * CICR (CPM interrupt configuration register):
+   *  SCC1 requests at SCCa position
+   *  SCC2 requests at SCCb position
+   *  SCC3 requests at SCCc position
+   *  SCC4 requests at SCCd position
+   *  Interrupt request level 4
+   *  Maintain original priority order
+   *  Vector base 128
+   *  SCCs priority grouped at top of table
+   */
+  m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
+  m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
+            (4 << 13) | (0x1F << 8) | (128);
+
+  /*
+   * Step 15: Set module configuration register
+   *  Disable timers during FREEZE
+   *  Enable bus monitor during FREEZE
+   *  BCLRO* arbitration level 3
+   */
 
 #elif defined(PGH360)
-	/*
-	 * Step 6: Is this a power-up reset?
-	 * For now we just ignore this and do *all* the steps
-	 * Someday we might want to:
-	 *	if (Hard, Loss of Clock, Power-up)
-	 *		Do all steps
-	 *	else if (Double bus fault, watchdog or soft reset)
-	 *		Skip to step 12
-	 *	else (must be a CPU32+ reset command)
-	 *		Skip to step 14
-	 */
-
-	/*
-	 * Step 7: Deal with clock synthesizer
-	 * HARDWARE:
-	 *	Change if you're not using an external 25 MHz oscillator.
-	 */
-	m360.clkocr = 0x8e;	/* No more writes, CLKO1=1/3, CLKO2=off */
-	/*
-	 * adjust crystal to average between 4.19 MHz and 4.00 MHz
-	 * reprogram pll
-	 */
-	m360.pllcr = 0xA000+(24576000/((4000000+4194304)/2/128))-1;
-					/* LPSTOP slowdown, PLL /128*??? */
-	m360.cdvcr = 0x8000;	/* No more writes, no clock division */
-
-	/*
-	 * Step 8: Initialize system protection
-	 *	Enable watchdog
-	 *	Watchdog causes system reset
-	 *	128 sec. watchdog timeout
-	 *	Enable double bus fault monitor
-	 *	Enable bus monitor external
-	 *	128 clocks for external timeout
-	 */
-	m360.sypcr = 0xEF;
-	/*
-	 * also initialize the SWP bit in PITR to 1
-	 */
-	m360.pitr |= 0x0200;
-	/*
-	 * and trigger SWSR twice to ensure, that interval starts right now
-	 */
-	m360.swsr = 0x55;
-	m360.swsr = 0xAA;
-	m360.swsr = 0x55;
-	m360.swsr = 0xAA;
-	/*
-	 * Step 9: Clear parameter RAM and reset communication processor module
-	 */
-	for (i = 0 ; i < 192  ; i += sizeof (long)) {
-		*((long *)((char *)&m360 + 0xC00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xD00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xE00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xF00 + i)) = 0;
-	}
-	M360ExecuteRISC (M360_CR_RST);
-
-	/*
-	 * Step 10: Write PEPAR
-	 *	SINTOUT not used (CPU32+ mode)
-	 *	CF1MODE=00 (CONFIG1 input)
-	 *	IPIPE1
-	 *	WE0-3
-	 *	OE* output
-	 *	CAS2* / CAS3*
-	 *	CAS0* / CAS1*
-	 *	CS7*
-	 *	AVEC*
-	 * HARDWARE:
-	 *	Change if you are using a different memory configuration
-	 *	(static RAM, external address multiplexing, etc).
-	 */
-	m360.pepar = 0x0080;
-	/*
-	 * Step 11: Remap Chip Select 0 (CS0*), set up GMR
-	 *	no DRAM support
-	 * HARDWARE:
-	 *	Change if you are using a different memory configuration
-	 */
-	m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN      | M360_GMR_RCYC(0) |
-		   M360_GMR_PGS(6)   | M360_GMR_DPS_32BIT | M360_GMR_DWQ     |
-	           M360_GMR_GAMX;
-
-	m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
-							M360_MEMC_BR_V;
-	m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB |
-							M360_MEMC_OR_8BIT;
-
-	/*
-	 * Step 12: Initialize the system RAM
-	 *	Set up option/base registers
-	 *		16 MB DRAM
-	 *		1 wait state
-	 * HARDWARE:
-	 *	Change if you are using a different memory configuration
-	 *      NOTE: no Page mode possible for EDO RAMs (?)
-	 */
-	ramSize = 16 * 1024 * 1024;
-	m360.memc[7].or = M360_MEMC_OR_TCYC(1)  | M360_MEMC_OR_16MB |
-			  M360_MEMC_OR_FCMC(0)  | /* M360_MEMC_OR_PGME | */
+  /*
+   * Step 6: Is this a power-up reset?
+   * For now we just ignore this and do *all* the steps
+   * Someday we might want to:
+   *  if (Hard, Loss of Clock, Power-up)
+   *    Do all steps
+   *  else if (Double bus fault, watchdog or soft reset)
+   *    Skip to step 12
+   *  else (must be a CPU32+ reset command)
+   *    Skip to step 14
+   */
+
+  /*
+   * Step 7: Deal with clock synthesizer
+   * HARDWARE:
+   *  Change if you're not using an external 25 MHz oscillator.
+   */
+  m360.clkocr = 0x8e;  /* No more writes, CLKO1=1/3, CLKO2=off */
+  /*
+   * adjust crystal to average between 4.19 MHz and 4.00 MHz
+   * reprogram pll
+   */
+  m360.pllcr = 0xA000+(24576000/((4000000+4194304)/2/128))-1;
+          /* LPSTOP slowdown, PLL /128*??? */
+  m360.cdvcr = 0x8000;  /* No more writes, no clock division */
+
+  /*
+   * Step 8: Initialize system protection
+   *  Enable watchdog
+   *  Watchdog causes system reset
+   *  128 sec. watchdog timeout
+   *  Enable double bus fault monitor
+   *  Enable bus monitor external
+   *  128 clocks for external timeout
+   */
+  m360.sypcr = 0xEF;
+  /*
+   * also initialize the SWP bit in PITR to 1
+   */
+  m360.pitr |= 0x0200;
+  /*
+   * and trigger SWSR twice to ensure, that interval starts right now
+   */
+  m360.swsr = 0x55;
+  m360.swsr = 0xAA;
+  m360.swsr = 0x55;
+  m360.swsr = 0xAA;
+  /*
+   * Step 9: Clear parameter RAM and reset communication processor module
+   */
+  for (i = 0 ; i < 192  ; i += sizeof (long)) {
+    *((long *)((char *)&m360 + 0xC00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xD00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xE00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xF00 + i)) = 0;
+  }
+  M360ExecuteRISC (M360_CR_RST);
+
+  /*
+   * Step 10: Write PEPAR
+   *  SINTOUT not used (CPU32+ mode)
+   *  CF1MODE=00 (CONFIG1 input)
+   *  IPIPE1
+   *  WE0-3
+   *  OE* output
+   *  CAS2* / CAS3*
+   *  CAS0* / CAS1*
+   *  CS7*
+   *  AVEC*
+   * HARDWARE:
+   *  Change if you are using a different memory configuration
+   *  (static RAM, external address multiplexing, etc).
+   */
+  m360.pepar = 0x0080;
+  /*
+   * Step 11: Remap Chip Select 0 (CS0*), set up GMR
+   *  no DRAM support
+   * HARDWARE:
+   *  Change if you are using a different memory configuration
+   */
+  m360.gmr = M360_GMR_RCNT(23) | M360_GMR_RFEN      | M360_GMR_RCYC(0) |
+       M360_GMR_PGS(6)   | M360_GMR_DPS_32BIT | M360_GMR_DWQ     |
+             M360_GMR_GAMX;
+
+  m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
+              M360_MEMC_BR_V;
+  m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_512KB |
+              M360_MEMC_OR_8BIT;
+
+  /*
+   * Step 12: Initialize the system RAM
+   *  Set up option/base registers
+   *    16 MB DRAM
+   *    1 wait state
+   * HARDWARE:
+   *  Change if you are using a different memory configuration
+   *      NOTE: no Page mode possible for EDO RAMs (?)
+   */
+  ramSize = 16 * 1024 * 1024;
+  m360.memc[7].or = M360_MEMC_OR_TCYC(1)  | M360_MEMC_OR_16MB |
+        M360_MEMC_OR_FCMC(0)  | /* M360_MEMC_OR_PGME | */
                           M360_MEMC_OR_32BIT    | M360_MEMC_OR_DRAM;
-	m360.memc[7].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
-
-	/*
-	 * FIXME: here we should wait for 8 refresh cycles...
-	 */
-	/*
-	 * Step 12a: test the ram, if wanted
-	 * FIXME: when do we call this?
-	 * -> only during firmware execution
-	 * -> perform intesive test only on request
-	 * -> ensure, that results are stored properly
-	 */
+  m360.memc[7].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
+
+  /*
+   * FIXME: here we should wait for 8 refresh cycles...
+   */
+  /*
+   * Step 12a: test the ram, if wanted
+   * FIXME: when do we call this?
+   * -> only during firmware execution
+   * -> perform intesive test only on request
+   * -> ensure, that results are stored properly
+   */
 #if 0 /* FIXME: activate RAM tests again */
-	{
-	  void *ram_base, *ram_end, *code_loc;
-	  extern char ramtest_start,ramtest_end;
-	  ram_base = &ramtest_start;
-	  ram_end  = &ramtest_end;
-	  code_loc = (void *)ramtest_exec;
-	  if ((ram_base < ram_end) &&
-	    !((ram_base <= code_loc) && (code_loc < ram_end))) {
-	    ramtest_exec(ram_base,ram_end);
-	  }
-	}
+  {
+    void *ram_base, *ram_end, *code_loc;
+    extern char ramtest_start,ramtest_end;
+    ram_base = &ramtest_start;
+    ram_end  = &ramtest_end;
+    code_loc = (void *)ramtest_exec;
+    if ((ram_base < ram_end) &&
+      !((ram_base <= code_loc) && (code_loc < ram_end))) {
+      ramtest_exec(ram_base,ram_end);
+    }
+  }
 #endif
-	/*
-	 * Step 13: Copy  the exception vector table to system RAM
-	 */
-	m68k_get_vbr (vbr);
-	for (i = 0; i < 256; ++i)
-		M68Kvec[i] = vbr[i];
-	m68k_set_vbr (M68Kvec);
-
-	/*
-	 * Step 14: More system initialization
-	 * SDCR (Serial DMA configuration register)
-	 *	Disable SDMA during FREEZE
-	 *	Give SDMA priority over all interrupt handlers
-	 *	Set DMA arbiration level to 4
-	 * CICR (CPM interrupt configuration register):
-	 *	SCC1 requests at SCCa position
-	 *	SCC2 requests at SCCb position
-	 *	SCC3 requests at SCCc position
-	 *	SCC4 requests at SCCd position
-	 *	Interrupt request level 4
-	 *	Maintain original priority order
-	 *	Vector base 128
-	 *	SCCs priority grouped at top of table
-	 */
-	m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
-	m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
-						(4 << 13) | (0x1F << 8) | (128);
-
-	/*
-	 * Step 15: Set module configuration register
-	 *	Disable timers during FREEZE
-	 *	Enable bus monitor during FREEZE
-	 *	BCLRO* arbitration level 3
-	 *	No show cycles
-	 *	User/supervisor access
-	 *	Bus clear interupt service level 7
-	 *	SIM60 interrupt sources higher priority than CPM
-	 */
-	m360.mcr = 0x4C7F;
+  /*
+   * Step 13: Copy  the exception vector table to system RAM
+   */
+  m68k_get_vbr (vbr);
+  for (i = 0; i < 256; ++i)
+    M68Kvec[i] = vbr[i];
+  m68k_set_vbr (M68Kvec);
+
+  /*
+   * Step 14: More system initialization
+   * SDCR (Serial DMA configuration register)
+   *  Disable SDMA during FREEZE
+   *  Give SDMA priority over all interrupt handlers
+   *  Set DMA arbiration level to 4
+   * CICR (CPM interrupt configuration register):
+   *  SCC1 requests at SCCa position
+   *  SCC2 requests at SCCb position
+   *  SCC3 requests at SCCc position
+   *  SCC4 requests at SCCd position
+   *  Interrupt request level 4
+   *  Maintain original priority order
+   *  Vector base 128
+   *  SCCs priority grouped at top of table
+   */
+  m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
+  m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
+            (4 << 13) | (0x1F << 8) | (128);
+
+  /*
+   * Step 15: Set module configuration register
+   *  Disable timers during FREEZE
+   *  Enable bus monitor during FREEZE
+   *  BCLRO* arbitration level 3
+   *  No show cycles
+   *  User/supervisor access
+   *  Bus clear interupt service level 7
+   *  SIM60 interrupt sources higher priority than CPM
+   */
+  m360.mcr = 0x4C7F;
 
 #elif (defined (GEN68360_WITH_SRAM))
    /*
@@ -642,197 +645,197 @@ void _Init68360 (void)
    m360.mcr = 0x4C7F;
 
 #else
-	/*
-	 ***************************************************
-	 * Generic Standalone Motorola 68360               *
-	 *           As described in MC68360 User's Manual *
-	 *           Atlas ACE360                          *
-	 ***************************************************
-	 */
-
-	/*
-	 * Step 6: Is this a power-up reset?
-	 * For now we just ignore this and do *all* the steps
-	 * Someday we might want to:
-	 *	if (Hard, Loss of Clock, Power-up)
-	 *		Do all steps
-	 *	else if (Double bus fault, watchdog or soft reset)
-	 *		Skip to step 12
-	 *	else (must be a CPU32+ reset command)
-	 *		Skip to step 14
-	 */
-
-	/*
-	 * Step 7: Deal with clock synthesizer
-	 * HARDWARE:
-	 *	Change if you're not using an external 25 MHz oscillator.
-	 */
-	m360.clkocr = 0x8F;	/* No more writes, no clock outputs */
-	m360.pllcr = 0xD000;	/* PLL, no writes, no prescale,
-				   no LPSTOP slowdown, PLL X1 */
-	m360.cdvcr = 0x8000;	/* No more writes, no clock division */
-
-	/*
-	 * Step 8: Initialize system protection
-	 *	Enable watchdog
-	 *	Watchdog causes system reset
-	 *	Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
-	 *	Enable double bus fault monitor
-	 *	Enable bus monitor for external cycles
-	 *	1024 clocks for external timeout
-	 */
-	m360.sypcr = 0xEC;
-
-	/*
-	 * Step 9: Clear parameter RAM and reset communication processor module
-	 */
-	for (i = 0 ; i < 192  ; i += sizeof (long)) {
-		*((long *)((char *)&m360 + 0xC00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xD00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xE00 + i)) = 0;
-		*((long *)((char *)&m360 + 0xF00 + i)) = 0;
-	}
-	M360ExecuteRISC (M360_CR_RST);
-
-	/*
-	 * Step 10: Write PEPAR
-	 *	SINTOUT not used (CPU32+ mode)
-	 *	CF1MODE=00 (CONFIG1 input)
-	 *	RAS1* double drive
-	 *	WE0* - WE3*
-	 *	OE* output
-	 *	CAS2* - CAS3*
-	 *	CAS0* - CAS1*
-	 *	CS7*
-	 *	AVEC*
-	 * HARDWARE:
-	 *	Change if you are using a different memory configuration
-	 *	(static RAM, external address multiplexing, etc).
-	 */
-	m360.pepar = 0x0180;
-
-	/*
-	 * Step 11: Remap Chip Select 0 (CS0*), set up GMR
-	 *	32-bit DRAM
-	 *	Internal DRAM address multiplexing
-	 *	60 nsec DRAM
-	 *	180 nsec ROM (3 wait states)
-	 *	15.36 usec DRAM refresh interval
-	 *	The DRAM page size selection is not modified since this
-	 *	startup code may be running in a bootstrap PROM or in
-	 *	a program downloaded by the bootstrap PROM.
-	 */
-	m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) |
-					M360_GMR_RFEN | M360_GMR_RCYC(0) |
-					M360_GMR_DPS_32BIT | M360_GMR_NCS |
-					M360_GMR_GAMX;
-	m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
-								M360_MEMC_BR_V;
-	m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
-							M360_MEMC_OR_8BIT;
-
-	/*
-	 * Step 12: Initialize the system RAM
-	 * Do this only if the DRAM has not already been set up
-	 */
-	if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) {
-		/*
-		 * Set up GMR DRAM page size, option and  base registers
-		 *	Assume 16Mbytes of DRAM
-		 *	60 nsec DRAM
-		 */
-		m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5);
-		m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
-						M360_MEMC_OR_16MB |
-						M360_MEMC_OR_DRAM;
-		m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
-
-		/*
-		 * Wait for chips to power up
-		 *	Perform 8 read cycles
-		 */
-		for (i = 0; i < 50000; i++)
-			continue;
-		for (i = 0; i < 8; ++i)
-			*RamBase_p;
-
-		/*
-		 * Determine memory size (1, 4, or 16 Mbytes)
-		 * Set GMR DRAM page size appropriately.
-		 * The OR is left at 16 Mbytes.  The bootstrap PROM places its
-		 * .data and .bss segments at the top of the 16 Mbyte space.
-		 * A 1 Mbyte or 4 Mbyte DRAM will show up several times in
-		 * the memory map, but will work with the same bootstrap PROM.
-		 */
-		*(volatile char *)&RamBase = 0;
-		*((volatile char *)&RamBase+0x00C01800) = 1;
-		if (*(volatile char *)&RamBase) {
-			m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1);
-		}
-		else {
-			*((volatile char *)&RamBase+0x00801000) = 1;
-			if (*(volatile char *)&RamBase) {
-				m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3);
-			}
-		}
-
-		/*
-		 * Enable parity checking
-		 */
-		m360.memc[1].br |= M360_MEMC_BR_PAREN;
-	}
-	switch (m360.gmr & 0x001C0000) {
-	default:		ramSize =  4 * 1024 * 1024;	break;
-	case M360_GMR_PGS(1):	ramSize =  1 * 1024 * 1024;	break;
-	case M360_GMR_PGS(3):	ramSize =  4 * 1024 * 1024;	break;
-	case M360_GMR_PGS(5):	ramSize = 16 * 1024 * 1024;	break;
-	}
-
-	/*
-	 * Step 13: Copy  the exception vector table to system RAM
-	 */
-	m68k_get_vbr (vbr);
-	for (i = 0; i < 256; ++i)
-		M68Kvec[i] = vbr[i];
-	m68k_set_vbr (M68Kvec);
-
-	/*
-	 * Step 14: More system initialization
-	 * SDCR (Serial DMA configuration register)
-	 *	Enable SDMA during FREEZE
-	 *	Give SDMA priority over all interrupt handlers
-	 *	Set DMA arbiration level to 4
-	 * CICR (CPM interrupt configuration register):
-	 *	SCC1 requests at SCCa position
-	 *	SCC2 requests at SCCb position
-	 *	SCC3 requests at SCCc position
-	 *	SCC4 requests at SCCd position
-	 *	Interrupt request level 4
-	 *	Maintain original priority order
-	 *	Vector base 128
-	 *	SCCs priority grouped at top of table
-	 */
-	m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
-	m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
-						(4 << 13) | (0x1F << 8) | (128);
-
-	/*
-	 * Step 15: Set module configuration register
-	 *	Disable timers during FREEZE
-	 *	Enable bus monitor during FREEZE
-	 *	BCLRO* arbitration level 3
-	 *	No show cycles
-	 *	User/supervisor access
-	 *	Bus clear interrupt service level 7
-	 *	SIM60 interrupt sources higher priority than CPM
-	 */
-	m360.mcr = 0x4C7F;
+  /*
+   ***************************************************
+   * Generic Standalone Motorola 68360               *
+   *           As described in MC68360 User's Manual *
+   *           Atlas ACE360                          *
+   ***************************************************
+   */
+
+  /*
+   * Step 6: Is this a power-up reset?
+   * For now we just ignore this and do *all* the steps
+   * Someday we might want to:
+   *  if (Hard, Loss of Clock, Power-up)
+   *    Do all steps
+   *  else if (Double bus fault, watchdog or soft reset)
+   *    Skip to step 12
+   *  else (must be a CPU32+ reset command)
+   *    Skip to step 14
+   */
+
+  /*
+   * Step 7: Deal with clock synthesizer
+   * HARDWARE:
+   *  Change if you're not using an external 25 MHz oscillator.
+   */
+  m360.clkocr = 0x8F;  /* No more writes, no clock outputs */
+  m360.pllcr = 0xD000;  /* PLL, no writes, no prescale,
+           no LPSTOP slowdown, PLL X1 */
+  m360.cdvcr = 0x8000;  /* No more writes, no clock division */
+
+  /*
+   * Step 8: Initialize system protection
+   *  Enable watchdog
+   *  Watchdog causes system reset
+   *  Next-to-slowest watchdog timeout (21 seconds with 25 MHz oscillator)
+   *  Enable double bus fault monitor
+   *  Enable bus monitor for external cycles
+   *  1024 clocks for external timeout
+   */
+  m360.sypcr = 0xEC;
+
+  /*
+   * Step 9: Clear parameter RAM and reset communication processor module
+   */
+  for (i = 0 ; i < 192  ; i += sizeof (long)) {
+    *((long *)((char *)&m360 + 0xC00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xD00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xE00 + i)) = 0;
+    *((long *)((char *)&m360 + 0xF00 + i)) = 0;
+  }
+  M360ExecuteRISC (M360_CR_RST);
+
+  /*
+   * Step 10: Write PEPAR
+   *  SINTOUT not used (CPU32+ mode)
+   *  CF1MODE=00 (CONFIG1 input)
+   *  RAS1* double drive
+   *  WE0* - WE3*
+   *  OE* output
+   *  CAS2* - CAS3*
+   *  CAS0* - CAS1*
+   *  CS7*
+   *  AVEC*
+   * HARDWARE:
+   *  Change if you are using a different memory configuration
+   *  (static RAM, external address multiplexing, etc).
+   */
+  m360.pepar = 0x0180;
+
+  /*
+   * Step 11: Remap Chip Select 0 (CS0*), set up GMR
+   *  32-bit DRAM
+   *  Internal DRAM address multiplexing
+   *  60 nsec DRAM
+   *  180 nsec ROM (3 wait states)
+   *  15.36 usec DRAM refresh interval
+   *  The DRAM page size selection is not modified since this
+   *  startup code may be running in a bootstrap PROM or in
+   *  a program downloaded by the bootstrap PROM.
+   */
+  m360.gmr = (m360.gmr & 0x001C0000) | M360_GMR_RCNT(23) |
+          M360_GMR_RFEN | M360_GMR_RCYC(0) |
+          M360_GMR_DPS_32BIT | M360_GMR_NCS |
+          M360_GMR_GAMX;
+  m360.memc[0].br = (unsigned long)&_RomBase | M360_MEMC_BR_WP |
+                M360_MEMC_BR_V;
+  m360.memc[0].or = M360_MEMC_OR_WAITS(3) | M360_MEMC_OR_1MB |
+              M360_MEMC_OR_8BIT;
+
+  /*
+   * Step 12: Initialize the system RAM
+   * Do this only if the DRAM has not already been set up
+   */
+  if ((m360.memc[1].br & M360_MEMC_BR_V) == 0) {
+    /*
+     * Set up GMR DRAM page size, option and  base registers
+     *  Assume 16Mbytes of DRAM
+     *  60 nsec DRAM
+     */
+    m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(5);
+    m360.memc[1].or = M360_MEMC_OR_TCYC(0) |
+            M360_MEMC_OR_16MB |
+            M360_MEMC_OR_DRAM;
+    m360.memc[1].br = (unsigned long)&RamBase | M360_MEMC_BR_V;
+
+    /*
+     * Wait for chips to power up
+     *  Perform 8 read cycles
+     */
+    for (i = 0; i < 50000; i++)
+      continue;
+    for (i = 0; i < 8; ++i)
+      *RamBase_p;
+
+    /*
+     * Determine memory size (1, 4, or 16 Mbytes)
+     * Set GMR DRAM page size appropriately.
+     * The OR is left at 16 Mbytes.  The bootstrap PROM places its
+     * .data and .bss segments at the top of the 16 Mbyte space.
+     * A 1 Mbyte or 4 Mbyte DRAM will show up several times in
+     * the memory map, but will work with the same bootstrap PROM.
+     */
+    *(volatile char *)&RamBase = 0;
+    *((volatile char *)&RamBase+0x00C01800) = 1;
+    if (*(volatile char *)&RamBase) {
+      m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(1);
+    }
+    else {
+      *((volatile char *)&RamBase+0x00801000) = 1;
+      if (*(volatile char *)&RamBase) {
+        m360.gmr = (m360.gmr & ~0x001C0000) | M360_GMR_PGS(3);
+      }
+    }
+
+    /*
+     * Enable parity checking
+     */
+    m360.memc[1].br |= M360_MEMC_BR_PAREN;
+  }
+  switch (m360.gmr & 0x001C0000) {
+  default:    ramSize =  4 * 1024 * 1024;  break;
+  case M360_GMR_PGS(1):  ramSize =  1 * 1024 * 1024;  break;
+  case M360_GMR_PGS(3):  ramSize =  4 * 1024 * 1024;  break;
+  case M360_GMR_PGS(5):  ramSize = 16 * 1024 * 1024;  break;
+  }
+
+  /*
+   * Step 13: Copy  the exception vector table to system RAM
+   */
+  m68k_get_vbr (vbr);
+  for (i = 0; i < 256; ++i)
+    M68Kvec[i] = vbr[i];
+  m68k_set_vbr (M68Kvec);
+
+  /*
+   * Step 14: More system initialization
+   * SDCR (Serial DMA configuration register)
+   *  Enable SDMA during FREEZE
+   *  Give SDMA priority over all interrupt handlers
+   *  Set DMA arbiration level to 4
+   * CICR (CPM interrupt configuration register):
+   *  SCC1 requests at SCCa position
+   *  SCC2 requests at SCCb position
+   *  SCC3 requests at SCCc position
+   *  SCC4 requests at SCCd position
+   *  Interrupt request level 4
+   *  Maintain original priority order
+   *  Vector base 128
+   *  SCCs priority grouped at top of table
+   */
+  m360.sdcr = M360_SDMA_SISM_7 | M360_SDMA_SAID_4;
+  m360.cicr = (3 << 22) | (2 << 20) | (1 << 18) | (0 << 16) |
+            (4 << 13) | (0x1F << 8) | (128);
+
+  /*
+   * Step 15: Set module configuration register
+   *  Disable timers during FREEZE
+   *  Enable bus monitor during FREEZE
+   *  BCLRO* arbitration level 3
+   *  No show cycles
+   *  User/supervisor access
+   *  Bus clear interrupt service level 7
+   *  SIM60 interrupt sources higher priority than CPM
+   */
+  m360.mcr = 0x4C7F;
 #endif
 
-	/*
-	 * Copy data, clear BSS, switch stacks and call main()
-	 * Must pass ramSize as argument since the data/bss segment
-	 * may be overwritten.
-	 */
-	_CopyDataClearBSSAndStart (ramSize);
+  /*
+   * Copy data, clear BSS, switch stacks and call main()
+   * Must pass ramSize as argument since the data/bss segment
+   * may be overwritten.
+   */
+  _CopyDataClearBSSAndStart (ramSize);
 }
diff --git a/c/src/lib/libbsp/m68k/mrm332/console/sci.c b/c/src/lib/libbsp/m68k/mrm332/console/sci.c
index 63f9e653e3..299f218e9e 100644
--- a/c/src/lib/libbsp/m68k/mrm332/console/sci.c
+++ b/c/src/lib/libbsp/m68k/mrm332/console/sci.c
@@ -1038,7 +1038,6 @@ rtems_device_driver SciRead (
 {
     rtems_libio_rw_args_t *rw_args;             /* ptr to argument struct */
     char      *buffer;
-    uint16_t   length;
 
     rw_args = (rtems_libio_rw_args_t *) arg;    /* arguments to read() */
 
@@ -1054,8 +1053,6 @@ rtems_device_driver SciRead (
 
     buffer = rw_args->buffer;                   /* points to user's buffer */
 
-    length = rw_args->count;                    /* how many bytes they want */
-
 /*  *buffer = SciReadCharWait();                   wait for a character */
 
     /* if there isn't a character available, wait until one shows up */
@@ -1147,7 +1144,6 @@ rtems_device_driver SciControl (
 {
     rtems_libio_ioctl_args_t *args = arg;       /* rtems arg struct */
     uint16_t   command;                         /* the cmd to execute */
-    uint16_t   unused;                          /* maybe later */
     uint16_t   *ptr;                            /* ptr to user data */
 
 /*printk("%s major=%d minor=%d\r\n", __FUNCTION__,major,minor); */
diff --git a/c/src/lib/libbsp/m68k/mvme162/console/console.c b/c/src/lib/libbsp/m68k/mvme162/console/console.c
index 281fe4c260..d5661ffd60 100644
--- a/c/src/lib/libbsp/m68k/mvme162/console/console.c
+++ b/c/src/lib/libbsp/m68k/mvme162/console/console.c
@@ -1,7 +1,9 @@
 /*
  *  This file contains the MVME162 console IO package.
- *
- *  COPYRIGHT (c) 1989-1999.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2013.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -24,19 +26,10 @@
 
 Ring_buffer_t  Console_Buffer[2];
 
-static bool    Console_Is_Initialized = false;
-
-/* Printk function */
-static void _162Bug_output_char( char c );
-static void _BSP_output_char( char c );
-BSP_output_char_function_type BSP_output_char = _BSP_output_char;
-
-
 /*
  *  Interrupt handler for receiver interrupts
  */
-
-rtems_isr C_Receive_ISR(rtems_vector_number vector)
+static rtems_isr C_Receive_ISR(rtems_vector_number vector)
 {
   register int    ipend, port;
 
@@ -55,44 +48,6 @@ rtems_isr C_Receive_ISR(rtems_vector_number vector)
   }
 }
 
-
-/*
- *  _162Bug_output_char
- *
- *  Output a single character using the 162Bug functions.  The character
- *  will be written to the default output port.
- */
-
-void _162Bug_output_char( char c )
-{
-  asm volatile( "moveb  %0, -(%%sp)\n\t"   /* char to output */
-                "trap   #15\n\t"           /* Trap to 162Bug */
-                ".short 0x20"              /* Code for .OUTCHR */
-    :: "d" (c) );
-}
-
-
-/*
- *  _BSP_output_char
- *
- *  printk() function prototyped in bspIo.h. Does not use termios.
- *
- *  If we have initialized the console device then use it, otherwise
- *  use the 162Bug routines to send it to the default output port.
- */
-
-void _BSP_output_char(char c)
-{
-  if (Console_Is_Initialized)
-    putchar(c);
-  else
-    _162Bug_output_char(c);
-
-  if ('\n' == c)
-    _BSP_output_char('\r');
-}
-
-
 rtems_device_driver console_initialize(
   rtems_device_major_number  major,
   rtems_device_minor_number  minor,
@@ -105,7 +60,6 @@ rtems_device_driver console_initialize(
   /*
    * Initialise receiver interrupts on both ports
    */
-
   for (i = 0; i <= 1; i++) {
     Ring_buffer_Initialize( &Console_Buffer[i] );
     ZWRITE(i, 2, SCC_VECTOR);
@@ -153,7 +107,6 @@ rtems_device_driver console_initialize(
 /*
  *   Non-blocking char input
  */
-
 bool char_ready(int port, char *ch)
 {
   if ( Ring_buffer_Is_empty( &Console_Buffer[port] ) )
@@ -167,8 +120,7 @@ bool char_ready(int port, char *ch)
 /*
  *   Block on char input
  */
-
-char inbyte(int port)
+static char inbyte(int port)
 {
   char tmp_char;
 
@@ -180,8 +132,7 @@ char inbyte(int port)
  *   This routine transmits a character out the SCC.  It no longer supports
  *   XON/XOFF flow control.
  */
-
-void outbyte(char ch, int port)
+static void outbyte(char ch, int port)
 {
   while (1) {
     if (ZREAD0(port) & TX_BUFFER_EMPTY) break;
@@ -192,7 +143,6 @@ void outbyte(char ch, int port)
 /*
  *  Open entry point
  */
-
 rtems_device_driver console_open(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -205,7 +155,6 @@ rtems_device_driver console_open(
 /*
  *  Close entry point
  */
-
 rtems_device_driver console_close(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -218,7 +167,6 @@ rtems_device_driver console_close(
 /*
  * read bytes from the serial port. We only have stdin.
  */
-
 rtems_device_driver console_read(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -253,7 +201,6 @@ rtems_device_driver console_read(
 /*
  * write bytes to the serial port. Stdout and stderr are the same.
  */
-
 rtems_device_driver console_write(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -287,7 +234,6 @@ rtems_device_driver console_write(
 /*
  *  IO Control entry point
  */
-
 rtems_device_driver console_control(
   rtems_device_major_number major,
   rtems_device_minor_number minor,
@@ -296,3 +242,33 @@ rtems_device_driver console_control(
 {
   return RTEMS_SUCCESSFUL;
 }
+
+/*
+ *  _162Bug_output_char
+ *
+ *  Output a single character using the 162Bug functions.  The character
+ *  will be written to the default output port.
+ */
+static void _162Bug_output_char( char c )
+{
+  asm volatile( "moveb  %0, -(%%sp)\n\t"   /* char to output */
+                "trap   #15\n\t"           /* Trap to 162Bug */
+                ".short 0x20"              /* Code for .OUTCHR */
+    :: "d" (c) );
+}
+
+/*
+ *  _BSP_output_char
+ *
+ *  printk() function prototyped in bspIo.h. Does not use termios.
+ *
+ *  If we have initialized the console device then use it, otherwise
+ *  use the 162Bug routines to send it to the default output port.
+ */
+static void _BSP_output_char(char c)
+{
+  _162Bug_output_char(c);
+}
+
+/* Printk function */
+BSP_output_char_function_type BSP_output_char = _BSP_output_char;
diff --git a/c/src/lib/libbsp/m68k/mvme162/include/bsp.h b/c/src/lib/libbsp/m68k/mvme162/include/bsp.h
index 9954bfc5fe..056cb1a2e7 100644
--- a/c/src/lib/libbsp/m68k/mvme162/include/bsp.h
+++ b/c/src/lib/libbsp/m68k/mvme162/include/bsp.h
@@ -1,8 +1,9 @@
-/*  bsp.h
- *
+/*
  *  This include file contains all MVME162fx board IO definitions.
- *
- *  COPYRIGHT (c) 1989-1999.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2014.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -162,7 +163,6 @@ typedef volatile struct {
 #define EXTERN extern
 #endif
 
-
 /*
  *  This value is the default address location of the 162Bug vector table
  *  and is also the default start address of the boards DRAM.  This value
@@ -194,6 +194,12 @@ rtems_isr_entry set_vector(
   int                 type
 );
 
+/*
+ * Prototypes for methods in the BSP that cross file boundaries.
+ */
+bool char_ready(int port, char *ch);
+
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/c/src/lib/libbsp/m68k/mvme162/startup/bspclean.c b/c/src/lib/libbsp/m68k/mvme162/startup/bspclean.c
index 86402ddb29..085f346309 100644
--- a/c/src/lib/libbsp/m68k/mvme162/startup/bspclean.c
+++ b/c/src/lib/libbsp/m68k/mvme162/startup/bspclean.c
@@ -1,7 +1,9 @@
 /*
  *  This routine returns control to 162Bug.
- *
- *  COPYRIGHT (c) 1989-2010.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2014.
  *  On-Line Applications Research Corporation (OAR).
  *
  *  The license and distribution terms for this file may be
@@ -21,9 +23,9 @@
 #include <rtems/zilog/z8036.h>
 #include <page_table.h>
 
-extern void start( void  );
-
-void bsp_return_to_monitor_trap(void)
+static rtems_isr bsp_return_to_monitor_trap(
+  rtems_vector_number vector
+)
 {
   page_table_teardown();
 
@@ -32,18 +34,6 @@ void bsp_return_to_monitor_trap(void)
 
   __asm__ volatile( "trap   #15"  );    /* trap to 162Bug */
   __asm__ volatile( ".short 0x63" );    /* return to 162Bug (.RETURN) */
-                                    /* restart program */
-  /*
-   *  This does not work on the 162....
-   */
-#if 0
-  {  register volatile void *start_addr;
-
-     start_addr = start;
-
-     __asm__ volatile ( "jmp %0@" : "=a" (start_addr) : "0" (start_addr) );
-  }
-#endif
 }
 
 void bsp_fatal_extension(
@@ -53,5 +43,5 @@ void bsp_fatal_extension(
 )
 {
    M68Kvec[ 45 ] = bsp_return_to_monitor_trap;   /* install handler */
-   __asm__ volatile( "trap #13" );  /* insures SUPV mode */
+   __asm__ volatile( "trap #13" );               /* ensures SUPV mode */
 }
diff --git a/c/src/lib/libbsp/m68k/mvme162/timer/timer.c b/c/src/lib/libbsp/m68k/mvme162/timer/timer.c
index 579685ca6b..c7dce0475d 100644
--- a/c/src/lib/libbsp/m68k/mvme162/timer/timer.c
+++ b/c/src/lib/libbsp/m68k/mvme162/timer/timer.c
@@ -27,7 +27,7 @@
 uint32_t            Ttimer_val;
 bool                benchmark_timer_find_average_overhead;
 
-rtems_isr timerisr(void);
+rtems_isr timerisr(rtems_vector_number vector);
 
 void benchmark_timer_initialize(void)
 {
diff --git a/c/src/lib/libbsp/m68k/mvme167/console/console.c b/c/src/lib/libbsp/m68k/mvme167/console/console.c
index 1fcf1069de..7ec174e825 100644
--- a/c/src/lib/libbsp/m68k/mvme167/console/console.c
+++ b/c/src/lib/libbsp/m68k/mvme167/console/console.c
@@ -229,9 +229,8 @@ rtems_isr_entry Prev_modem_isr;     /* Previous modem/timer isr */
 )
 {
   unsigned long i = 20000;  /* In case clock is off */
-  rtems_interval ticks_per_second, start_ticks, end_ticks, current_ticks;
+  rtems_interval start_ticks, end_ticks, current_ticks;
 
-  ticks_per_second = rtems_clock_get_ticks_per_second();
   start_ticks = rtems_clock_get_ticks_since_boot();
   end_ticks = start_ticks + delay;
 
diff --git a/c/src/lib/libbsp/m68k/shared/m68000spurious.c b/c/src/lib/libbsp/m68k/shared/m68000spurious.c
index 95e174a14a..e511ebbe74 100644
--- a/c/src/lib/libbsp/m68k/shared/m68000spurious.c
+++ b/c/src/lib/libbsp/m68k/shared/m68000spurious.c
@@ -31,9 +31,11 @@ rtems_isr bsp_spurious_handler(
    CPU_Interrupt_frame *isf */
 )
 {
+#if 0
+  printk( "Unexpected interrupt (0x%x)\n", vector );
+#else
   char *s;
 
-  printk( "Unexpected interrupt (0x%x)\n", vector );
 /*
   printk( "It looks like we got the interrupt at 0x%x\n", isf->interrupted );
 */
@@ -41,9 +43,7 @@ rtems_isr bsp_spurious_handler(
   /*
    *  Can we print a name?
    */
-
   s = 0;
-#if 0
   if ( vector <= 0x1f ) {
     switch ( vector ) {
       case 1:     s = "INT0";     break;
-- 
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