From 95e0ca9337eb7a5e30abd44235d6c0a077c7892f Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Thu, 8 Nov 2001 23:32:59 +0000 Subject: 2001-11-08 Dennis Ehlin (ECS) This modification is part of the submitted modifications necessary to support the IBM PPC405 family. This submission was reviewed by Thomas Doerfler who ensured it did not negatively impact the ppc403 BSPs. The submission and tracking process was captured as PR50. * shared/asm.h, shared/ppc.h: Added PPC405 support. --- c/src/exec/score/cpu/powerpc/ChangeLog | 9 +++++++++ c/src/exec/score/cpu/powerpc/asm.h | 13 ++++++++++--- c/src/exec/score/cpu/powerpc/rtems/score/ppc.h | 8 ++++++-- c/src/exec/score/cpu/powerpc/shared/asm.h | 13 ++++++++++--- c/src/exec/score/cpu/powerpc/shared/ppc.h | 8 ++++++-- 5 files changed, 41 insertions(+), 10 deletions(-) (limited to 'c') diff --git a/c/src/exec/score/cpu/powerpc/ChangeLog b/c/src/exec/score/cpu/powerpc/ChangeLog index e89f4322e4..3bea72892a 100644 --- a/c/src/exec/score/cpu/powerpc/ChangeLog +++ b/c/src/exec/score/cpu/powerpc/ChangeLog @@ -1,3 +1,12 @@ +2001-11-08 Dennis Ehlin (ECS) + + This modification is part of the submitted modifications necessary to + support the IBM PPC405 family. This submission was reviewed by + Thomas Doerfler who ensured it did + not negatively impact the ppc403 BSPs. The submission and tracking + process was captured as PR50. + * shared/asm.h, shared/ppc.h: Added PPC405 support. + 2001-10-22 Andy Dachs * shared/ppc.h: Added mpc8260 support. diff --git a/c/src/exec/score/cpu/powerpc/asm.h b/c/src/exec/score/cpu/powerpc/asm.h index 3c2e28ad5c..a33ee828d4 100644 --- a/c/src/exec/score/cpu/powerpc/asm.h +++ b/c/src/exec/score/cpu/powerpc/asm.h @@ -164,10 +164,10 @@ */ #define srr0 0x01a #define srr1 0x01b -#ifdef ppc403 +#if defined(ppc403) || defined(ppc405) #define srr2 0x3de /* IBM 400 series only */ #define srr3 0x3df /* IBM 400 series only */ -#endif /* ppc403 */ +#endif /* ppc403 or ppc405 */ #define sprg0 0x110 #define sprg1 0x111 @@ -177,15 +177,22 @@ #define dar 0x013 /* Data Address Register */ #define dec 0x016 /* Decrementer Register */ -#if defined(ppc403) +#if defined(ppc403) || defined(ppc405) /* the following SPR/DCR registers exist only in IBM 400 series */ #define dear 0x3d5 #define evpr 0x3d6 /* SPR: exception vector prefix register */ #define iccr 0x3fb /* SPR: instruction cache control reg. */ #define dccr 0x3fa /* SPR: data cache control reg. */ +#if defined (ppc403) #define exisr 0x040 /* DCR: external interrupt status register */ #define exier 0x042 /* DCR: external interrupt enable register */ +#endif /* ppc403 */ +#if defined(ppc405) +#define exisr 0x0C0 /* DCR: external interrupt status register */ +#define exier 0x0C2 /* DCR: external interrupt enable register */ +#endif /* ppc405 */ + #define br0 0x080 /* DCR: memory bank register 0 */ #define br1 0x081 /* DCR: memory bank register 1 */ #define br2 0x082 /* DCR: memory bank register 2 */ diff --git a/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h b/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h index 7708d7c21c..dcfb8b968a 100644 --- a/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h +++ b/c/src/exec/score/cpu/powerpc/rtems/score/ppc.h @@ -124,7 +124,7 @@ extern "C" { #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD #define PPC_HAS_DOUBLE 0 -#elif defined(ppc403) +#elif defined(ppc403) || defined(ppc405) /* * IBM 403 * @@ -133,7 +133,11 @@ extern "C" { * Does not have user mode. */ +#if defined(ppc403) #define CPU_MODEL_NAME "PowerPC 403" +#elif defined (ppc405) +#define CPU_MODEL_NAME "PowerPC 405" +#endif #define PPC_ALIGNMENT 4 #define PPC_CACHE_ALIGNMENT 16 #define PPC_HAS_RFCI 1 @@ -504,7 +508,7 @@ extern "C" { #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET -#if defined(ppc403) +#if defined(ppc403) || defined(ppc405) #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ diff --git a/c/src/exec/score/cpu/powerpc/shared/asm.h b/c/src/exec/score/cpu/powerpc/shared/asm.h index 3c2e28ad5c..a33ee828d4 100644 --- a/c/src/exec/score/cpu/powerpc/shared/asm.h +++ b/c/src/exec/score/cpu/powerpc/shared/asm.h @@ -164,10 +164,10 @@ */ #define srr0 0x01a #define srr1 0x01b -#ifdef ppc403 +#if defined(ppc403) || defined(ppc405) #define srr2 0x3de /* IBM 400 series only */ #define srr3 0x3df /* IBM 400 series only */ -#endif /* ppc403 */ +#endif /* ppc403 or ppc405 */ #define sprg0 0x110 #define sprg1 0x111 @@ -177,15 +177,22 @@ #define dar 0x013 /* Data Address Register */ #define dec 0x016 /* Decrementer Register */ -#if defined(ppc403) +#if defined(ppc403) || defined(ppc405) /* the following SPR/DCR registers exist only in IBM 400 series */ #define dear 0x3d5 #define evpr 0x3d6 /* SPR: exception vector prefix register */ #define iccr 0x3fb /* SPR: instruction cache control reg. */ #define dccr 0x3fa /* SPR: data cache control reg. */ +#if defined (ppc403) #define exisr 0x040 /* DCR: external interrupt status register */ #define exier 0x042 /* DCR: external interrupt enable register */ +#endif /* ppc403 */ +#if defined(ppc405) +#define exisr 0x0C0 /* DCR: external interrupt status register */ +#define exier 0x0C2 /* DCR: external interrupt enable register */ +#endif /* ppc405 */ + #define br0 0x080 /* DCR: memory bank register 0 */ #define br1 0x081 /* DCR: memory bank register 1 */ #define br2 0x082 /* DCR: memory bank register 2 */ diff --git a/c/src/exec/score/cpu/powerpc/shared/ppc.h b/c/src/exec/score/cpu/powerpc/shared/ppc.h index 7708d7c21c..dcfb8b968a 100644 --- a/c/src/exec/score/cpu/powerpc/shared/ppc.h +++ b/c/src/exec/score/cpu/powerpc/shared/ppc.h @@ -124,7 +124,7 @@ extern "C" { #define PPC_LOW_POWER_MODE PPC_LOW_POWER_MODE_STANDARD #define PPC_HAS_DOUBLE 0 -#elif defined(ppc403) +#elif defined(ppc403) || defined(ppc405) /* * IBM 403 * @@ -133,7 +133,11 @@ extern "C" { * Does not have user mode. */ +#if defined(ppc403) #define CPU_MODEL_NAME "PowerPC 403" +#elif defined (ppc405) +#define CPU_MODEL_NAME "PowerPC 405" +#endif #define PPC_ALIGNMENT 4 #define PPC_CACHE_ALIGNMENT 16 #define PPC_HAS_RFCI 1 @@ -504,7 +508,7 @@ extern "C" { #define PPC_IRQ_FIRST PPC_IRQ_SYSTEM_RESET -#if defined(ppc403) +#if defined(ppc403) || defined(ppc405) #define PPC_IRQ_CRIT PPC_IRQ_SYSTEM_RESET /*0x00100- Critical int. pin */ #define PPC_IRQ_PIT (PPC_STD_IRQ_LAST+1) /*0x01000- Pgm interval timer*/ -- cgit v1.2.3