From 4d6b3b66e1001e60dc2cf11ad76638da6b0d10bb Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Fri, 12 Jan 2001 13:28:27 +0000 Subject: 2001-01-12 Joel Sherrill * include/bsp.h, timer/timer.c: Updated so timer appears to work and support tm27. I would prefer to time a software interrupt rather than an use an extra timer though. --- c/src/lib/libbsp/mips/jmr3904/ChangeLog | 6 ++++++ c/src/lib/libbsp/mips/jmr3904/include/bsp.h | 31 +++++++++++++++++++++++++++-- c/src/lib/libbsp/mips/jmr3904/timer/timer.c | 22 ++++++++++---------- 3 files changed, 46 insertions(+), 13 deletions(-) (limited to 'c') diff --git a/c/src/lib/libbsp/mips/jmr3904/ChangeLog b/c/src/lib/libbsp/mips/jmr3904/ChangeLog index 2a1645c40e..56cdcebb97 100644 --- a/c/src/lib/libbsp/mips/jmr3904/ChangeLog +++ b/c/src/lib/libbsp/mips/jmr3904/ChangeLog @@ -1,3 +1,9 @@ +2001-01-12 Joel Sherrill + + * include/bsp.h, timer/timer.c: Updated so timer appears to + work and support tm27. I would prefer to time a software + interrupt rather than an use an extra timer though. + 2001-01-09 Joel Sherrill * clock/clockdrv.c: Clean up. diff --git a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h index 78d602b120..7f147040c2 100644 --- a/c/src/lib/libbsp/mips/jmr3904/include/bsp.h +++ b/c/src/lib/libbsp/mips/jmr3904/include/bsp.h @@ -44,16 +44,42 @@ extern "C" { * */ -#define MUST_WAIT_FOR_INTERRUPT 0 +#define MUST_WAIT_FOR_INTERRUPT 1 +#if 0 #define Install_tm27_vector( handler ) \ (void) set_vector( handler, TX3904_IRQ_SOFTWARE_1, 1 ); \ #define Cause_tm27_intr() \ + asm volatile ( "syscall 0x01" : : ); + +#define CLOCK_VECTOR TX3904_IRQ_TMR0 #define Clear_tm27_intr() #define Lower_tm27_intr() +#else +#define Install_tm27_vector( handler ) \ + (void) set_vector( handler, TX3904_IRQ_TMR0, 1 ); \ + +#define Cause_tm27_intr() \ + do { \ + unsigned32 _clicks = 20; \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, _clicks ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0xC0 ); \ + *((volatile unsigned32 *) 0xFFFFC01C) = 0x00000700; \ + } while(0) + +#define Clear_tm27_intr() \ + TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0x03 ); + +#define Lower_tm27_intr() \ + mips_enable_in_interrupt_mask( 0xff01 ); + +#endif /* Constants */ @@ -77,7 +103,8 @@ extern rtems_configuration_table BSP_Configuration; void bsp_cleanup( void ); -rtems_isr_entry set_vector( rtems_isr_entry, unsigned int, unsigned int ); +rtems_isr_entry set_vector( + rtems_isr_entry, rtems_vector_number, int ); #ifdef __cplusplus } diff --git a/c/src/lib/libbsp/mips/jmr3904/timer/timer.c b/c/src/lib/libbsp/mips/jmr3904/timer/timer.c index f2fddab5ea..5a4375fe5e 100644 --- a/c/src/lib/libbsp/mips/jmr3904/timer/timer.c +++ b/c/src/lib/libbsp/mips/jmr3904/timer/timer.c @@ -26,21 +26,21 @@ void Timer_initialize() * it run long enough and accurate enough not to require an interrupt. * but if it ever does generate an interrupt, we will simply fault. * - * NOTE: This is identical to the clock driver initialization + * NOTE: This is similar to the clock driver initialization * with the exception that the divider is disabled and * the compare register is set to the maximum value. */ - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CCDR, 0x3 ); - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TRR, 0x0 ); - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_CPRA, 0xFFFFFFFF ); - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TISR, 0x00 ); - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_ITMR, 0x8001 ); - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0xc0 ); - *((volatile unsigned32 *) 0xFFFFC01C) = 0x00000700; + TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_CCDR, 0x3 ); + TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_TRR, 0x0 ); + TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_CPRA, 0xFFFFFFFF ); + TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_TISR, 0x00 ); + TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_ITMR, 0x8001 ); + TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_TCR, 0x20 ); + TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_TCR, 0xe0 ); } -#define AVG_OVERHEAD 0 /* It typically takes 24 instructions */ +#define AVG_OVERHEAD 0 /* It typically takes N instructions */ /* to start/stop the timer. */ #define LEAST_VALID 1 /* Don't trust a value lower than this */ /* tx39 simulator can count instructions. :) */ @@ -49,8 +49,8 @@ int Read_timer() { rtems_unsigned32 total; - TX3904_TIMER_WRITE( TX3904_TIMER0_BASE, TX3904_TIMER_TCR, 0x03 ); - total = TX3904_TIMER_READ( TX3904_TIMER0_BASE, TX3904_TIMER_TRR ); + TX3904_TIMER_WRITE( TX3904_TIMER1_BASE, TX3904_TIMER_TCR, 0x03 ); + total = TX3904_TIMER_READ( TX3904_TIMER1_BASE, TX3904_TIMER_TRR ); if ( Timer_driver_Find_average_overhead == 1 ) return total; /* in one microsecond units */ -- cgit v1.2.3