From 4c4974e81f1d8cfcc2677be528144a8e68466873 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 20 May 2010 13:15:35 +0000 Subject: 2010-05-20 Sebastian Huber * make/custom/lpc32xx.inc, make/custom/lpc32xx_mzx_boot_int.cfg, startup/linkcmds.lpc32xx_mzx_boot_int: New files. * Makefile.am, configure.ac, preinstall.am, include/bsp.h, include/bspopts.h.in, include/lpc32xx.h, irq/irq.c, make/custom/lpc32xx_phycore.cfg, startup/bspstart.c, startup/bspstarthooks.c: Changes throughout. --- c/src/lib/libbsp/arm/lpc32xx/ChangeLog | 9 + c/src/lib/libbsp/arm/lpc32xx/Makefile.am | 5 +- c/src/lib/libbsp/arm/lpc32xx/configure.ac | 4 + c/src/lib/libbsp/arm/lpc32xx/include/bsp.h | 2 + c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in | 3 + c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h | 2 + c/src/lib/libbsp/arm/lpc32xx/irq/irq.c | 12 +- .../lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc | 14 ++ .../lpc32xx/make/custom/lpc32xx_mzx_boot_int.cfg | 7 + .../arm/lpc32xx/make/custom/lpc32xx_phycore.cfg | 9 +- c/src/lib/libbsp/arm/lpc32xx/preinstall.am | 4 + c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c | 78 +------ .../lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c | 234 +++++++++++++-------- .../lpc32xx/startup/linkcmds.lpc32xx_mzx_boot_int | 57 +++++ 14 files changed, 258 insertions(+), 182 deletions(-) create mode 100644 c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc create mode 100644 c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_boot_int.cfg create mode 100644 c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx_boot_int (limited to 'c') diff --git a/c/src/lib/libbsp/arm/lpc32xx/ChangeLog b/c/src/lib/libbsp/arm/lpc32xx/ChangeLog index 217c8a9c18..99366d0937 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/ChangeLog +++ b/c/src/lib/libbsp/arm/lpc32xx/ChangeLog @@ -1,3 +1,12 @@ +2010-05-20 Sebastian Huber + + * make/custom/lpc32xx.inc, make/custom/lpc32xx_mzx_boot_int.cfg, + startup/linkcmds.lpc32xx_mzx_boot_int: New files. + * Makefile.am, configure.ac, preinstall.am, include/bsp.h, + include/bspopts.h.in, include/lpc32xx.h, irq/irq.c, + make/custom/lpc32xx_phycore.cfg, startup/bspstart.c, + startup/bspstarthooks.c: Changes throughout. + 2010-05-20 Sebastian Huber * make/custom/lpc32xx_phycore.cfg: Workaround for GCC bug 38644. diff --git a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am index 2f0d476692..69ae723625 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/Makefile.am +++ b/c/src/lib/libbsp/arm/lpc32xx/Makefile.am @@ -33,6 +33,7 @@ include_bsp_HEADERS += ../../shared/include/utility.h include_bsp_HEADERS += ../../shared/include/irq-generic.h include_bsp_HEADERS += ../../shared/include/irq-info.h include_bsp_HEADERS += ../../shared/include/stackalloc.h +include_bsp_HEADERS += ../../shared/include/uart-output-char.h include_bsp_HEADERS += ../../shared/tod.h include_bsp_HEADERS += ../shared/include/linker-symbols.h include_bsp_HEADERS += ../shared/include/start.h @@ -60,7 +61,8 @@ project_lib_DATA = start.$(OBJEXT) project_lib_DATA += startup/linkcmds project_lib_DATA += ../shared/startup/linkcmds.base -EXTRA_DIST = startup/linkcmds.lpc32xx_phycore +EXTRA_DIST = startup/linkcmds.lpc32xx_phycore \ + startup/linkcmds.lpc32xx_mzx_boot_int ############################################################################### # LibBSP # @@ -83,6 +85,7 @@ libbsp_a_SOURCES += ../../shared/bootcard.c \ ../../shared/gnatinstallhandler.c \ ../../shared/sbrk.c \ ../../shared/src/stackalloc.c \ + ../../shared/src/uart-output-char.c \ ../shared/abort/simple_abort.c # Startup diff --git a/c/src/lib/libbsp/arm/lpc32xx/configure.ac b/c/src/lib/libbsp/arm/lpc32xx/configure.ac index c9f84e8fff..96691024af 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/configure.ac +++ b/c/src/lib/libbsp/arm/lpc32xx/configure.ac @@ -63,6 +63,10 @@ RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_U6CLK],[clock configuration for UART 6]) RTEMS_BSPOPTS_SET([LPC32XX_CONFIG_UART_CLKMODE],[*],[0x00000200U]) RTEMS_BSPOPTS_HELP([LPC32XX_CONFIG_UART_CLKMODE],[clock mode configuration for UARTs]) +RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[lpc32xx_boot],[1]) +RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_MMU],[*],[]) +RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_MMU],[disable MMU]) + RTEMS_BSPOPTS_SET([LPC32XX_DISABLE_READ_WRITE_DATA_CACHE],[*],[]) RTEMS_BSPOPTS_HELP([LPC32XX_DISABLE_READ_WRITE_DATA_CACHE],[disable cache for read-write data sections]) diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h index fcee27899a..bef90e1333 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h +++ b/c/src/lib/libbsp/arm/lpc32xx/include/bsp.h @@ -100,6 +100,8 @@ static inline unsigned lpc32xx_timer(void) return timer->tc; } +#define BSP_CONSOLE_UART_BASE 0x40090000 + /** @} */ /** diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in b/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in index b5054133d3..a75bc57b88 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in +++ b/c/src/lib/libbsp/arm/lpc32xx/include/bspopts.h.in @@ -33,6 +33,9 @@ /* clock mode configuration for UARTs */ #undef LPC32XX_CONFIG_UART_CLKMODE +/* disable MMU */ +#undef LPC32XX_DISABLE_MMU + /* disable MMU protection of read-only sections */ #undef LPC32XX_DISABLE_READ_ONLY_PROTECTION diff --git a/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h index 0c90c4355b..3efda3141b 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h +++ b/c/src/lib/libbsp/arm/lpc32xx/include/lpc32xx.h @@ -22,6 +22,8 @@ #ifndef LIBBSP_ARM_LPC32XX_LPC32XX_H #define LIBBSP_ARM_LPC32XX_LPC32XX_H +#include + /** * @defgroup lpc32xx_reg Register Definitions * diff --git a/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c b/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c index 9a569c4a76..4ea1c1cc1c 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c +++ b/c/src/lib/libbsp/arm/lpc32xx/irq/irq.c @@ -308,12 +308,18 @@ void lpc32xx_set_exception_handler( ) { if ((unsigned) exception < MAX_EXCEPTIONS) { - uint32_t *table = (uint32_t *) bsp_section_vector_begin + MAX_EXCEPTIONS; + #ifndef LPC32XX_DISABLE_MMU + uint32_t *table = (uint32_t *) bsp_section_vector_begin + MAX_EXCEPTIONS; + #else + uint32_t *table = (uint32_t *) bsp_section_start_begin + MAX_EXCEPTIONS; + #endif table [exception] = (uint32_t) handler; - rtems_cache_flush_multiple_data_lines(NULL, 64); - rtems_cache_invalidate_multiple_data_lines(NULL, 64); + #ifndef LPC32XX_DISABLE_MMU + rtems_cache_flush_multiple_data_lines(table, 64); + rtems_cache_invalidate_multiple_instruction_lines(NULL, 64); + #endif } } diff --git a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc new file mode 100644 index 0000000000..b79183ae9c --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx.inc @@ -0,0 +1,14 @@ +# +# Config file for LPC32XX. +# +# $Id$ +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU = arm + +CPU_CFLAGS = -mstructure-size-boundary=8 -mcpu=arm926ej-s -mfpu=vfp -mfloat-abi=soft -mthumb \ + -fno-schedule-insns2 + +CFLAGS_OPTIMIZE_V = -Os -g diff --git a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_boot_int.cfg b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_boot_int.cfg new file mode 100644 index 0000000000..398f5e0b33 --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_mzx_boot_int.cfg @@ -0,0 +1,7 @@ +# +# Config file for boot loader. +# +# $Id$ +# + +include $(RTEMS_ROOT)/make/custom/lpc32xx.inc diff --git a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg index c949db3fa3..36e0d19b9d 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg +++ b/c/src/lib/libbsp/arm/lpc32xx/make/custom/lpc32xx_phycore.cfg @@ -4,11 +4,4 @@ # $Id$ # -include $(RTEMS_ROOT)/make/custom/default.cfg - -RTEMS_CPU = arm - -CPU_CFLAGS = -mstructure-size-boundary=8 -mcpu=arm926ej-s -mfpu=vfp -mfloat-abi=soft -mthumb \ - -fno-schedule-insns2 - -CFLAGS_OPTIMIZE_V = -Os -g +include $(RTEMS_ROOT)/make/custom/lpc32xx.inc diff --git a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am index 52840cf7f6..b9eb42f3b8 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/preinstall.am +++ b/c/src/lib/libbsp/arm/lpc32xx/preinstall.am @@ -78,6 +78,10 @@ $(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h +$(PROJECT_INCLUDE)/bsp/uart-output-char.h: ../../shared/include/uart-output-char.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) + $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/uart-output-char.h +PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/uart-output-char.h + $(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/tod.h diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c index a005054222..c8f0a728ba 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c +++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstart.c @@ -7,7 +7,7 @@ */ /* - * Copyright (c) 2009 + * Copyright (c) 2009, 2010 * embedded brains GmbH * Obere Lagerstr. 30 * D-82178 Puchheim @@ -27,22 +27,6 @@ #include #include -/* FIXME */ -#define CONSOLE_RBR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00)) -#define CONSOLE_THR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00)) -#define CONSOLE_DLL (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x00)) -#define CONSOLE_DLM (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x04)) -#define CONSOLE_IER (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x04)) -#define CONSOLE_IIR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x08)) -#define CONSOLE_FCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x08)) -#define CONSOLE_LCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x0C)) -#define CONSOLE_LSR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x14)) -#define CONSOLE_SCR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x1C)) -#define CONSOLE_ACR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x20)) -#define CONSOLE_ICR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x24)) -#define CONSOLE_FDR (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x28)) -#define CONSOLE_TER (*(volatile uint32_t *) (LPC32XX_BASE_UART_5 + 0x30)) - static void lpc32xx_timer_initialize(void) { volatile lpc_timer *timer = LPC32XX_STANDARD_TIMER; @@ -60,42 +44,6 @@ static void lpc32xx_timer_initialize(void) void bsp_start(void) { - uint32_t uartclk_ctrl = 0; - - #ifdef LPC32XX_CONFIG_U3CLK - uartclk_ctrl |= 1U << 0; - LPC32XX_U3CLK = LPC32XX_CONFIG_U3CLK; - #endif - #ifdef LPC32XX_CONFIG_U4CLK - uartclk_ctrl |= 1U << 1; - LPC32XX_U4CLK = LPC32XX_CONFIG_U4CLK; - #endif - #ifdef LPC32XX_CONFIG_U5CLK - uartclk_ctrl |= 1U << 2; - LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK; - #endif - #ifdef LPC32XX_CONFIG_U6CLK - uartclk_ctrl |= 1U << 3; - LPC32XX_U6CLK = LPC32XX_CONFIG_U6CLK; - #endif - - #ifdef LPC32XX_CONFIG_UART_CLKMODE - LPC32XX_UART_CLKMODE = LPC32XX_CONFIG_UART_CLKMODE; - #endif - - LPC32XX_UARTCLK_CTRL = uartclk_ctrl; - LPC32XX_UART_CTRL = 0x0; - LPC32XX_UART_LOOP = 0x0; - - /* FIXME */ - CONSOLE_LCR = 0x0; - CONSOLE_IER = 0x0; - CONSOLE_LCR = 0x80; - CONSOLE_DLL = 0x1; /* Clock is already set in LPC32XX_U5CLK */ - CONSOLE_DLM = 0x0; - CONSOLE_LCR = 0x3; - CONSOLE_FCR = 0x7; - if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) { _CPU_Fatal_halt(0xe); } @@ -107,27 +55,3 @@ void bsp_start(void) lpc32xx_timer_initialize(); } - -#define UART_LSR_THRE 0x00000020U - -static void lpc32xx_console_wait(void) -{ - while ((CONSOLE_LSR & UART_LSR_THRE) == 0) { - /* Wait */ - } -} - -static void lpc32xx_BSP_output_char(char c) -{ - lpc32xx_console_wait(); - - CONSOLE_THR = c; - - if (c == '\n') { - lpc32xx_console_wait(); - - CONSOLE_THR = '\r'; - } -} - -BSP_output_char_function_type BSP_output_char = lpc32xx_BSP_output_char; diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c index 32c9f1a3d1..7c9c7fec5e 100644 --- a/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c +++ b/c/src/lib/libbsp/arm/lpc32xx/startup/bspstarthooks.c @@ -26,6 +26,7 @@ #include #include #include +#include #ifdef LPC32XX_DISABLE_READ_WRITE_DATA_CACHE #define LPC32XX_MMU_READ_WRITE_DATA LPC32XX_MMU_READ_WRITE @@ -56,94 +57,118 @@ static void BSP_START_SECTION lpc32xx_clear_bss(void) } } -typedef struct { - uint32_t begin; - uint32_t end; - uint32_t flags; -} lpc32xx_mmu_config; +#ifndef LPC32XX_DISABLE_MMU + typedef struct { + uint32_t begin; + uint32_t end; + uint32_t flags; + } lpc32xx_mmu_config; -static const BSP_START_DATA_SECTION lpc32xx_mmu_config - lpc32xx_mmu_config_table [] = { + static const BSP_START_DATA_SECTION lpc32xx_mmu_config + lpc32xx_mmu_config_table [] = { + { + .begin = (uint32_t) bsp_section_start_begin, + .end = (uint32_t) bsp_section_start_end, + .flags = LPC32XX_MMU_CODE + }, { + .begin = (uint32_t) bsp_section_vector_begin, + .end = (uint32_t) bsp_section_vector_end, + .flags = LPC32XX_MMU_READ_WRITE_CACHED + }, { + .begin = (uint32_t) bsp_section_text_begin, + .end = (uint32_t) bsp_section_text_end, + .flags = LPC32XX_MMU_CODE + }, { + .begin = (uint32_t) bsp_section_rodata_begin, + .end = (uint32_t) bsp_section_rodata_end, + .flags = LPC32XX_MMU_READ_ONLY_DATA + }, { + .begin = (uint32_t) bsp_section_data_begin, + .end = (uint32_t) bsp_section_data_end, + .flags = LPC32XX_MMU_READ_WRITE_DATA + }, { + .begin = (uint32_t) bsp_section_fast_begin, + .end = (uint32_t) bsp_section_fast_end, + .flags = LPC32XX_MMU_CODE + }, { + .begin = (uint32_t) bsp_section_bss_begin, + .end = (uint32_t) bsp_section_bss_end, + .flags = LPC32XX_MMU_READ_WRITE_DATA + }, { + .begin = (uint32_t) bsp_section_work_begin, + .end = (uint32_t) bsp_section_work_end, + .flags = LPC32XX_MMU_READ_WRITE_DATA + }, { + .begin = (uint32_t) bsp_section_stack_begin, + .end = (uint32_t) bsp_section_stack_end, + .flags = LPC32XX_MMU_READ_WRITE_DATA + }, { + .begin = 0x0U, + .end = 0x100000U, + .flags = LPC32XX_MMU_READ_ONLY_CACHED + }, { + .begin = 0x20000000U, + .end = 0x200c0000U, + .flags = LPC32XX_MMU_READ_WRITE + }, { + .begin = 0x30000000U, + .end = 0x32000000U, + .flags = LPC32XX_MMU_READ_WRITE + }, { + .begin = 0x40000000U, + .end = 0x40100000U, + .flags = LPC32XX_MMU_READ_WRITE + } + }; + + static void BSP_START_SECTION lpc32xx_mmu_set_entries( + uint32_t *ttb, + const lpc32xx_mmu_config *config + ) { - .begin = (uint32_t) bsp_section_start_begin, - .end = (uint32_t) bsp_section_start_end, - .flags = LPC32XX_MMU_CODE - }, { - .begin = (uint32_t) bsp_section_vector_begin, - .end = (uint32_t) bsp_section_vector_end, - .flags = LPC32XX_MMU_READ_WRITE_CACHED - }, { - .begin = (uint32_t) bsp_section_text_begin, - .end = (uint32_t) bsp_section_text_end, - .flags = LPC32XX_MMU_CODE - }, { - .begin = (uint32_t) bsp_section_rodata_begin, - .end = (uint32_t) bsp_section_rodata_end, - .flags = LPC32XX_MMU_READ_ONLY_DATA - }, { - .begin = (uint32_t) bsp_section_data_begin, - .end = (uint32_t) bsp_section_data_end, - .flags = LPC32XX_MMU_READ_WRITE_DATA - }, { - .begin = (uint32_t) bsp_section_fast_begin, - .end = (uint32_t) bsp_section_fast_end, - .flags = LPC32XX_MMU_CODE - }, { - .begin = (uint32_t) bsp_section_bss_begin, - .end = (uint32_t) bsp_section_bss_end, - .flags = LPC32XX_MMU_READ_WRITE_DATA - }, { - .begin = (uint32_t) bsp_section_work_begin, - .end = (uint32_t) bsp_section_work_end, - .flags = LPC32XX_MMU_READ_WRITE_DATA - }, { - .begin = (uint32_t) bsp_section_stack_begin, - .end = (uint32_t) bsp_section_stack_end, - .flags = LPC32XX_MMU_READ_WRITE_DATA - }, { - .begin = 0x0U, - .end = 0x100000U, - .flags = LPC32XX_MMU_READ_ONLY_CACHED - }, { - .begin = 0x20000000U, - .end = 0x200c0000U, - .flags = LPC32XX_MMU_READ_WRITE - }, { - .begin = 0x30000000U, - .end = 0x32000000U, - .flags = LPC32XX_MMU_READ_WRITE - }, { - .begin = 0x40000000U, - .end = 0x40100000U, - .flags = LPC32XX_MMU_READ_WRITE + uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin); + uint32_t iend = + ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end)); + + if (config->begin != config->end) { + while (i < iend) { + ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags; + ++i; + } + } } -}; -static void BSP_START_SECTION lpc32xx_mmu_set_entries( - uint32_t *ttb, - const lpc32xx_mmu_config *config -) -{ - uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin); - uint32_t iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end)); + static void BSP_START_SECTION + lpc32xx_setup_translation_table_and_enable_mmu(uint32_t ctrl) + { + uint32_t const dac = + ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT); + uint32_t *const ttb = (uint32_t *) bsp_section_work_end; + size_t const config_entry_count = + sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]); + size_t i = 0; + + arm_cp15_set_domain_access_control(dac); + arm_cp15_set_translation_table_base(ttb); - if (config->begin != config->end) { - while (i < iend) { - ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags; - ++i; + /* Initialize translation table with invalid entries */ + for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) { + ttb [i] = 0; } + + for (i = 0; i < config_entry_count; ++i) { + lpc32xx_mmu_set_entries(ttb, &lpc32xx_mmu_config_table [i]); + } + + /* Enable MMU and cache */ + ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; + arm_cp15_set_control(ctrl); } -} +#endif static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void) { - uint32_t const dac = - ARM_CP15_DAC_DOMAIN(LPC32XX_MMU_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT); uint32_t ctrl = 0; - uint32_t *const ttb = (uint32_t *) bsp_section_work_end; - size_t const config_entry_count = - sizeof(lpc32xx_mmu_config_table) / sizeof(lpc32xx_mmu_config_table [0]); - size_t i = 0; /* Disable MMU and cache, basic settings */ ctrl = arm_cp15_get_control(); @@ -155,21 +180,9 @@ static void BSP_START_SECTION lpc32xx_mmu_and_cache_setup(void) arm_cp15_cache_invalidate(); arm_cp15_tlb_invalidate(); - arm_cp15_set_domain_access_control(dac); - arm_cp15_set_translation_table_base(ttb); - - /* Initialize translation table with invalid entries */ - for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) { - ttb [i] = 0; - } - - for (i = 0; i < config_entry_count; ++i) { - lpc32xx_mmu_set_entries(ttb, &lpc32xx_mmu_config_table [i]); - } - - /* Enable MMU and cache */ - ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; - arm_cp15_set_control(ctrl); + #ifndef LPC32XX_DISABLE_MMU + lpc32xx_setup_translation_table_and_enable_mmu(ctrl); + #endif } void BSP_START_SECTION bsp_start_hook_0(void) @@ -177,9 +190,44 @@ void BSP_START_SECTION bsp_start_hook_0(void) lpc32xx_mmu_and_cache_setup(); } +static void BSP_START_SECTION bsp_start_config_uarts(void) +{ + uint32_t uartclk_ctrl = 0; + + #ifdef LPC32XX_CONFIG_U3CLK + uartclk_ctrl |= 1U << 0; + LPC32XX_U3CLK = LPC32XX_CONFIG_U3CLK; + #endif + #ifdef LPC32XX_CONFIG_U4CLK + uartclk_ctrl |= 1U << 1; + LPC32XX_U4CLK = LPC32XX_CONFIG_U4CLK; + #endif + #ifdef LPC32XX_CONFIG_U5CLK + uartclk_ctrl |= 1U << 2; + LPC32XX_U5CLK = LPC32XX_CONFIG_U5CLK; + #endif + #ifdef LPC32XX_CONFIG_U6CLK + uartclk_ctrl |= 1U << 3; + LPC32XX_U6CLK = LPC32XX_CONFIG_U6CLK; + #endif + + #ifdef LPC32XX_CONFIG_UART_CLKMODE + LPC32XX_UART_CLKMODE = LPC32XX_CONFIG_UART_CLKMODE; + #endif + + LPC32XX_UARTCLK_CTRL = uartclk_ctrl; + LPC32XX_UART_CTRL = 0x0; + LPC32XX_UART_LOOP = 0x0; + + #ifdef LPC32XX_CONFIG_U5CLK + /* Clock is already set in LPC32XX_U5CLK */ + BSP_CONSOLE_UART_INIT(0x01); + #endif +} + void BSP_START_SECTION bsp_start_hook_1(void) { - /* TODO */ + bsp_start_config_uarts(); /* Copy .text section */ arm_cp15_instruction_cache_invalidate(); diff --git a/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx_boot_int b/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx_boot_int new file mode 100644 index 0000000000..54aef5364c --- /dev/null +++ b/c/src/lib/libbsp/arm/lpc32xx/startup/linkcmds.lpc32xx_mzx_boot_int @@ -0,0 +1,57 @@ +/** + * @file + * + * @ingroup lpc32xx_linker_boot + * + * @brief Memory map. + */ + +/** + * @defgroup lpc32xx_linker_boot Boot Memory Map + * + * @ingroup bsp_linker + * + * @brief Boot memory map. + * + * + * + * + *
Region NameRegion BeginRegion Size
RAM_INT0x08000000256k
+ * + * + * + * + * + * + * + * + * + * + * + * + *
Section NameSection Runtime RegionSection Load Region
.startRAM_INT
.vectorRAM_INT
.textRAM_INTRAM_INT
.rodataRAM_INTRAM_INT
.dataRAM_INTRAM_INT
.fastRAM_INTRAM_INT
.bssRAM_INT
.workRAM_INT
.stackRAM_INT
+ */ + +MEMORY { + RAM_INT (AIW) : ORIGIN = 0x08000000, LENGTH = 256k + NIRVANA : ORIGIN = 0, LENGTH = 0 +} + +REGION_ALIAS ("REGION_START", RAM_INT); +REGION_ALIAS ("REGION_VECTOR", RAM_INT); +REGION_ALIAS ("REGION_TEXT", RAM_INT); +REGION_ALIAS ("REGION_TEXT_LOAD", RAM_INT); +REGION_ALIAS ("REGION_RODATA", RAM_INT); +REGION_ALIAS ("REGION_RODATA_LOAD", RAM_INT); +REGION_ALIAS ("REGION_DATA", RAM_INT); +REGION_ALIAS ("REGION_DATA_LOAD", RAM_INT); +REGION_ALIAS ("REGION_FAST", RAM_INT); +REGION_ALIAS ("REGION_FAST_LOAD", RAM_INT); +REGION_ALIAS ("REGION_BSS", RAM_INT); +REGION_ALIAS ("REGION_WORK", RAM_INT); +REGION_ALIAS ("REGION_STACK", RAM_INT); + +bsp_stack_irq_size = DEFINED (bsp_stack_irq_size) ? bsp_stack_irq_size : 4096; +bsp_stack_abt_size = DEFINED (bsp_stack_abt_size) ? bsp_stack_abt_size : 1024; + +INCLUDE linkcmds.base -- cgit v1.2.3