From 1ec501c567ddc0cd377d6a14766d2306e12ccefc Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 22 Oct 2001 13:42:45 +0000 Subject: 2001-10-22 Andy Dachs * Added mpc8260 directory. * Modified Makefile.am and configure.in to build the contents * mpc8260/Makefile.am, mpc8260/README, mpc8260/clock/Makefile.am, mpc8260/clock/clock.c, mpc8260/console-generic/Makefile.am, mpc8260/console-generic/console-generic.c, mpc8260/cpm/.cvsignore, mpc8260/cpm/Makefile.am, mpc8260/cpm/brg.c, mpc8260/cpm/cp.c, mpc8260/cpm/dpram.c, mpc8260/exceptions/.cvsignore, mpc8260/exceptions/Makefile.am, mpc8260/exceptions/asm_utils.S, mpc8260/exceptions/raw_exception.c, mpc8260/exceptions/raw_exception.h, mpc8260/include/Makefile.am, mpc8260/include/console.h, mpc8260/include/cpm.h, mpc8260/include/mmu.h, mpc8260/include/mpc8260.h, mpc8260/mmu/Makefile.am, mpc8260/mmu/mmu.c, mpc8260/timer/Makefile.am, mpc8260/timer/timer.c: New files. --- c/src/lib/libcpu/powerpc/ChangeLog | 16 + c/src/lib/libcpu/powerpc/mpc8260/Makefile.am | 10 + c/src/lib/libcpu/powerpc/mpc8260/README | 19 + c/src/lib/libcpu/powerpc/mpc8260/clock/Makefile.am | 29 + c/src/lib/libcpu/powerpc/mpc8260/clock/clock.c | 228 +++ .../powerpc/mpc8260/console-generic/Makefile.am | 29 + .../mpc8260/console-generic/console-generic.c | 1143 +++++++++++++++ c/src/lib/libcpu/powerpc/mpc8260/cpm/.cvsignore | 2 + c/src/lib/libcpu/powerpc/mpc8260/cpm/Makefile.am | 29 + c/src/lib/libcpu/powerpc/mpc8260/cpm/brg.c | 204 +++ c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c | 35 + c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c | 91 ++ .../libcpu/powerpc/mpc8260/exceptions/.cvsignore | 2 + .../libcpu/powerpc/mpc8260/exceptions/Makefile.am | 43 + .../libcpu/powerpc/mpc8260/exceptions/asm_utils.S | 65 + .../powerpc/mpc8260/exceptions/raw_exception.c | 205 +++ .../powerpc/mpc8260/exceptions/raw_exception.h | 183 +++ .../lib/libcpu/powerpc/mpc8260/include/Makefile.am | 27 + c/src/lib/libcpu/powerpc/mpc8260/include/console.h | 65 + c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h | 123 ++ c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h | 47 + c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h | 1510 ++++++++++++++++++++ c/src/lib/libcpu/powerpc/mpc8260/mmu/Makefile.am | 29 + c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c | 130 ++ c/src/lib/libcpu/powerpc/mpc8260/timer/Makefile.am | 29 + c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c | 116 ++ 26 files changed, 4409 insertions(+) create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/Makefile.am create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/README create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/clock/Makefile.am create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/clock/clock.c create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/console-generic/Makefile.am create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/cpm/.cvsignore create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/cpm/Makefile.am create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/cpm/brg.c create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/exceptions/.cvsignore create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/exceptions/Makefile.am create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/exceptions/asm_utils.S create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/exceptions/raw_exception.c create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/exceptions/raw_exception.h create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/include/Makefile.am create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/include/console.h create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/mmu/Makefile.am create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/timer/Makefile.am create mode 100644 c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c (limited to 'c') diff --git a/c/src/lib/libcpu/powerpc/ChangeLog b/c/src/lib/libcpu/powerpc/ChangeLog index 6230851eac..4dee3665af 100644 --- a/c/src/lib/libcpu/powerpc/ChangeLog +++ b/c/src/lib/libcpu/powerpc/ChangeLog @@ -1,3 +1,19 @@ +2001-10-22 Andy Dachs + + * Added mpc8260 directory. + * Modified Makefile.am and configure.in to build the contents + * mpc8260/Makefile.am, mpc8260/README, mpc8260/clock/Makefile.am, + mpc8260/clock/clock.c, mpc8260/console-generic/Makefile.am, + mpc8260/console-generic/console-generic.c, mpc8260/cpm/.cvsignore, + mpc8260/cpm/Makefile.am, mpc8260/cpm/brg.c, mpc8260/cpm/cp.c, + mpc8260/cpm/dpram.c, mpc8260/exceptions/.cvsignore, + mpc8260/exceptions/Makefile.am, mpc8260/exceptions/asm_utils.S, + mpc8260/exceptions/raw_exception.c, mpc8260/exceptions/raw_exception.h, + mpc8260/include/Makefile.am, mpc8260/include/console.h, + mpc8260/include/cpm.h, mpc8260/include/mmu.h, + mpc8260/include/mpc8260.h, mpc8260/mmu/Makefile.am, mpc8260/mmu/mmu.c, + mpc8260/timer/Makefile.am, mpc8260/timer/timer.c: New files. + 2001-10-12 Joel Sherrill * mpc6xx/clock/c_clock.c, mpc6xx/clock/c_clock.h, mpc8xx/clock/clock.c, diff --git a/c/src/lib/libcpu/powerpc/mpc8260/Makefile.am b/c/src/lib/libcpu/powerpc/mpc8260/Makefile.am new file mode 100644 index 0000000000..107a550588 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/Makefile.am @@ -0,0 +1,10 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +SUBDIRS = include console-generic clock timer exceptions mmu cpm + +include $(top_srcdir)/../../../../../automake/subdirs.am +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc8260/README b/c/src/lib/libcpu/powerpc/mpc8260/README new file mode 100644 index 0000000000..5853ac444d --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/README @@ -0,0 +1,19 @@ +# +# $Id$ +# Modified from mpc860 version by A. Dachs, 28-4-00 + +Various non BSP dependant support routines. + +clock - Uses the MPC8260 decrementer to + generate RTEMS clock ticks. + +console_generic - Uses the MPC8260 SCCs and SMCs to to serial I/O + +include - console.h: function declarations for console related functions + +timer - Uses the MPC8260 timebase register for timing + tests. It only uses the lower 32 bits + +vectors - MPC8260 specific vector entry points. + Includes CPU dependant, application independant + handlers: alignment. diff --git a/c/src/lib/libcpu/powerpc/mpc8260/clock/Makefile.am b/c/src/lib/libcpu/powerpc/mpc8260/clock/Makefile.am new file mode 100644 index 0000000000..78b2d09d9a --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/clock/Makefile.am @@ -0,0 +1,29 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +PGM = ${ARCH}/clock.rel + +## C sources +C_FILES = clock.c + +clock_rel_OBJECTS = $(C_FILES:%.c=${ARCH}/%.o) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(top_srcdir)/../../../../../automake/compile.am +include $(top_srcdir)/../../../../../automake/lib.am + +# +# (OPTIONAL) Add local stuff here using += +# + +$(PGM): $(clock_rel_OBJECTS) + $(make-rel) + +all-local: ${ARCH} $(PGM) + +EXTRA_DIST = $(C_FILES) + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc8260/clock/clock.c b/c/src/lib/libcpu/powerpc/mpc8260/clock/clock.c new file mode 100644 index 0000000000..672ecf29da --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/clock/clock.c @@ -0,0 +1,228 @@ +/* clock.c + * + * This routine initializes the PIT on the MPC8xx. + * The tick frequency is specified by the bsp. + * + * Author: Jay Monkman (jmonkman@frasca.com) + * Copyright (C) 1998 by Frasca International, Inc. + * + * Derived from c/src/lib/libcpu/ppc/ppc403/clock/clock.c: + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libcpu/hppa1_1/clock/clock.c: + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include +#include + +#include /* for atexit() */ +#include +#include + +volatile rtems_unsigned32 Clock_driver_ticks; +extern int BSP_get_clock_irq_level(); +extern int BSP_connect_clock_handler(rtems_isr_entry); +extern int BSP_disconnect_clock_handler(); + +void Clock_exit( void ); + +rtems_unsigned32 decrementer_value; + +volatile int ClockInitialised = 0; + + +/* + * These are set by clock driver during its init + */ + +rtems_device_major_number rtems_clock_major = ~0; +rtems_device_minor_number rtems_clock_minor; + +/* + * ISR Handler + */ +rtems_isr Clock_isr(rtems_vector_number vector) +{ + int clicks; + + if( ClockInitialised ) { + PPC_Get_decrementer( clicks ); + do { + clicks += decrementer_value; + PPC_Set_decrementer( clicks ); + + Clock_driver_ticks++; + rtems_clock_tick(); + } while( clicks < 100 ); + } +#if 0 + m8260.piscr |= M8260_PISCR_PS; + Clock_driver_ticks++; + rtems_clock_tick(); +#endif + + +} + +void clockOn(void* unused) +{ + + decrementer_value = rtems_configuration_get_microseconds_per_tick() * + rtems_cpu_configuration_get_clicks_per_usec() - 1; + + PPC_Set_decrementer( decrementer_value ); + Clock_driver_ticks = 0; + + ClockInitialised = 1; + + +#if 0 + unsigned desiredLevel; + rtems_unsigned32 pit_value; + + pit_value = (rtems_configuration_get_microseconds_per_tick() * + rtems_cpu_configuration_get_clicks_per_usec()) - 1 ; + + if (pit_value > 0xffff) { /* pit is only 16 bits long */ + rtems_fatal_error_occurred(-1); + } + m8260.sccr &= ~(1<<24); + m8260.pitc = pit_value; + + desiredLevel = BSP_get_clock_irq_level(); + /* set PIT irq level, enable PIT, PIT interrupts */ + /* and clear int. status */ + m8260.piscr = /*M8260_PISCR_PIRQ(desiredLevel) |*/ + M8260_PISCR_PTE | M8260_PISCR_PS | M8260_PISCR_PIE; +#endif +} +/* + * Called via atexit() + * Remove the clock interrupt handler by setting handler to NULL + */ +void +clockOff(void* unused) +{ +#if 0 + /* disable PIT and PIT interrupts */ + m8260.piscr &= ~(M8260_PISCR_PTE | M8260_PISCR_PIE); +#endif + ClockInitialised = 0; +} + +int clockIsOn(void* unused) +{ + return ClockInitialised; +#if 0 + if (m8260.piscr & M8260_PISCR_PIE) return 1; + return 0; +#endif + +} + +/* + * Called via atexit() + * Remove the clock interrupt handler by setting handler to NULL + */ +void +Clock_exit(void) +{ + (void) BSP_disconnect_clock_handler (); +} + +void Install_clock(rtems_isr_entry clock_isr) +{ + Clock_driver_ticks = 0; + + + decrementer_value = rtems_configuration_get_microseconds_per_tick() * + rtems_cpu_configuration_get_clicks_per_usec() - 1; + + PPC_Set_decrementer( decrementer_value ); + + BSP_connect_clock_handler (clock_isr); + + + ClockInitialised = 1; + + atexit(Clock_exit); + +} + +void +ReInstall_clock(rtems_isr_entry new_clock_isr) +{ + BSP_connect_clock_handler (new_clock_isr); +} + + +rtems_device_driver Clock_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + Install_clock( Clock_isr ); + + /* + * make major/minor avail to others such as shared memory driver + */ + + rtems_clock_major = major; + rtems_clock_minor = minor; + + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver Clock_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + rtems_libio_ioctl_args_t *args = pargp; + + if (args == 0) + goto done; + + /* + * This is hokey, but until we get a defined interface + * to do this, it will just be this simple... + */ + + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) { + Clock_isr(BSP_PERIODIC_TIMER); + } + else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { + ReInstall_clock(args->buffer); + } + + done: + return RTEMS_SUCCESSFUL; +} + diff --git a/c/src/lib/libcpu/powerpc/mpc8260/console-generic/Makefile.am b/c/src/lib/libcpu/powerpc/mpc8260/console-generic/Makefile.am new file mode 100644 index 0000000000..bb760de630 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/console-generic/Makefile.am @@ -0,0 +1,29 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +PGM = ${ARCH}/console-generic.rel + +## C sources +C_FILES = console-generic.c + +console_generic_rel_OBJECTS = $(C_FILES:%.c=${ARCH}/%.o) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(top_srcdir)/../../../../../automake/compile.am +include $(top_srcdir)/../../../../../automake/lib.am + +# +# (OPTIONAL) Add local stuff here using += +# + +$(PGM): $(console_generic_rel_OBJECTS) + $(make-rel) + +all-local: ${ARCH} $(PGM) + +EXTRA_DIST = $(C_FILES) + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c new file mode 100644 index 0000000000..542cdcf1c0 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/console-generic/console-generic.c @@ -0,0 +1,1143 @@ +/* + * General Serial I/O functions. + * + * This file contains the functions for performing serial I/O. + * The actual system calls (console_*) should be in the BSP part + * of the source tree. That way different BSPs can use whichever + * SMCs and SCCs they want. Originally, all the stuff was in + * this file, and it caused problems with one BSP using SCC2 + * as /dev/console, others using SMC1 for /dev/console, etc. + * + * On-chip resources used: + * resource minor note + * SMC1 0 + * SMC2 1 + * SCC1 2 + * SCC2 3 + * SCC3 4 + * SCC4 5 + * BRG1 + * BRG2 + * BRG3 + * BRG4 + * Author: Jay Monkman (jmonkman@frasca.com) + * Copyright (C) 1998 by Frasca International, Inc. + * + * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c written by: + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * + * Modifications by Darlene Stewart + * and Charles-Antoine Gauthier + * Copyright (c) 1999, National Research Council of Canada + * + * Modifications by Andy Dachs to add MPC8260 + * support. + * Copyright (c) 2001, Surrey Satellite Technology Ltd + * SCC1 and SSC2 are used on MPC8260ADS board + * SMCs are unused + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include /* for printk */ + + + +/* BSP supplied routine */ +extern int mbx8xx_console_get_configuration(); + + +/* + * Interrupt-driven input buffer + */ +#define RXBUFSIZE 16 + +/* + * I/O buffers and pointers to buffer descriptors. + * Currently, single buffered input is done. This will work only + * if the Rx interrupts are serviced quickly. + * + * TODO: Add a least double buffering for safety. + */ +static volatile char rxBuf[NUM_PORTS][RXBUFSIZE]; +static volatile char txBuf[NUM_PORTS]; + +/* SCC/SMC buffer descriptors */ +static volatile m8260BufferDescriptor_t *RxBd[NUM_PORTS], *TxBd[NUM_PORTS]; + + + +/* Used to track termios private data for callbacks */ +struct rtems_termios_tty *ttyp[NUM_PORTS]; + +/* Used to record previous ISR */ +static rtems_isr_entry old_handler[NUM_PORTS]; + +/* + * Device-specific routines + */ +void m8xx_console_reserve_resources(rtems_configuration_table *); +static int m8xx_smc_set_attributes(int, const struct termios*); +static int m8xx_scc_set_attributes(int, const struct termios*); +static rtems_isr m8xx_smc1_interrupt_handler(rtems_vector_number); +static rtems_isr m8xx_smc2_interrupt_handler(rtems_vector_number); +static rtems_isr m8xx_scc1_interrupt_handler(rtems_vector_number); +static rtems_isr m8xx_scc2_interrupt_handler(rtems_vector_number); +static rtems_isr m8xx_scc3_interrupt_handler(rtems_vector_number); +static rtems_isr m8xx_scc4_interrupt_handler(rtems_vector_number); + + + +/* + * Hardware-dependent portion of tcsetattr(). + */ +static int +m8xx_smc_set_attributes (int minor, const struct termios *t) +{ + int baud, brg=0, csize=0, ssize, psize; + rtems_unsigned16 clen=0, cstopb, parenb, parodd, cread; + + /* Baud rate */ + switch (t->c_cflag & CBAUD) { + default: baud = -1; break; + case B50: baud = 50; break; + case B75: baud = 75; break; + case B110: baud = 110; break; + case B134: baud = 134; break; + case B150: baud = 150; break; + case B200: baud = 200; break; + case B300: baud = 300; break; + case B600: baud = 600; break; + case B1200: baud = 1200; break; + case B1800: baud = 1800; break; + case B2400: baud = 2400; break; + case B4800: baud = 4800; break; + case B9600: baud = 9600; break; + case B19200: baud = 19200; break; + case B38400: baud = 38400; break; + case B57600: baud = 57600; break; + case B115200: baud = 115200; break; + case B230400: baud = 230400; break; + case B460800: baud = 460800; break; + } + if (baud > 0) { + switch( minor ) { + case SMC1_MINOR: + /* SMC1 can only choose between BRG1 and 7 */ + brg = m8xx_get_brg( M8260_SMC1_BRGS, baud*16 ) + 1; + m8260.cmxsmr &= ~0x30; + m8260.cmxsmr |= (brg==1? 0x00: 0x10 ); + break; + case SMC2_MINOR: + /* SMC2 can only choose between BRG2 and 8 */ + brg = m8xx_get_brg( M8260_SMC2_BRGS, baud*16 ) + 1; + m8260.cmxsmr &= ~0x30; + m8260.cmxsmr |= (brg==2? 0x00: 0x01 ); + break; + } + } + + /* Number of data bits */ + switch ( t->c_cflag & CSIZE ) { + case CS5: csize = 5; break; + case CS6: csize = 6; break; + case CS7: csize = 7; break; + case CS8: csize = 8; break; + } + + /* Stop bits */ + if ( t->c_cflag & CSTOPB ) { + cstopb = 0x0400; /* Two stop bits */ + ssize = 2; + } else { + cstopb = 0x0000; /* One stop bit */ + ssize = 1; + } + + /* Parity */ + if ( t->c_cflag & PARENB ) { + parenb = 0x0200; /* Parity enabled on Tx and Rx */ + psize = 1; + } else { + parenb = 0x0000; /* No parity on Tx and Rx */ + psize = 0; + } + + if ( t->c_cflag & PARODD ) + parodd = 0x0000; /* Odd parity */ + else + parodd = 0x0100; + + /* + * Character Length = start + data + parity + stop - 1 + */ + switch ( 1 + csize + psize + ssize - 1 ) { + case 6: clen = 0x3000; break; + case 7: clen = 0x3800; break; + case 8: clen = 0x4000; break; + case 9: clen = 0x4800; break; + case 10: clen = 0x5000; break; + case 11: clen = 0x5800; break; + } + + if ( t->c_cflag & CREAD ) + cread = 0x0023; /* UART normal operation, enable Rx and Tx */ + else + cread = 0x0021; /* UART normal operation, enable Tx */ + + /* Write the SIMODE/SMCMR registers */ + switch (minor) { + case SMC1_MINOR: +/* + m8xx.simode = ( (m8xx.simode & 0xffff8fff) | (brg << 12) ); +*/ + m8260.smc1.smcmr = clen | cstopb | parenb | parodd | cread; + break; + case SMC2_MINOR: + /* CHECK THIS */ +/* + m8xx.simode = ( (m8xx.simode & 0x8fffffff) | (brg << 28) ); +*/ + m8260.smc2.smcmr = clen | cstopb | parenb | parodd | cread; + break; + } + return 0; +} + + +static int +m8xx_scc_set_attributes (int minor, const struct termios *t) +{ + int baud, brg=0; + rtems_unsigned16 csize=0, cstopb, parenb, parodd; + + /* Baud rate */ + switch (t->c_cflag & CBAUD) { + default: baud = -1; break; + case B50: baud = 50; break; + case B75: baud = 75; break; + case B110: baud = 110; break; + case B134: baud = 134; break; + case B150: baud = 150; break; + case B200: baud = 200; break; + case B300: baud = 300; break; + case B600: baud = 600; break; + case B1200: baud = 1200; break; + case B1800: baud = 1800; break; + case B2400: baud = 2400; break; + case B4800: baud = 4800; break; + case B9600: baud = 9600; break; + case B19200: baud = 19200; break; + case B38400: baud = 38400; break; + case B57600: baud = 57600; break; + case B115200: baud = 115200; break; + case B230400: baud = 230400; break; + case B460800: baud = 460800; break; + } + if (baud > 0) { + brg = m8xx_get_brg( M8260_SCC_BRGS, baud*16 ); + m8260.cmxscr &= ~(0xFF000000 >> (8*(minor-SCC1_MINOR)) ); + m8260.cmxscr |= ((brg<<(3+8*(3-(minor-SCC1_MINOR)))) & + (brg<<(8*(3-(minor-SCC1_MINOR))))); + } + /* Number of data bits */ + switch ( t->c_cflag & CSIZE ) { + case CS5: csize = 0x0000; break; + case CS6: csize = 0x1000; break; + case CS7: csize = 0x2000; break; + case CS8: csize = 0x3000; break; + } + + /* Stop bits */ + if ( t->c_cflag & CSTOPB ) + cstopb = 0x4000; /* Two stop bits */ + else + cstopb = 0x0000; /* One stop bit */ + + /* Parity */ + if ( t->c_cflag & PARENB ) + parenb = 0x0010; /* Parity enabled on Tx and Rx */ + else + parenb = 0x0000; /* No parity on Tx and Rx */ + + if ( t->c_cflag & PARODD ) + parodd = 0x0000; /* Odd parity */ + else + parodd = 0x000a; + + /* Write the SICR/PSMR Registers */ + switch (minor) { + case SCC1_MINOR: +/* + m8xx.sicr = ( (m8xx.sicr & 0xffffc0ff) | (brg << 11) | (brg << 8) ); +*/ + m8260.scc1.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc1.psmr & 0x8fe0) ); + break; + case SCC2_MINOR: +/* + m8xx.sicr = ( (m8xx.sicr & 0xffffc0ff) | (brg << 11) | (brg << 8) ); +*/ + m8260.scc2.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc2.psmr & 0x8fe0) ); + break; + case SCC3_MINOR: +/* + m8xx.sicr = ( (m8xx.sicr & 0xffc0ffff) | (brg << 19) | (brg << 16) ); +*/ + m8260.scc3.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc3.psmr & 0x8fe0) ); + break; + case SCC4_MINOR: +/* + m8xx.sicr = ( (m8xx.sicr & 0xc0ffffff) | (brg << 27) | (brg << 24) ); +*/ + m8260.scc4.psmr = ( (cstopb | csize | parenb | parodd) | (m8260.scc4.psmr & 0x8fe0) ); + break; + } + + return 0; +} + + +int +m8xx_uart_setAttributes( + int minor, + const struct termios *t +) +{ + /* + * Check that port number is valid + */ + if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) + return 0; + + switch (minor) { + case SMC1_MINOR: + case SMC2_MINOR: + return m8xx_smc_set_attributes( minor, t ); + + case SCC1_MINOR: + case SCC2_MINOR: + case SCC3_MINOR: + case SCC4_MINOR: + return m8xx_scc_set_attributes( minor, t ); + } + return 0; +} + + +/* + * Interrupt handlers + */ + +static void +m8xx_scc1_interrupt_handler (rtems_vector_number v) +{ + int nb_overflow; + + /* + * Buffer received? + */ + if ((m8260.scc1.sccm & M8260_SCCE_RX) && (m8260.scc1.scce & M8260_SCCE_RX)) { + m8260.scc1.scce = M8260_SCCE_RX; /* Clear the event */ + + + /* Check that the buffer is ours */ + if ((RxBd[SCC1_MINOR]->status & M8260_BD_EMPTY) == 0) { + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC1_MINOR]->buffer, + RxBd[SCC1_MINOR]->length ); + nb_overflow = rtems_termios_enqueue_raw_characters( + (void *)ttyp[SCC1_MINOR], + (char *)RxBd[SCC1_MINOR]->buffer, + (int)RxBd[SCC1_MINOR]->length ); + RxBd[SCC1_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | + M8260_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ + if (m8260.scc1.scce & M8260_SCCE_TX) { + m8260.scc1.scce = M8260_SCCE_TX; /* Clear the event */ + + /* Check that the buffer is ours */ + if ((TxBd[SCC1_MINOR]->status & M8260_BD_READY) == 0) + rtems_termios_dequeue_characters ( + (void *)ttyp[SCC1_MINOR], + (int)TxBd[SCC1_MINOR]->length); + } + +#if 0 + m8260.sipnr_l |= M8260_SIMASK_SCC1; /* Clear pending register */ +#endif +} + +static void +m8xx_scc2_interrupt_handler (rtems_vector_number v) +{ + int nb_overflow; + + /* + * Buffer received? + */ + if ((m8260.scc2.sccm & M8260_SCCE_RX) && (m8260.scc2.scce & M8260_SCCE_RX)) { + m8260.scc2.scce = M8260_SCCE_RX; /* Clear the event */ + + + /* Check that the buffer is ours */ + if ((RxBd[SCC2_MINOR]->status & M8260_BD_EMPTY) == 0) { + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC2_MINOR]->buffer, + RxBd[SCC2_MINOR]->length ); + nb_overflow = rtems_termios_enqueue_raw_characters( + (void *)ttyp[SCC2_MINOR], + (char *)RxBd[SCC2_MINOR]->buffer, + (int)RxBd[SCC2_MINOR]->length ); + RxBd[SCC2_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | + M8260_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ + if (m8260.scc2.scce & M8260_SCCE_TX) { + m8260.scc2.scce = M8260_SCCE_TX; /* Clear the event */ + + /* Check that the buffer is ours */ + if ((TxBd[SCC2_MINOR]->status & M8260_BD_READY) == 0) + rtems_termios_dequeue_characters ( + (void *)ttyp[SCC2_MINOR], + (int)TxBd[SCC2_MINOR]->length); + } + +#if 0 + m8260.sipnr_l |= M8260_SIMASK_SCC2; /* Clear pending register */ +#endif +} + + +static void +m8xx_scc3_interrupt_handler (rtems_vector_number v) +{ + int nb_overflow; + + /* + * Buffer received? + */ + if ((m8260.scc3.sccm & M8260_SCCE_RX) && (m8260.scc3.scce & M8260_SCCE_RX)) { + m8260.scc3.scce = M8260_SCCE_RX; /* Clear the event */ + + + /* Check that the buffer is ours */ + if ((RxBd[SCC3_MINOR]->status & M8260_BD_EMPTY) == 0) { + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC3_MINOR]->buffer, + RxBd[SCC3_MINOR]->length ); + nb_overflow = rtems_termios_enqueue_raw_characters( + (void *)ttyp[SCC3_MINOR], + (char *)RxBd[SCC3_MINOR]->buffer, + (int)RxBd[SCC3_MINOR]->length ); + RxBd[SCC3_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | + M8260_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ + if (m8260.scc3.scce & M8260_SCCE_TX) { + m8260.scc3.scce = M8260_SCCE_TX; /* Clear the event */ + + /* Check that the buffer is ours */ + if ((TxBd[SCC3_MINOR]->status & M8260_BD_READY) == 0) + rtems_termios_dequeue_characters ( + (void *)ttyp[SCC3_MINOR], + (int)TxBd[SCC3_MINOR]->length); + } + + +#if 0 + m8260.sipnr_l |= M8260_SIMASK_SCC3; /* Clear pending register */ +#endif +} + + +static void +m8xx_scc4_interrupt_handler (rtems_vector_number v) +{ + int nb_overflow; + + /* + * Buffer received? + */ + if ((m8260.scc4.sccm & M8260_SCCE_RX) && (m8260.scc4.scce & M8260_SCCE_RX)) { + m8260.scc4.scce = M8260_SCCE_RX; /* Clear the event */ + + + /* Check that the buffer is ours */ + if ((RxBd[SCC4_MINOR]->status & M8260_BD_EMPTY) == 0) { + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SCC4_MINOR]->buffer, + RxBd[SCC4_MINOR]->length ); + nb_overflow = rtems_termios_enqueue_raw_characters( + (void *)ttyp[SCC4_MINOR], + (char *)RxBd[SCC4_MINOR]->buffer, + (int)RxBd[SCC4_MINOR]->length ); + RxBd[SCC4_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | + M8260_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ + if (m8260.scc4.scce & M8260_SCCE_TX) { + m8260.scc4.scce = M8260_SCCE_TX; /* Clear the event */ + + /* Check that the buffer is ours */ + if ((TxBd[SCC4_MINOR]->status & M8260_BD_READY) == 0) + rtems_termios_dequeue_characters ( + (void *)ttyp[SCC4_MINOR], + (int)TxBd[SCC4_MINOR]->length); + } + +#if 0 + m8260.sipnr_l |= M8260_SIMASK_SCC4; /* Clear pending register */ +#endif +} + +static void +m8xx_smc1_interrupt_handler (rtems_vector_number v) +{ + int nb_overflow; + + /* + * Buffer received? + */ + if (m8260.smc1.smce & M8260_SMCE_RX) { + m8260.smc1.smce = M8260_SMCE_RX; /* Clear the event */ + + + /* Check that the buffer is ours */ + if ((RxBd[SMC1_MINOR]->status & M8260_BD_EMPTY) == 0) { + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SMC1_MINOR]->buffer, + RxBd[SMC1_MINOR]->length ); + nb_overflow = rtems_termios_enqueue_raw_characters( + (void *)ttyp[SMC1_MINOR], + (char *)RxBd[SMC1_MINOR]->buffer, + (int)RxBd[SMC1_MINOR]->length ); + RxBd[SMC1_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | + M8260_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ + if (m8260.smc1.smce & M8260_SMCE_TX) { + m8260.smc1.smce = M8260_SMCE_TX; /* Clear the event */ + + /* Check that the buffer is ours */ + if ((TxBd[SMC1_MINOR]->status & M8260_BD_READY) == 0) + rtems_termios_dequeue_characters ( + (void *)ttyp[SMC1_MINOR], + (int)TxBd[SMC1_MINOR]->length); + } + +#if 0 + m8260.sipnr_l = 0x00001000; /* Clear SMC1 interrupt-in-service bit */ +#endif +} + + +static void +m8xx_smc2_interrupt_handler (rtems_vector_number v) +{ + int nb_overflow; + + /* + * Buffer received? + */ + if (m8260.smc2.smce & M8260_SMCE_RX) { + m8260.smc2.smce = M8260_SMCE_RX; /* Clear the event */ + + + /* Check that the buffer is ours */ + if ((RxBd[SMC2_MINOR]->status & M8260_BD_EMPTY) == 0) { + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[SMC2_MINOR]->buffer, + RxBd[SMC2_MINOR]->length ); + nb_overflow = rtems_termios_enqueue_raw_characters( + (void *)ttyp[SMC2_MINOR], + (char *)RxBd[SMC2_MINOR]->buffer, + (int)RxBd[SMC2_MINOR]->length ); + RxBd[SMC2_MINOR]->status = M8260_BD_EMPTY | M8260_BD_WRAP | + M8260_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ + if (m8260.smc2.smce & M8260_SMCE_TX) { + m8260.smc2.smce = M8260_SMCE_TX; /* Clear the event */ + + /* Check that the buffer is ours */ + if ((TxBd[SMC2_MINOR]->status & M8260_BD_READY) == 0) + rtems_termios_dequeue_characters ( + (void *)ttyp[SMC2_MINOR], + (int)TxBd[SMC2_MINOR]->length); + } + +#if 0 + m8260.sipnr_l = 0x00000800; /* Clear SMC2 interrupt-in-service bit */ +#endif +} + + +void m8xx_scc_enable(const rtems_irq_connect_data* ptr) +{ + volatile m8260SCCRegisters_t *sccregs = 0; + switch (ptr->name) { + case BSP_CPM_IRQ_SCC4 : + m8260.sipnr_l |= M8260_SIMASK_SCC4; + sccregs = &m8260.scc4; + break; + case BSP_CPM_IRQ_SCC3 : + m8260.sipnr_l |= M8260_SIMASK_SCC3; + sccregs = &m8260.scc3; + break; + case BSP_CPM_IRQ_SCC2 : + m8260.sipnr_l |= M8260_SIMASK_SCC2; + sccregs = &m8260.scc2; + break; + case BSP_CPM_IRQ_SCC1 : + m8260.sipnr_l |= M8260_SIMASK_SCC1; + sccregs = &m8260.scc1; + break; + default: + break; + } + sccregs->sccm = 3; +} + +void m8xx_scc_disable(const rtems_irq_connect_data* ptr) +{ + volatile m8260SCCRegisters_t *sccregs = 0; + switch (ptr->name) { + case BSP_CPM_IRQ_SCC4 : + sccregs = &m8260.scc4; + break; + case BSP_CPM_IRQ_SCC3 : + sccregs = &m8260.scc3; + break; + case BSP_CPM_IRQ_SCC2 : + sccregs = &m8260.scc2; + break; + case BSP_CPM_IRQ_SCC1 : + sccregs = &m8260.scc1; + break; + default: + break; + } + sccregs->sccm &= (~3); +} + +int m8xx_scc_isOn(const rtems_irq_connect_data* ptr) +{ + return BSP_irq_enabled_at_cpm (ptr->name); +} + +static rtems_irq_connect_data consoleIrqData = +{ + BSP_CPM_IRQ_SCC1, + (rtems_irq_hdl)m8xx_scc1_interrupt_handler, + (rtems_irq_enable) m8xx_scc_enable, + (rtems_irq_disable) m8xx_scc_disable, + (rtems_irq_is_enabled) m8xx_scc_isOn +}; + + +void +m8xx_uart_scc_initialize (int minor) +{ + unsigned char brg; + volatile m8260SCCparms_t *sccparms = 0; + volatile m8260SCCRegisters_t *sccregs = 0; + + /* + * Check that minor number is valid + */ + if ( (minor < SCC1_MINOR) || (minor > NUM_PORTS-1) ) + return; + + /* Get the sicr clock source bit values for 9600 bps */ + brg = m8xx_get_brg(M8260_SCC_BRGS, 9600*16); + + m8260.cmxscr &= ~(0xFF000000 >> (8*(minor-SCC1_MINOR)) ); + m8260.cmxscr |= (brg<<(3+8*(3-(minor-SCC1_MINOR)))); + m8260.cmxscr |= (brg<<(8*(3-(minor-SCC1_MINOR)))); + + /* + * Allocate buffer descriptors + */ + RxBd[minor] = m8xx_bd_allocate(1); + TxBd[minor] = m8xx_bd_allocate(1); + + /* + * Configure ports to enable TXDx and RXDx pins + */ + + m8260.ppard |= (0x07 << ((minor-SCC1_MINOR)*3)); + m8260.psord &= ~(0x07 << ((minor-SCC1_MINOR)*3)); + if( minor == SCC1_MINOR ) + m8260.psord |= 0x02; + m8260.pdird |= (0x06 << ((minor-SCC1_MINOR)*3)); + m8260.pdird &= ~(0x01 << ((minor-SCC1_MINOR)*3)); + + + /* + * Set up SMC1 parameter RAM common to all protocols + */ + if( minor == SCC1_MINOR ) { + sccparms = (m8260SCCparms_t*)&m8260.scc1p; + sccregs = (m8260SCCRegisters_t*)&m8260.scc1; + } + else if( minor == SCC2_MINOR ) { + sccparms = (m8260SCCparms_t*)&m8260.scc2p; + sccregs = (m8260SCCRegisters_t*)&m8260.scc2; + } + else if( minor == SCC3_MINOR ) { + sccparms = (m8260SCCparms_t*)&m8260.scc3p; + sccregs = (m8260SCCRegisters_t*)&m8260.scc3; + } + else { + sccparms = (m8260SCCparms_t*)&m8260.scc4p; + sccregs = (m8260SCCRegisters_t*)&m8260.scc4; + } + + sccparms->rbase = (char *)RxBd[minor] - (char *)&m8260; + sccparms->tbase = (char *)TxBd[minor] - (char *)&m8260; + + + + + sccparms->rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS; + sccparms->tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS; + if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) + sccparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ + else + sccparms->mrblr = 1; /* Maximum Rx buffer size */ + sccparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */ + sccparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */ + + sccparms->un.uart.parec = 0; /* Clear parity error counter */ + sccparms->un.uart.frmec = 0; /* Clear framing error counter */ + sccparms->un.uart.nosec = 0; /* Clear noise counter */ + sccparms->un.uart.brkec = 0; /* Clear break counter */ + + sccparms->un.uart.uaddr[0] = 0; /* Not in multidrop mode, so clear */ + sccparms->un.uart.uaddr[1] = 0; /* Not in multidrop mode, so clear */ + sccparms->un.uart.toseq = 0; /* Tx Out-Of-SEQuence--no XON/XOFF now */ + + sccparms->un.uart.character[0] = 0x8000; /* Entry is invalid */ + sccparms->un.uart.character[1] = 0x8000; /* Entry is invalid */ + sccparms->un.uart.character[2] = 0x8000; /* Entry is invalid */ + sccparms->un.uart.character[3] = 0x8000; /* Entry is invalid */ + sccparms->un.uart.character[4] = 0x8000; /* Entry is invalid */ + sccparms->un.uart.character[5] = 0x8000; /* Entry is invalid */ + sccparms->un.uart.character[6] = 0x8000; /* Entry is invalid */ + sccparms->un.uart.character[7] = 0x8000; /* Entry is invalid */ + + + sccparms->un.uart.rccm = 0xc0ff; /* No masking */ + + /* + * Set up the Receive Buffer Descriptor + */ + RxBd[minor]->status = M8260_BD_EMPTY | M8260_BD_WRAP | M8260_BD_INTERRUPT; + RxBd[minor]->length = 0; + RxBd[minor]->buffer = rxBuf[minor]; + + /* + * Setup the Transmit Buffer Descriptor + */ + TxBd[minor]->status = M8260_BD_WRAP; + + /* + * Set up SCCx general and protocol-specific mode registers + */ + sccregs->gsmr_h = 0x00000020; /* RFW=low latency operation */ + sccregs->gsmr_l = 0x00028004; /* TDCR=RDCR=16x clock mode, MODE=uart*/ + sccregs->scce = ~0; /* Clear any pending event */ + sccregs->sccm = 0; /* Mask all interrupt/event sources */ + sccregs->psmr = 0x3000; /* Normal operation & mode, 1 stop bit, + 8 data bits, no parity */ + sccregs->dsr = 0x7E7E; /* No fractional stop bits */ + sccregs->gsmr_l = 0x00028034; /* ENT=enable Tx, ENR=enable Rx */ + + /* + * Initialize the Rx and Tx with the new parameters. + */ + switch (minor) { + case SCC1_MINOR: + m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC1); + break; + case SCC2_MINOR: + m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC2); + break; + case SCC3_MINOR: + m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC3); + break; + case SCC4_MINOR: + m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SCC4); + break; + } + + if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) { + switch (minor) { + case SCC1_MINOR: + consoleIrqData.name = BSP_CPM_IRQ_SCC1; + consoleIrqData.hdl = m8xx_scc1_interrupt_handler; + break; + case SCC2_MINOR: + consoleIrqData.name = BSP_CPM_IRQ_SCC2; + consoleIrqData.hdl = m8xx_scc2_interrupt_handler; + break; + case SCC3_MINOR: + consoleIrqData.name = BSP_CPM_IRQ_SCC3; + consoleIrqData.hdl = m8xx_scc3_interrupt_handler; + break; + case SCC4_MINOR: + consoleIrqData.name = BSP_CPM_IRQ_SCC4; + consoleIrqData.hdl = m8xx_scc4_interrupt_handler; + break; + + } + if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { + printk("Unable to connect SCC Irq handler\n"); + rtems_fatal_error_occurred(1); + } + } +} + + + +void m8xx_smc_enable(const rtems_irq_connect_data* ptr) +{ + volatile m8260SMCRegisters_t *smcregs = 0; + switch (ptr->name) { + case BSP_CPM_IRQ_SMC1 : + smcregs = &m8260.smc1; + break; + case BSP_CPM_IRQ_SMC2 : + smcregs = &m8260.smc2; + break; + default: + break; + } + smcregs->smcm = 3; +} + +void m8xx_smc_disable(const rtems_irq_connect_data* ptr) +{ + volatile m8260SMCRegisters_t *smcregs = 0; + switch (ptr->name) { + case BSP_CPM_IRQ_SMC1 : + smcregs = &m8260.smc1; + break; + case BSP_CPM_IRQ_SMC2 : + smcregs = &m8260.smc2; + break; + default: + break; + } + smcregs->smcm &= (~3); +} + +int m8xx_smc_isOn(const rtems_irq_connect_data* ptr) +{ + return BSP_irq_enabled_at_cpm (ptr->name); +} + + +void +m8xx_uart_smc_initialize (int minor) +{ + unsigned char brg; + volatile m8260SMCparms_t *smcparms = 0; + volatile m8260SMCRegisters_t *smcregs = 0; + + /* + * Check that minor number is valid + */ + if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) + return; + + /* Get the simode clock source bit values for 9600 bps */ + if( minor == SMC1_MINOR ) + brg = m8xx_get_brg(M8260_SMC1_BRGS, 9600*16); + else + brg = m8xx_get_brg(M8260_SMC2_BRGS, 9600*16); + + /* + * Allocate buffer descriptors + */ + RxBd[minor] = m8xx_bd_allocate (1); + TxBd[minor] = m8xx_bd_allocate (1); + + /* + * Get the address of the parameter RAM for the specified port, + * configure I/O port B and put SMC in NMSI mode, connect the + * SMC to the appropriate BRG. + * + * SMC2 RxD is shared with port B bit 20 + * SMC2 TxD is shared with port B bit 21 + * SMC1 RxD is shared with port B bit 24 + * SMC1 TxD is shared with port B bit 25 + */ + switch (minor) { + case SMC1_MINOR: + smcparms = &m8260.smc1p; + smcregs = &m8260.smc1; + +#if 0 + m8260.pbpar |= 0x000000C0; /* PB24 & PB25 are dedicated peripheral pins */ + m8260.pbdir &= ~0x000000C0; /* PB24 & PB25 must not drive UART lines */ + m8260.pbodr &= ~0x000000C0; /* PB24 & PB25 are not open drain */ + + m8260.simode &= 0xFFFF0FFF; /* Clear SMC1CS & SMC1 for NMSI mode */ + m8260.simode |= brg << 12; /* SMC1CS = brg */ +#endif + break; + + case SMC2_MINOR: + smcparms = &m8260.smc2p; + smcregs = &m8260.smc2; +#if 0 + m8260.pbpar |= 0x00000C00; /* PB20 & PB21 are dedicated peripheral pins */ + m8260.pbdir &= ~0x00000C00; /* PB20 & PB21 must not drive the UART lines */ + m8260.pbodr &= ~0x00000C00; /* PB20 & PB21 are not open drain */ + + m8260.simode &= 0x0FFFFFFF; /* Clear SMC2CS & SMC2 for NMSI mode */ + m8260.simode |= brg << 28; /* SMC2CS = brg */ +#endif + break; + } + + /* + * Set up SMC parameter RAM common to all protocols + */ + smcparms->rbase = (char *)RxBd[minor] - (char *)&m8260; + smcparms->tbase = (char *)TxBd[minor] - (char *)&m8260; + smcparms->rfcr = M8260_RFCR_MOT | M8260_RFCR_60X_BUS; + smcparms->tfcr = M8260_TFCR_MOT | M8260_TFCR_60X_BUS; + if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) + smcparms->mrblr = RXBUFSIZE; /* Maximum Rx buffer size */ + else + smcparms->mrblr = 1; /* Maximum Rx buffer size */ + + /* + * Set up SMC1 parameter RAM UART-specific parameters + */ + smcparms->un.uart.max_idl = 10; /* Set nb of idle chars to close buffer */ + smcparms->un.uart.brkcr = 0; /* Set nb of breaks to send for STOP Tx */ + smcparms->un.uart.brkec = 0; /* Clear break counter */ + + /* + * Set up the Receive Buffer Descriptor + */ + RxBd[minor]->status = M8260_BD_EMPTY | M8260_BD_WRAP | M8260_BD_INTERRUPT; + RxBd[minor]->length = 0; + RxBd[minor]->buffer = rxBuf[minor]; + + /* + * Setup the Transmit Buffer Descriptor + */ + TxBd[minor]->status = M8260_BD_WRAP; + + /* + * Set up SMCx general and protocol-specific mode registers + */ + smcregs->smce = ~0; /* Clear any pending events */ + smcregs->smcm = 0; /* Enable SMC Rx & Tx interrupts */ + smcregs->smcmr = M8260_SMCMR_CLEN(9) | M8260_SMCMR_SM_UART; + + /* + * Send "Init parameters" command + */ + switch (minor) { + case SMC1_MINOR: + m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SMC1); + break; + + case SMC2_MINOR: + m8xx_cp_execute_cmd (M8260_CR_OP_INIT_RX_TX | M8260_CR_SMC2); + break; + } + + /* + * Enable receiver and transmitter + */ + smcregs->smcmr |= M8260_SMCMR_TEN | M8260_SMCMR_REN; + if ( (mbx8xx_console_get_configuration() & 0x06) == 0x02 ) { + consoleIrqData.on = m8xx_smc_enable; + consoleIrqData.off = m8xx_smc_disable; + consoleIrqData.isOn = m8xx_smc_isOn; + switch (minor) { + case SMC1_MINOR: + consoleIrqData.name = BSP_CPM_IRQ_SMC1; + consoleIrqData.hdl = m8xx_smc1_interrupt_handler; + break; + + case SMC2_MINOR: + consoleIrqData.name = BSP_CPM_IRQ_SMC2; + consoleIrqData.hdl = m8xx_smc2_interrupt_handler; + break; +#if 0 + case SMC1_MINOR: + rtems_interrupt_catch (m8xx_smc1_interrupt_handler, + PPC_IRQ_CPM_SMC1, + &old_handler[minor]); + + smcregs->smcm = 3; /* Enable SMC1 Rx & Tx interrupts */ + m8260.sipnr_l |= M8260_SIMASK_SMC1; /* Clear pending register */ + m8260.simr_l |= M8260_SIMASK_SMC1; /* Enable SMC1 interrupts */ + break; + + case SMC2_MINOR: + rtems_interrupt_catch (m8xx_smc2_interrupt_handler, + PPC_IRQ_CPM_SMC2, + &old_handler[minor]); + + smcregs->smcm = 3; /* Enable SMC2 Rx & Tx interrupts */ + m8260.sipnr_l |= M8260_SIMASK_SMC2; /* Clear pending register */ + m8260.simr_l |= M8260_SIMASK_SMC2; /* Enable SMC2 interrupts */ + break; +#endif + } + if (!BSP_install_rtems_irq_handler (&consoleIrqData)) { + printk("Unable to connect SMC Irq handler\n"); + rtems_fatal_error_occurred(1); + } + } +} + +void +m8xx_uart_initialize(void) +{ + +} + + +void +m8xx_uart_interrupts_initialize(void) +{ +#ifdef mpc8260 + /* CHECK THIS */ + +#else + +#if defined(mpc860) + m8xx.cicr = 0x00E43F80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, + SCdP=SCC4, IRL=1, HP=PC15, IEN=1 */ +#else + m8xx.cicr = 0x00043F80; /* SCaP=SCC1, SCbP=SCC2, IRL=1, HP=PC15, IEN=1 */ +#endif + m8xx.simask |= M8xx_SIMASK_LVM1; /* Enable level interrupts */ + +#endif +} + + +int +m8xx_uart_pollRead( + int minor +) +{ + unsigned char c; + + if (RxBd[minor]->status & M8260_BD_EMPTY) { + return -1; + } + rtems_cache_invalidate_multiple_data_lines( + (const void *) RxBd[minor]->buffer, + RxBd[minor]->length + ); + c = ((char *)RxBd[minor]->buffer)[0]; + RxBd[minor]->status = M8260_BD_EMPTY | M8260_BD_WRAP; + return c; +} + + +/* + * TODO: Get a free buffer and set it up. + */ +int +m8xx_uart_write( + int minor, + const char *buf, + int len +) +{ + while( (TxBd[minor]->status) & M8260_BD_READY ); + + rtems_cache_flush_multiple_data_lines( buf, len ); + TxBd[minor]->buffer = (char *) buf; + TxBd[minor]->length = len; + TxBd[minor]->status = M8260_BD_READY | M8260_BD_WRAP | M8260_BD_INTERRUPT; + return 0; +} + + +int +m8xx_uart_pollWrite( + int minor, + const char *buf, + int len +) +{ + + while (len--) { + while (TxBd[minor]->status & M8260_BD_READY) + continue; + txBuf[minor] = *buf++; + rtems_cache_flush_multiple_data_lines( (void *)&txBuf[minor], 1 ); + TxBd[minor]->buffer = &txBuf[minor]; + TxBd[minor]->length = 1; + TxBd[minor]->status = M8260_BD_READY | M8260_BD_WRAP; + } + + return 0; +} + +void +m8xx_uart_reserve_resources( + rtems_configuration_table *configuration +) +{ + rtems_termios_reserve_resources (configuration, NUM_PORTS); +} diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/.cvsignore b/c/src/lib/libcpu/powerpc/mpc8260/cpm/.cvsignore new file mode 100644 index 0000000000..282522db03 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/.cvsignore @@ -0,0 +1,2 @@ +Makefile +Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/Makefile.am b/c/src/lib/libcpu/powerpc/mpc8260/cpm/Makefile.am new file mode 100644 index 0000000000..55cd146dff --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/Makefile.am @@ -0,0 +1,29 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +PGM = ${ARCH}/cp.rel + +## C sources +C_FILES = cp.c dpram.c brg.c + +cpm_rel_OBJECTS = $(C_FILES:%.c=${ARCH}/%.o) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(top_srcdir)/../../../../../automake/compile.am +include $(top_srcdir)/../../../../../automake/lib.am + +# +# (OPTIONAL) Add local stuff here using += +# + +$(PGM): $(cpm_rel_OBJECTS) + $(make-rel) + +all-local: ${ARCH} $(PGM) + +EXTRA_DIST = $(C_FILES) + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/brg.c b/c/src/lib/libcpu/powerpc/mpc8260/cpm/brg.c new file mode 100644 index 0000000000..c6e48be0b0 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/brg.c @@ -0,0 +1,204 @@ +/* + * Baud rate generator management functions. + * + * This file contains routines for allocating baud rate generators + * and clock sources to the SCCs and FCCs on the MPC8260. The + * allocation is a little more complex on this processor because + * there are restrictions on which brgs and clks can be assigned to + * a particular port. Rather than coming up with a fixed assignment + * these routines try to allocate resources sensibly. + * + * *** All attempts to allocate a BRG or CLK line should be made via + * calls to these routines or they simply won't work. + * + * Author: Andy Dachs + * Copyright Surrey Satellite Technology Limited (SSTL), 2001 + * + * Derived in part from work by: + * + * Author: Jay Monkman (jmonkman@frasca.com) + * Copyright (C) 1998 by Frasca International, Inc. + * and + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include +#include +#include + +#define NUM_BRGS 8 +#define NUM_CLKS 20 + +/* Used to track the usage of the baud rate generators */ +/* (initialised to zeros) */ +static unsigned long brg_spd[NUM_BRGS]; +static unsigned int brg_use_count[NUM_BRGS]; + + +/* Used to track the usage of the clock inputs */ +/* (initialised to zeros) */ +static unsigned int clk_use_count[NUM_BRGS]; + + +extern rtems_cpu_table Cpu_table; + +/* + * Compute baud-rate-generator configuration register value + */ +int +m8xx_get_brg_cd (int baud) +{ + int divisor; + int div16 = 0; + + divisor = ((Cpu_table.serial_per_sec) + (baud / 2)) / baud; + if (divisor > 4096) { + div16 = 1; + divisor = (divisor + 8) / 16; + } + return M8260_BRG_EN | M8260_BRG_EXTC_BRGCLK | + ((divisor - 1) << 1) | div16; +} + + +/* + * Allocates an existing brg if one is already programmed for the same + * baud rate. Otherwise a new brg is assigned + * AFD: on the mpc8260 only some combinations of SCC/SMC and BRG are allowed + * so add a mask which specifies which of the BRGs we can choose from + */ +int +m8xx_get_brg(unsigned brgmask, int baud) +{ + int i; + + /* first try to find a BRG that is already at the right speed */ + for ( i = 0; i < NUM_BRGS; i++ ) { + if( (1 << i) & brgmask ) /* is this brg allowed? */ + if ( brg_spd[i] == baud ) { + break; + } + } + + if ( i == NUM_BRGS ) { /* I guess we didn't find one */ + for ( i = 0; i < NUM_BRGS; i++ ) { + if (((1<=0) && (brg_num 0 ) + brg_use_count[brg_num]--; +} + + +void m8xx_dump_brgs( void ) +{ + int i; + for(i=0; i=0) && (clk_num 0 ) + clk_use_count[clk_num]--; +} diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c b/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c new file mode 100644 index 0000000000..cfcae7b325 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/cp.c @@ -0,0 +1,35 @@ +/* + * cp.c + * + * MPC8xx CPM RISC Communication Processor routines. + * + * Based on code (alloc860.c in eth_comm port) by + * Jay Monkman (jmonkman@frasca.com), + * which, in turn, is based on code by + * W. Eric Norum (eric@skatter.usask.ca). + * + * Modifications by Darlene Stewart (Darlene.Stewart@iit.nrc.ca): + * Copyright (c) 1999, National Research Council of Canada + */ + +#include +#include +#include + +/* + * Send a command to the CPM RISC processer + */ + +void m8xx_cp_execute_cmd( unsigned32 command ) +{ + rtems_unsigned16 lvl; + + rtems_interrupt_disable(lvl); + while (m8260.cpcr & M8260_CR_FLG) { + continue; + } + + m8260.cpcr = command | M8260_CR_FLG; + rtems_interrupt_enable (lvl); +} + diff --git a/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c b/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c new file mode 100644 index 0000000000..7fb8f512a6 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/cpm/dpram.c @@ -0,0 +1,91 @@ +/* + * dpram.c + * + * MPC8260 dual-port RAM allocation routines + * + * Based on code in mpc8xx which is + * Based on code (alloc860.c in eth_comm port) by + * Jay Monkman (jmonkman@frasca.com), + * which, in turn, is based on code by + * W. Eric Norum (eric@skatter.usask.ca). + * + * + * Modifications : + * Copyright (c) 1999, National Research Council of Canada + * + * MPC8260 modifications Andy Dachs, + * Surrey Satellite Technology Limited, 2001 + */ + +#include +#include +#include + +/* + * Allocation order: + * - Dual-Port RAM section 0 + * - Dual-Port RAM section 1 + * - Dual-Port RAM section 2 + * - Dual-Port RAM section 3 + */ +static struct { + unsigned8 *base; + unsigned int size; + unsigned int used; +} dpram_regions[] = { +/* { (char *)&m8260.dpram0[0], sizeof m8260.dpram0, 0 },*/ + { (char *)&m8260.dpram1[0], sizeof m8260.dpram1, 0 }, +/* { (char *)&m8260.dpram2[0], sizeof m8260.dpram2, 0 },*/ + { (char *)&m8260.dpram3[0], sizeof m8260.dpram3, 0 } +}; + +#define NUM_DPRAM_REGIONS (sizeof(dpram_regions) / sizeof(dpram_regions[0])) + +void * +m8xx_dpram_allocate( unsigned int byte_count ) +{ + unsigned int i; + ISR_Level level; + void *blockp = NULL; + + byte_count = (byte_count + 3) & ~0x3; + + /* + * Running with interrupts disabled is usually considered bad + * form, but this routine is probably being run as part of an + * initialization sequence so the effect shouldn't be too severe. + */ + _ISR_Disable (level); + + for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) { + /* + * Verify that the region is available for use. + * This test is necessary because if extra microcode modules + * are installed, some regions are locked and unavailable. + * See MPC860 User's Manual Pages 19-9 to 19-11. + */ + if (dpram_regions[i].used == 0) { + volatile unsigned char *cp = dpram_regions[i].base; + *cp = 0xAA; + if (*cp != 0xAA) + dpram_regions[i].used = dpram_regions[i].size; + else { + *cp = 0x55; + if (*cp != 0x55) + dpram_regions[i].used = dpram_regions[i].size; + } + *cp = 0x0; + } + if (dpram_regions[i].size - dpram_regions[i].used >= byte_count) { + blockp = dpram_regions[i].base + dpram_regions[i].used; + dpram_regions[i].used += byte_count; + break; + } + } + + _ISR_Enable(level); + + if (blockp == NULL) + rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count); + return blockp; +} diff --git a/c/src/lib/libcpu/powerpc/mpc8260/exceptions/.cvsignore b/c/src/lib/libcpu/powerpc/mpc8260/exceptions/.cvsignore new file mode 100644 index 0000000000..282522db03 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/exceptions/.cvsignore @@ -0,0 +1,2 @@ +Makefile +Makefile.in diff --git a/c/src/lib/libcpu/powerpc/mpc8260/exceptions/Makefile.am b/c/src/lib/libcpu/powerpc/mpc8260/exceptions/Makefile.am new file mode 100644 index 0000000000..d79699810d --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/exceptions/Makefile.am @@ -0,0 +1,43 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +PGM = $(ARCH)/exceptions.rel + +C_FILES = raw_exception.c + +S_FILES = asm_utils.S + +H_FILES = raw_exception.h + +exceptions_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) \ + $(S_FILES:%.S=$(ARCH)/%.o) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(top_srcdir)/../../../../../automake/compile.am +include $(top_srcdir)/../../../../../automake/lib.am + +$(PROJECT_INCLUDE)/libcpu: + $(mkinstalldirs) $@ +$(PROJECT_INCLUDE)/libcpu/%.h: %.h + $(INSTALL_DATA) $< $@ + +# +# (OPTIONAL) Add local stuff here using += +# + +$(PGM): $(exceptions_rel_OBJECTS) + $(make-rel) + +PREINSTALL_FILES += $(PROJECT_INCLUDE)/libcpu \ + $(PROJECT_INCLUDE)/libcpu/raw_exception.h + +all-local: $(ARCH) $(PREINSTALL_FILES) $(exceptions_rel_OBJECTS) $(PGM) + +.PRECIOUS: $(PGM) + +EXTRA_DIST = asm_utils.S raw_exception.c raw_exception.h + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc8260/exceptions/asm_utils.S b/c/src/lib/libcpu/powerpc/mpc8260/exceptions/asm_utils.S new file mode 100644 index 0000000000..f046915404 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/exceptions/asm_utils.S @@ -0,0 +1,65 @@ +/* + * asm_utils.s + * + * $Id$ + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * + * This file contains the low-level support for moving exception + * exception code to appropriate location. + * + */ + +#include +#include +#include +#include "asm.h" + + .globl codemove +codemove: + .type codemove,@function +/* r3 dest, r4 src, r5 length in bytes, r6 cachelinesize */ + cmplw cr1,r3,r4 + addi r0,r5,3 + srwi. r0,r0,2 + beq cr1,4f /* In place copy is not necessary */ + beq 7f /* Protect against 0 count */ + mtctr r0 + bge cr1,2f + + la r8,-4(r4) + la r7,-4(r3) +1: lwzu r0,4(r8) + stwu r0,4(r7) + bdnz 1b + b 4f + +2: slwi r0,r0,2 + add r8,r4,r0 + add r7,r3,r0 +3: lwzu r0,-4(r8) + stwu r0,-4(r7) + bdnz 3b + +/* Now flush the cache: note that we must start from a cache aligned + * address. Otherwise we might miss one cache line. + */ +4: cmpwi r6,0 + add r5,r3,r5 + beq 7f /* Always flush prefetch queue in any case */ + subi r0,r6,1 + andc r3,r3,r0 + mr r4,r3 +5: cmplw r4,r5 + dcbst 0,r4 + add r4,r4,r6 + blt 5b + sync /* Wait for all dcbst to complete on bus */ + mr r4,r3 +6: cmplw r4,r5 + icbi 0,r4 + add r4,r4,r6 + blt 6b +7: sync /* Wait for all icbi to complete on bus */ + isync + blr diff --git a/c/src/lib/libcpu/powerpc/mpc8260/exceptions/raw_exception.c b/c/src/lib/libcpu/powerpc/mpc8260/exceptions/raw_exception.c new file mode 100644 index 0000000000..403c19eb43 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/exceptions/raw_exception.c @@ -0,0 +1,205 @@ +/* + * raw_exception.c - This file contains implementation of C function to + * Instanciate 8xx ppc primary exception entries. + * More detailled information can be found on motorola + * site and more precisely in the following book : + * + * MPC860 + * Risc Microporcessor User's Manual + * Motorola REF : MPC860UM/AD + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * Modified for mpc8260 by Andy Dachs + * Surrey Satellite Technology Limited (SSTL), 2001 + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ +#include +#include +#include +#include +#include +#include + +static rtems_raw_except_connect_data* raw_except_table; +static rtems_raw_except_connect_data default_raw_except_entry; +static rtems_raw_except_global_settings* local_settings; + +int mpc8260_vector_is_valid(rtems_vector vector) +{ + switch(vector) { + case ASM_RESET_VECTOR: /* fall through */ + case ASM_MACH_VECTOR: + case ASM_PROT_VECTOR: + case ASM_ISI_VECTOR: + case ASM_EXT_VECTOR: + case ASM_ALIGN_VECTOR: + case ASM_PROG_VECTOR: + case ASM_FLOAT_VECTOR: + case ASM_DEC_VECTOR: + + case ASM_SYS_VECTOR: + case ASM_TRACE_VECTOR: + case ASM_FLOATASSIST_VECTOR: + + case ASM_ITLBMISS_VECTOR: + case ASM_DTLBLMISS_VECTOR: + case ASM_DTLBSMISS_VECTOR: + + case ASM_IBREAK_VECTOR: + case ASM_SYSMANAGE_VECTOR: + return 1; + default: return 0; + } +} + +int mpc8xx_vector_is_valid(rtems_vector vector) +{ + switch (current_ppc_cpu) { + case PPC_8260: + if (!mpc8260_vector_is_valid(vector)) { + return 0; + } + break; + default: + printk("Please complete libcpu/powerpc/mpc8xx/exceptions/raw_exception.c\n"); + printk("current_ppc_cpu = %x\n", current_ppc_cpu); + return 0; + } + return 1; +} + +int mpc8xx_set_exception (const rtems_raw_except_connect_data* except) +{ + unsigned int level; + + if (!mpc8xx_vector_is_valid(except->exceptIndex)) { + return 0; + } + /* + * Check if default handler is actually connected. If not issue an error. + * You must first get the current handler via mpc8xx_get_current_exception + * and then disconnect it using mpc8xx_delete_exception. + * RATIONALE : to always have the same transition by forcing the user + * to get the previous handler before accepting to disconnect. + */ + if (memcmp(mpc8xx_get_vector_addr(except->exceptIndex), (void*)default_raw_except_entry.hdl.raw_hdl,default_raw_except_entry.hdl.raw_hdl_size)) { + return 0; + } + + _CPU_ISR_Disable(level); + + raw_except_table [except->exceptIndex] = *except; +/* + memmove((void*)mpc8xx_get_vector_addr(except->exceptIndex), + except->hdl.raw_hdl, + except->hdl.raw_hdl_size + ); +*/ + codemove((void*)mpc8xx_get_vector_addr(except->exceptIndex), + except->hdl.raw_hdl, + except->hdl.raw_hdl_size, + PPC_CACHE_ALIGNMENT); + + except->on(except); + + _CPU_ISR_Enable(level); + return 1; +} + +int mpc8xx_get_current_exception (rtems_raw_except_connect_data* except) +{ + if (!mpc8xx_vector_is_valid(except->exceptIndex)){ + return 0; + } + + *except = raw_except_table [except->exceptIndex]; + + return 1; +} + +int mpc8xx_delete_exception (const rtems_raw_except_connect_data* except) +{ + unsigned int level; + + if (!mpc8xx_vector_is_valid(except->exceptIndex)){ + return 0; + } + /* + * Check if handler passed is actually connected. If not issue an error. + * You must first get the current handler via mpc8xx_get_current_exception + * and then disconnect it using mpc8xx_delete_exception. + * RATIONALE : to always have the same transition by forcing the user + * to get the previous handler before accepting to disconnect. + */ + if (memcmp(mpc8xx_get_vector_addr(except->exceptIndex), + (void*)except->hdl.raw_hdl, + except->hdl.raw_hdl_size)) { + return 0; + } + _CPU_ISR_Disable(level); + + except->off(except); + codemove((void*)mpc8xx_get_vector_addr(except->exceptIndex), + default_raw_except_entry.hdl.raw_hdl, + default_raw_except_entry.hdl.raw_hdl_size, + PPC_CACHE_ALIGNMENT); + + + raw_except_table[except->exceptIndex] = default_raw_except_entry; + raw_except_table[except->exceptIndex].exceptIndex = except->exceptIndex; + + _CPU_ISR_Enable(level); + + return 1; +} + +/* + * Exception global init. + */ +int mpc8xx_init_exceptions (rtems_raw_except_global_settings* config) +{ + unsigned i; + unsigned int level; + + /* + * store various accelerators + */ + raw_except_table = config->rawExceptHdlTbl; + local_settings = config; + default_raw_except_entry = config->defaultRawEntry; + + _CPU_ISR_Disable(level); + + for (i=0; i <= LAST_VALID_EXC; i++) { + if (!mpc8xx_vector_is_valid(i)){ + continue; + } + codemove((void*)mpc8xx_get_vector_addr(i), + raw_except_table[i].hdl.raw_hdl, + raw_except_table[i].hdl.raw_hdl_size, + PPC_CACHE_ALIGNMENT); + if (raw_except_table[i].hdl.raw_hdl != default_raw_except_entry.hdl.raw_hdl) { + raw_except_table[i].on(&raw_except_table[i]); + } + else { + raw_except_table[i].off(&raw_except_table[i]); + } + } + _CPU_ISR_Enable(level); + + return 1; +} + +int mpc8xx_get_exception_config (rtems_raw_except_global_settings** config) +{ + *config = local_settings; + return 1; +} + diff --git a/c/src/lib/libcpu/powerpc/mpc8260/exceptions/raw_exception.h b/c/src/lib/libcpu/powerpc/mpc8260/exceptions/raw_exception.h new file mode 100644 index 0000000000..9679465e5d --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/exceptions/raw_exception.h @@ -0,0 +1,183 @@ +/* + * raw_execption.h + * + * This file contains implementation of C function to + * Instanciate 8xx ppc primary exception entries. + * More detailled information can be found on motorola + * site and more precisely in the following book : + * + * MPC860 + * Risc Microporcessor User's Manual + * Motorola REF : MPC860UM/AD 07/98 Rev .1 + * + * Copyright (C) 1999 Eric Valette (valette@crf.canon.fr) + * Canon Centre Recherche France. + * + * Modified Andy Dachs + * Surrey Satellite Technology Limited (SSTL), 2001 + * for MPC8260 + * + * The license and distribution terms for this file may be + * found in found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef _LIBCPU_MPC8XX_EXCEPTION_RAW_EXCEPTION_H +#define _LIBCPU_MPC8XX_EXCEPTION_RAW_EXCEPTION_H + +/* + * Exception Vectors as defined in the MCP750 manual + */ + +#define ASM_RESET_VECTOR 0x01 +#define ASM_MACH_VECTOR 0x02 +#define ASM_PROT_VECTOR 0x03 +#define ASM_ISI_VECTOR 0x04 +#define ASM_EXT_VECTOR 0x05 +#define ASM_ALIGN_VECTOR 0x06 +#define ASM_PROG_VECTOR 0x07 +#define ASM_FLOAT_VECTOR 0x08 +#define ASM_DEC_VECTOR 0x09 + +#define ASM_SYS_VECTOR 0x0C +#define ASM_TRACE_VECTOR 0x0D +#define ASM_FLOATASSIST_VECTOR 0x0E + +#define ASM_ITLBMISS_VECTOR 0x10 +#define ASM_DTLBLMISS_VECTOR 0x11 +#define ASM_DTLBSMISS_VECTOR 0x12 +#define ASM_IBREAK_VECTOR 0x13 +#define ASM_SYSMANAGE_VECTOR 0x14 + +#define LAST_VALID_EXC ASM_SYSMANAGE_VECTOR + +/* + * Vector offsets as defined in the MPC8260 manual + */ + +#define ASM_RESET_VECTOR_OFFSET (ASM_RESET_VECTOR << 8) +#define ASM_MACH_VECTOR_OFFSET (ASM_MACH_VECTOR << 8) +#define ASM_PROT_VECTOR_OFFSET (ASM_PROT_VECTOR << 8) +#define ASM_ISI_VECTOR_OFFSET (ASM_ISI_VECTOR << 8) +#define ASM_EXT_VECTOR_OFFSET (ASM_EXT_VECTOR << 8) +#define ASM_ALIGN_VECTOR_OFFSET (ASM_ALIGN_VECTOR << 8) +#define ASM_PROG_VECTOR_OFFSET (ASM_PROG_VECTOR << 8) +#define ASM_FLOAT_VECTOR_OFFSET (ASM_FLOAT_VECTOR << 8) +#define ASM_DEC_VECTOR_OFFSET (ASM_DEC_VECTOR << 8) + +#define ASM_SYS_VECTOR_OFFSET (ASM_SYS_VECTOR << 8) +#define ASM_TRACE_VECTOR_OFFSET (ASM_TRACE_VECTOR << 8) +#define ASM_FLOATASSIST_VECTOR_OFFSET (ASM_FLOATASSIST_VECTOR << 8) + +#define ASM_ITLBMISS_VECTOR_OFFSET (ASM_ITLBMISS_VECTOR << 8) +#define ASM_DTLBLMISS_VECTOR_OFFSET (ASM_DTLBLMISS_VECTOR << 8) +#define ASM_DTLBSMISS_VECTOR_OFFSET (ASM_DTLBSMISS_VECTOR << 8) + +#define ASM_IBREAK_VECTOR_OFFSET (ASM_IBREAK_VECTOR << 8) +#define ASM_SYSMANAGE_VECTOR_OFFSET (ASM_SYSMANAGE_VECTOR << 8) + +#ifndef ASM + +/* + * Type definition for raw exceptions. + */ + +typedef unsigned char rtems_vector; +struct __rtems_raw_except_connect_data__; +typedef void (*rtems_raw_except_func) (void); +typedef unsigned char rtems_raw_except_hdl_size; + +typedef struct { + rtems_vector vector; + rtems_raw_except_func raw_hdl; + rtems_raw_except_hdl_size raw_hdl_size; +}rtems_raw_except_hdl; + +typedef void (*rtems_raw_except_enable) (const struct __rtems_raw_except_connect_data__*); +typedef void (*rtems_raw_except_disable) (const struct __rtems_raw_except_connect_data__*); +typedef int (*rtems_raw_except_is_enabled) (const struct __rtems_raw_except_connect_data__*); + +typedef struct __rtems_raw_except_connect_data__{ + /* + * Exception vector (As defined in the manual) + */ + rtems_vector exceptIndex; + /* + * Exception raw handler. See comment on handler properties below in function prototype. + */ + rtems_raw_except_hdl hdl; + /* + * function for enabling raw exceptions. In order to be consistent + * with the fact that the raw connexion can defined in the + * libcpu library, this library should have no knowledge of + * board specific hardware to manage exceptions and thus the + * "on" routine must enable the except at processor level only. + * + */ + rtems_raw_except_enable on; + /* + * function for disabling raw exceptions. In order to be consistent + * with the fact that the raw connexion can defined in the + * libcpu library, this library should have no knowledge of + * board specific hardware to manage exceptions and thus the + * "on" routine must disable the except both at device and PIC level. + * + */ + rtems_raw_except_disable off; + /* + * function enabling to know what exception may currently occur + */ + rtems_raw_except_is_enabled isOn; +}rtems_raw_except_connect_data; + +typedef struct { + /* + * size of all the table fields (*Tbl) described below. + */ + unsigned int exceptSize; + /* + * Default handler used when disconnecting exceptions. + */ + rtems_raw_except_connect_data defaultRawEntry; + /* + * Table containing initials/current value. + */ + rtems_raw_except_connect_data* rawExceptHdlTbl; +}rtems_raw_except_global_settings; + +/* + * C callable function enabling to set up one raw idt entry + */ +extern int mpc8xx_set_exception (const rtems_raw_except_connect_data*); + +/* + * C callable function enabling to get one current raw idt entry + */ +extern int mpc8xx_get_current_exception (rtems_raw_except_connect_data*); + +/* + * C callable function enabling to remove one current raw idt entry + */ +extern int mpc8xx_delete_exception (const rtems_raw_except_connect_data*); + +/* + * C callable function enabling to check if vector is valid + */ +extern int mpc8xx_vector_is_valid(rtems_vector vector); + +inline static void* mpc8xx_get_vector_addr(rtems_vector vector) +{ + return ((void*) (((unsigned) vector) << 8)); +} +/* + * Exception global init. + */ +extern int mpc8xx_init_exceptions (rtems_raw_except_global_settings* config); +extern int mpc8xx_get_exception_config (rtems_raw_except_global_settings** config); + +# endif /* ASM */ + +#endif + diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/Makefile.am b/c/src/lib/libcpu/powerpc/mpc8260/include/Makefile.am new file mode 100644 index 0000000000..5dc0a978f2 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/Makefile.am @@ -0,0 +1,27 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +H_FILES = mpc8260.h +MPC8260_H_FILES = console.h mmu.h cpm.h + +noinst_HEADERS = $(H_FILES) $(MPC8260_H_FILES) + +PREINSTALL_FILES += $(PROJECT_INCLUDE)/mpc8260 \ + $(H_FILES:%.h=$(PROJECT_INCLUDE)/%.h) \ + $(MPC8260_H_FILES:%.h=$(PROJECT_INCLUDE)/mpc8260/%.h) + +$(PROJECT_INCLUDE)/mpc8260: + $(mkinstalldirs) $@ + +$(PROJECT_INCLUDE)/%.h: %.h + $(INSTALL_DATA) $< $@ + +$(PROJECT_INCLUDE)/mpc8260/%.h: %.h + $(INSTALL_DATA) $< $@ + +all-local: $(PREINSTALL_FILES) + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/console.h b/c/src/lib/libcpu/powerpc/mpc8260/include/console.h new file mode 100644 index 0000000000..d9527fcf95 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/console.h @@ -0,0 +1,65 @@ +/* + * $Id$ + */ + +#ifndef _M8260_CONSOLE_H_ +#define _M8260_CONSOLE_H_ + +#include + +void m8xx_uart_reserve_resources(rtems_configuration_table *configuration); +void m8xx_uart_initialize(void); +void m8xx_uart_interrupts_initialize(void); +void m8xx_uart_scc_initialize (int minor); +void m8xx_uart_smc_initialize (int minor); + +/* Termios callbacks */ +int m8xx_uart_pollRead(int minor); +int m8xx_uart_pollWrite(int minor, const char* buf, int len); +int m8xx_uart_write(int minor, const char *buf, int len); +int m8xx_uart_setAttributes(int, const struct termios* t); + + +#if 0 +int m8260_smc_set_attributes(int, const struct termios*); +int m8260_scc_set_attributes(int, const struct termios*); +void m8260_scc_initialize(int); +void m8260_smc_initialize(int); +int m8260_char_poll_read(int); +int m8260_char_poll_write(int, const char*, int); +rtems_isr m8260_scc1_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_scc2_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_scc3_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_scc4_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_smc1_console_interrupt_handler(rtems_vector_number); +rtems_isr m8260_smc2_console_interrupt_handler(rtems_vector_number); +int m8260_buf_poll_read(int, char**); +int m8260_buf_poll_write(int, char*, int); +void m8260_console_initialize(void); +rtems_device_driver m8260_console_read(rtems_device_major_number, + rtems_device_minor_number, + void*); +rtems_device_driver m8260_console_write(rtems_device_major_number, + rtems_device_minor_number, + void*); + + +typedef struct Buf_t_ { + struct Buf_t_ *next; + volatile char *buf; + volatile int len; + int pos; +} Buf_t; +#endif + +#define NUM_PORTS 6 + +#define SMC1_MINOR 0 +#define SMC2_MINOR 1 +#define SCC1_MINOR 2 +#define SCC2_MINOR 3 +#define SCC3_MINOR 4 +#define SCC4_MINOR 5 + + +#endif diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h b/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h new file mode 100644 index 0000000000..eec10bbf98 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/cpm.h @@ -0,0 +1,123 @@ +/* + * cpm.h + * + * This include file contains definitions pertaining + * to the Communications Processor Module (CPM) on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + */ + +#ifndef __M8xx_CPM_h +#define __M8xx_CPM_h + +#ifdef __cplusplus +extern "C" { +#endif + + +#define M8xx_BRG_1 (1U << 0) +#define M8xx_BRG_2 (1U << 1) +#define M8xx_BRG_3 (1U << 2) +#define M8xx_BRG_4 (1U << 3) +#define M8xx_BRG_5 (1U << 4) +#define M8xx_BRG_6 (1U << 5) +#define M8xx_BRG_7 (1U << 6) +#define M8xx_BRG_8 (1U << 7) + + +#define M8260_SCC_BRGS (M8xx_BRG_1 | M8xx_BRG_2 | M8xx_BRG_3 | M8xx_BRG_4) +#define M8260_FCC_BRGS (M8xx_BRG_5 | M8xx_BRG_6 | M8xx_BRG_7 | M8xx_BRG_8) +#define M8260_SMC1_BRGS (M8xx_BRG_1|M8xx_BRG_7) +#define M8260_SMC2_BRGS (M8xx_BRG_2|M8xx_BRG_8) + + +#define M8xx_CLK_1 (1U << 0) +#define M8xx_CLK_2 (1U << 1) +#define M8xx_CLK_3 (1U << 2) +#define M8xx_CLK_4 (1U << 3) +#define M8xx_CLK_5 (1U << 4) +#define M8xx_CLK_6 (1U << 5) +#define M8xx_CLK_7 (1U << 6) +#define M8xx_CLK_8 (1U << 7) +#define M8xx_CLK_9 (1U << 8) +#define M8xx_CLK_10 (1U << 9) +#define M8xx_CLK_11 (1U << 10) +#define M8xx_CLK_12 (1U << 11) +#define M8xx_CLK_13 (1U << 12) +#define M8xx_CLK_14 (1U << 13) +#define M8xx_CLK_15 (1U << 14) +#define M8xx_CLK_16 (1U << 15) +#define M8xx_CLK_17 (1U << 16) +#define M8xx_CLK_18 (1U << 17) +#define M8xx_CLK_19 (1U << 18) +#define M8xx_CLK_20 (1U << 19) + +#define M8260_BRG1_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG2_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG3_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) +#define M8260_BRG4_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) +#define M8260_BRG5_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG6_CLKS (M8xx_CLK_3 | M8xx_CLK_5 ) +#define M8260_BRG7_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) +#define M8260_BRG8_CLKS (M8xx_CLK_9 | M8xx_CLK_15 ) + +#define M8260_SCC1_CLKS (M8xx_CLK_3 | M8xx_CLK_4 | M8xx_CLK_11 | M8xx_CLK_12) +#define M8260_SCC2_CLKS (M8xx_CLK_3 | M8xx_CLK_4 | M8xx_CLK_11 | M8xx_CLK_12) +#define M8260_SCC3_CLKS (M8xx_CLK_5 | M8xx_CLK_6 | M8xx_CLK_7 | M8xx_CLK_8 ) +#define M8260_SCC4_CLKS (M8xx_CLK_5 | M8xx_CLK_6 | M8xx_CLK_7 | M8xx_CLK_8 ) + +#define M8260_FCC1_CLKS (M8xx_CLK_9 | M8xx_CLK_10 | M8xx_CLK_11 | M8xx_CLK_12) +#define M8260_FCC2_CLKS (M8xx_CLK_13 | M8xx_CLK_14 | M8xx_CLK_15 | M8xx_CLK_16) +#define M8260_FCC3_CLKS (M8xx_CLK_13 | M8xx_CLK_14 | M8xx_CLK_15 | M8xx_CLK_16) + +#define M8260_TDM_RXA1 (M8xx_CLK_1 | M8xx_CLK_19 ) +#define M8260_TDM_RXB1 (M8xx_CLK_3 | M8xx_CLK_9 ) +#define M8260_TDM_RXC1 (M8xx_CLK_5 | M8xx_CLK_13 ) +#define M8260_TDM_RXD1 (M8xx_CLK_7 | M8xx_CLK_15 ) +#define M8260_TDM_TXA1 (M8xx_CLK_2 | M8xx_CLK_20 ) +#define M8260_TDM_TXB1 (M8xx_CLK_4 | M8xx_CLK_10 ) +#define M8260_TDM_TXC1 (M8xx_CLK_6 | M8xx_CLK_14 ) +#define M8260_TDM_TXD1 (M8xx_CLK_8 | M8xx_CLK_16 ) + +#define M8260_TDM_RXA2 (M8xx_CLK_13 | M8xx_CLK_5 ) +#define M8260_TDM_RXB2 (M8xx_CLK_15 | M8xx_CLK_17 ) +#define M8260_TDM_RXC2 (M8xx_CLK_3 | M8xx_CLK_17 ) +#define M8260_TDM_RXD2 (M8xx_CLK_1 | M8xx_CLK_19 ) +#define M8260_TDM_TXA2 (M8xx_CLK_14 | M8xx_CLK_6 ) +#define M8260_TDM_TXB2 (M8xx_CLK_16 | M8xx_CLK_18 ) +#define M8260_TDM_TXC2 (M8xx_CLK_4 | M8xx_CLK_18 ) +#define M8260_TDM_TXD2 (M8xx_CLK_2 | M8xx_CLK_20 ) + + + +/* Functions */ + +void m8xx_cp_execute_cmd( unsigned32 command ); +void *m8xx_dpram_allocate( unsigned int byte_count ); + +#define m8xx_bd_allocate(count) \ + m8xx_dpram_allocate( (count) * sizeof(m8260BufferDescriptor_t) ) +#define m8xx_RISC_timer_table_allocate(count) \ + m8xx_dpram_allocate( (count) * 4 ) + + + +int m8xx_get_brg_cd (int baud); +int m8xx_get_brg(unsigned brgmask, int baud); +void m8xx_free_brg(int brg_num); + + +int m8xx_get_clk( unsigned clkmask ); +void m8xx_free_clk( int clk_num ); + + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h b/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h new file mode 100644 index 0000000000..45a1c697ae --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/mmu.h @@ -0,0 +1,47 @@ +/* + * mmu.h + * + * This include file contains definitions pertaining + * to the MMU on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + */ + +#ifndef __M8260_MMU_h +#define __M8260_MMU_h + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * The MMU_TLB_table is used to statically initialize the Table Lookaside + * Buffers in the MMU of an MPC8260. + */ +typedef struct { + unsigned32 mmu_epn; /* Effective Page Number */ + unsigned32 mmu_twc; /* Tablewalk Control Register */ + unsigned32 mmu_rpn; /* Real Page Number */ +} MMU_TLB_table_t; + +/* + * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be + * supplied by the BSP. + */ +extern MMU_TLB_table_t MMU_TLB_table[]; /* MMU TLB table supplied by BSP */ +extern int MMU_N_TLB_Table_Entries; /* Number of entries in MMU TLB table */ + +/* Functions */ + +void mmu_init( void ); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h b/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h new file mode 100644 index 0000000000..d6126afbf2 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/include/mpc8260.h @@ -0,0 +1,1510 @@ +/* buggy version of CPU */ +#define REV_0_2 + +/* +************************************************************************** +************************************************************************** +** ** +** MOTOROLA MPC8260 POWER QUAD INTEGRATED COMMUNICATIONS CONTROLLER ** +** POWERQUICC II ** +** ** +** HARDWARE DECLARATIONS ** +** ** +** ** +** Submitted by: ** +** Andy Dachs ** ** +** Surrey Satellite Technology Limited ** ** +** http://www.sstl.co.uk ** ** +** a.dachs@sstl.co.uk ** ** +** ** +** Based on previous submissions for other PPC variants by: ** +** ** +** Submitted By: ** +** ** +** W. Eric Norum ** +** Saskatchewan Accelerator Laboratory ** +** University of Saskatchewan ** +** 107 North Road ** +** Saskatoon, Saskatchewan, CANADA ** +** S7N 5C6 ** +** ** +** eric@skatter.usask.ca ** +** ** +** Modified for use with the MPC860 (original code was for MC68360) ** +** by ** +** Jay Monkman ** +** Frasca International, Inc. ** +** 906 E. Airport Rd. ** +** Urbana, IL, 61801 ** +** ** +** jmonkman@frasca.com ** +** ** +** ** +************************************************************************** +************************************************************************** +*/ + +#ifndef __MPC8260_h +#define __MPC8260_h + +#ifndef ASM +/* + Macros for SPRs +*/ + + + + +/* +************************************************************************* +* REGISTER SUBBLOCKS * +************************************************************************* +*/ + + +/* + * Memory controller registers + */ +typedef struct m8260MEMCRegisters_ { + rtems_unsigned32 br; + rtems_unsigned32 or; +} m8260MEMCRegisters_t; + + +/* + * Fast Communication Controller Registers +*/ +typedef struct m8260FCCRegisters_ { + rtems_unsigned32 gfmr; + rtems_unsigned32 fpsmr; + rtems_unsigned16 ftodr; + rtems_unsigned8 fcc_pad0[2]; + rtems_unsigned16 fdsr; + rtems_unsigned8 fcc_pad1[2]; + rtems_unsigned32 fcce; + rtems_unsigned32 fccm; + rtems_unsigned8 fccs; + rtems_unsigned8 fcc_pad2[3]; + rtems_unsigned8 ftirr_phy0; /* n/a on FCC3 */ + rtems_unsigned8 ftirr_phy1; /* n/a on FCC3 */ + rtems_unsigned8 ftirr_phy2; /* n/a on FCC3 */ + rtems_unsigned8 ftirr_phy3; /* n/a on FCC3 */ +} m8260FCCRegisters_t; + + +/* + * Serial Communications Controller registers + */ +typedef struct m8260SCCRegisters_ { + rtems_unsigned32 gsmr_l; + rtems_unsigned32 gsmr_h; + rtems_unsigned16 psmr; + rtems_unsigned8 scc_pad0[2]; + rtems_unsigned16 todr; + rtems_unsigned16 dsr; + rtems_unsigned16 scce; + rtems_unsigned8 scc_pad2[2]; + rtems_unsigned16 sccm; + rtems_unsigned8 scc_pad3[1]; + rtems_unsigned8 sccs; + rtems_unsigned8 scc_pad1[8]; +} m8260SCCRegisters_t; + +/* + * Serial Management Controller registers + */ +typedef struct m8260SMCRegisters_ { + rtems_unsigned8 smc_pad0[2]; + rtems_unsigned16 smcmr; + rtems_unsigned8 smc_pad2[2]; + rtems_unsigned8 smce; + rtems_unsigned8 smc_pad3[3]; + rtems_unsigned8 smcm; + rtems_unsigned8 smc_pad1[5]; +} m8260SMCRegisters_t; + + +/* + * Serial Interface With Time Slot Assigner Registers + */ +typedef struct m8260SIRegisters_ { + rtems_unsigned16 siamr; + rtems_unsigned16 sibmr; + rtems_unsigned16 sicmr; + rtems_unsigned16 sidmr; + rtems_unsigned8 sigmr; + rtems_unsigned8 si_pad0[1]; + rtems_unsigned8 sicmdr; + rtems_unsigned8 si_pad1[1]; + rtems_unsigned8 sistr; + rtems_unsigned8 si_pad2[1]; + rtems_unsigned16 sirsr; +} m8260SIRegisters_t; + + +/* + * Multi Channel Controller registers + */ +typedef struct m8260MCCRegisters_ { + rtems_unsigned16 mcce; + rtems_unsigned8 mcc_pad2[2]; + rtems_unsigned16 mccm; + rtems_unsigned16 mcc_pad0; + rtems_unsigned8 mccf; + rtems_unsigned8 mcc_pad1[7]; +} m8260MCCRegisters_t; + + +/* +************************************************************************* +* RISC Timers * +************************************************************************* +*/ +/* +typedef struct m8260TimerParms_ { + rtems_unsigned16 tm_base; + rtems_unsigned16 _tm_ptr; + rtems_unsigned16 _r_tmr; + rtems_unsigned16 _r_tmv; + rtems_unsigned32 tm_cmd; + rtems_unsigned32 tm_cnt; +} m8260TimerParms_t; +*/ + +/* + * RISC Controller Configuration Register (RCCR) + * All other bits in this register are reserved. + */ +#define M8260_RCCR_TIME (1<<31) /* Enable timer */ +#define M8260_RCCR_TIMEP(x) ((x)<<24) /* Timer period */ +#define M8260_RCCR_DR1M (1<<23) /* IDMA Rqst 1 Mode */ +#define M8260_RCCR_DR2M (1<<22) /* IDMA Rqst 2 Mode */ +#define M8260_RCCR_DR1QP(x) ((x)<<20) /* IDMA1 Rqst Priority */ +#define M8260_RCCR_EIE (1<<19) /* External Interrupt Enable */ +#define M8260_RCCR_SCD (1<<18) /* Scheduler Configuration */ +#define M8260_RCCR_DR2QP(x) ((x)<<16) /* IDMA2 Rqst Priority */ +#define M8260_RCCR_ERAM(x) ((x)<<13) /* Enable RAM Microcode */ +#define M8260_RCCR_EDM1 (1<<11) /* DRQ1 Edge detect mode */ +#define M8260_RCCR_EDM2 (1<<10) /* DRQ2 Edge detect mode */ +#define M8260_RCCR_EDM3 (1<<9) /* DRQ3 Edge detect mode */ +#define M8260_RCCR_EDM4 (1<<8) /* DRQ4 Edge detect mode */ +#define M8260_RCCR_DR3M (1<<7) /* IDMA Rqst 1 Mode */ +#define M8260_RCCR_DR4M (1<<6) /* IDMA Rqst 2 Mode */ +#define M8260_RCCR_DR3QP(x) ((x)<<4) /* IDMA3 Rqst Priority */ +#define M8260_RCCR_DEM12 (1<<3) /* DONE1,2 Edge detect mode */ +#define M8260_RCCR_DEM34 (1<<2) /* DONE3,4 Edge detect mode */ +#define M8260_RCCR_DR4QP(x) (x) /* IDMA4 Rqst Priority */ + + + +/* + * Command register + * Set up this register before issuing a M8260_CR_OP_SET_TIMER command. + */ +#if 0 +#define M8260_TM_CMD_V (1<<31) /* Set to enable timer */ +#define M8260_TM_CMD_R (1<<30) /* Set for automatic restart */ +#define M8260_TM_CMD_PWM (1<<29) /* Set for PWM operation */ +#define M8260_TM_CMD_TIMER(x) ((x)<<16) /* Select timer */ +#define M8260_TM_CMD_PERIOD(x) (x) /* Timer period (16 bits) */ +#endif + +/* +************************************************************************* +* DMA Controllers * +************************************************************************* +*/ +typedef struct m8260IDMAparms_ { + rtems_unsigned16 ibase; + rtems_unsigned16 dcm; + rtems_unsigned16 ibdptr; + rtems_unsigned16 dpr_buf; + rtems_unsigned16 _buf_inv; + rtems_unsigned16 ssmax; + rtems_unsigned16 _dpr_in_ptr; + rtems_unsigned16 sts; + rtems_unsigned16 _dpr_out_ptr; + rtems_unsigned16 seob; + rtems_unsigned16 deob; + rtems_unsigned16 dts; + rtems_unsigned16 _ret_add; + rtems_unsigned16 reserved; + rtems_unsigned32 _bd_cnt; + rtems_unsigned32 _s_ptr; + rtems_unsigned32 _d_ptr; + rtems_unsigned32 istate; +} m8260IDMAparms_t; + + +/* +************************************************************************* +* Serial Communication Controllers * +************************************************************************* +*/ + + +typedef struct m8260SCCparms_ { + rtems_unsigned16 rbase; + rtems_unsigned16 tbase; + rtems_unsigned8 rfcr; + rtems_unsigned8 tfcr; + rtems_unsigned16 mrblr; + rtems_unsigned32 _rstate; + rtems_unsigned32 _pad0; + rtems_unsigned16 _rbptr; + rtems_unsigned16 _pad1; + rtems_unsigned32 _pad2; + rtems_unsigned32 _tstate; + rtems_unsigned32 _pad3; + rtems_unsigned16 _tbptr; + rtems_unsigned16 _pad4; + rtems_unsigned32 _pad5; + rtems_unsigned32 _rcrc; + rtems_unsigned32 _tcrc; + union { + struct { + rtems_unsigned32 _res0; + rtems_unsigned32 _res1; + rtems_unsigned16 max_idl; + rtems_unsigned16 idlc; + rtems_unsigned16 brkcr; + rtems_unsigned16 parec; + rtems_unsigned16 frmec; + rtems_unsigned16 nosec; + rtems_unsigned16 brkec; + rtems_unsigned16 brklen; + rtems_unsigned16 uaddr[2]; + rtems_unsigned16 rtemp; + rtems_unsigned16 toseq; + rtems_unsigned16 character[8]; + rtems_unsigned16 rccm; + rtems_unsigned16 rccr; + rtems_unsigned16 rlbc; + } uart; + struct { + rtems_unsigned32 _pad0; + rtems_unsigned32 c_mask; + rtems_unsigned32 c_pres; + rtems_unsigned16 disfc; + rtems_unsigned16 crcec; + rtems_unsigned16 abtsc; + rtems_unsigned16 nmarc; + rtems_unsigned16 retrc; + rtems_unsigned16 mflr; + rtems_unsigned16 _max_cnt; + rtems_unsigned16 rfthr; + rtems_unsigned16 _rfcnt; + rtems_unsigned16 hmask; + rtems_unsigned16 haddr1; + rtems_unsigned16 haddr2; + rtems_unsigned16 haddr3; + rtems_unsigned16 haddr4; + rtems_unsigned16 _tmp; + rtems_unsigned16 _tmp_mb; + } hdlc; + struct { + rtems_unsigned32 _pad0; + rtems_unsigned32 crcc; + rtems_unsigned16 prcrc; + rtems_unsigned16 ptcrc; + rtems_unsigned16 parec; + rtems_unsigned16 bsync; + rtems_unsigned16 bdle; + rtems_unsigned16 character[8]; + rtems_unsigned16 rccm; + } bisync; + struct { + rtems_unsigned32 _crc_p; + rtems_unsigned32 _crc_c; + } transparent; + struct { + rtems_unsigned32 c_pres; + rtems_unsigned32 c_mask; + rtems_unsigned32 crcec; + rtems_unsigned32 alec; + rtems_unsigned32 disfc; + rtems_unsigned16 pads; + rtems_unsigned16 ret_lim; + rtems_unsigned16 _ret_cnt; + rtems_unsigned16 mflr; + rtems_unsigned16 minflr; + rtems_unsigned16 maxd1; + rtems_unsigned16 maxd2; + rtems_unsigned16 _maxd; + rtems_unsigned16 _dma_cnt; + rtems_unsigned16 _max_b; + rtems_unsigned16 gaddr1; + rtems_unsigned16 gaddr2; + rtems_unsigned16 gaddr3; + rtems_unsigned16 gaddr4; + rtems_unsigned32 _tbuf0data0; + rtems_unsigned32 _tbuf0data1; + rtems_unsigned32 _tbuf0rba0; + rtems_unsigned32 _tbuf0crc; + rtems_unsigned16 _tbuf0bcnt; + rtems_unsigned16 paddr_h; + rtems_unsigned16 paddr_m; + rtems_unsigned16 paddr_l; + rtems_unsigned16 p_per; + rtems_unsigned16 _rfbd_ptr; + rtems_unsigned16 _tfbd_ptr; + rtems_unsigned16 _tlbd_ptr; + rtems_unsigned32 _tbuf1data0; + rtems_unsigned32 _tbuf1data1; + rtems_unsigned32 _tbuf1rba0; + rtems_unsigned32 _tbuf1crc; + rtems_unsigned16 _tbuf1bcnt; + rtems_unsigned16 _tx_len; + rtems_unsigned16 iaddr1; + rtems_unsigned16 iaddr2; + rtems_unsigned16 iaddr3; + rtems_unsigned16 iaddr4; + rtems_unsigned16 _boff_cnt; + rtems_unsigned16 taddr_l; + rtems_unsigned16 taddr_m; + rtems_unsigned16 taddr_h; + } ethernet; + } un; +} m8260SCCparms_t; + + +/* + * Event and mask registers (SCCE, SCCM) + */ +#define M8260_SCCE_BRKE (1<<6) +#define M8260_SCCE_BRK (1<<5) +#define M8260_SCCE_TXE (1<<4) +#define M8260_SCCE_RXF (1<<3) +#define M8260_SCCE_BSY (1<<2) +#define M8260_SCCE_TX (1<<1) +#define M8260_SCCE_RX (1<<0) + + +/* +************************************************************************* +* Fast Serial Communication Controllers * +************************************************************************* +*/ + + +typedef struct m8260FCCparms_ { + rtems_unsigned16 riptr; + rtems_unsigned16 tiptr; + rtems_unsigned16 _pad0; + rtems_unsigned16 mrblr; + rtems_unsigned32 rstate; + rtems_unsigned32 rbase; + rtems_unsigned16 _rbdstat; + rtems_unsigned16 _rbdlen; + rtems_unsigned32 _rdptr; + rtems_unsigned32 tstate; + rtems_unsigned32 tbase; + rtems_unsigned16 _tbdstat; + rtems_unsigned16 _tbdlen; + rtems_unsigned32 _tdptr; + rtems_unsigned32 _rbptr; + rtems_unsigned32 _tbptr; + rtems_unsigned32 _rcrc; + rtems_unsigned32 _pad1; + rtems_unsigned32 _tcrc; + + union { + struct { + rtems_unsigned32 _pad0; + rtems_unsigned32 _pad1; + rtems_unsigned32 c_mask; + rtems_unsigned32 c_pres; + rtems_unsigned16 disfc; + rtems_unsigned16 crcec; + rtems_unsigned16 abtsc; + rtems_unsigned16 nmarc; + rtems_unsigned32 _max_cnt; + rtems_unsigned16 mflr; + rtems_unsigned16 rfthr; + rtems_unsigned16 rfcnt; + rtems_unsigned16 hmask; + rtems_unsigned16 haddr1; + rtems_unsigned16 haddr2; + rtems_unsigned16 haddr3; + rtems_unsigned16 haddr4; + rtems_unsigned16 _ts_tmp; + rtems_unsigned16 _tmp_mb; + } hdlc; + struct { + rtems_unsigned32 _pad0; + rtems_unsigned32 _pad1; + rtems_unsigned32 c_mask; + rtems_unsigned32 c_pres; + rtems_unsigned16 disfc; + rtems_unsigned16 crcec; + rtems_unsigned16 abtsc; + rtems_unsigned16 nmarc; + rtems_unsigned32 _max_cnt; + rtems_unsigned16 mflr; + rtems_unsigned16 rfthr; + rtems_unsigned16 rfcnt; + rtems_unsigned16 hmask; + rtems_unsigned16 haddr1; + rtems_unsigned16 haddr2; + rtems_unsigned16 haddr3; + rtems_unsigned16 haddr4; + rtems_unsigned16 _ts_tmp; + rtems_unsigned16 _tmp_mb; + } transparent; + struct { + rtems_unsigned32 _stat_buf; + rtems_unsigned32 cam_ptr; + rtems_unsigned32 c_mask; + rtems_unsigned32 c_pres; + rtems_unsigned32 crcec; + rtems_unsigned32 alec; + rtems_unsigned32 disfc; + rtems_unsigned16 ret_lim; + rtems_unsigned16 _ret_cnt; + rtems_unsigned16 p_per; + rtems_unsigned16 _boff_cnt; + rtems_unsigned32 gaddr_h; + rtems_unsigned32 gaddr_l; + rtems_unsigned16 tfcstat; + rtems_unsigned16 tfclen; + rtems_unsigned32 tfcptr; + rtems_unsigned16 mflr; + rtems_unsigned16 paddr1_h; + rtems_unsigned16 paddr1_m; + rtems_unsigned16 paddr1_l; + rtems_unsigned16 _ibd_cnt; + rtems_unsigned16 _ibd_start; + rtems_unsigned16 _ibd_end; + rtems_unsigned16 _tx_len; + rtems_unsigned16 _ibd_base; + rtems_unsigned32 iaddr_h; + rtems_unsigned32 iaddr_l; + rtems_unsigned16 minflr; + rtems_unsigned16 taddr_h; + rtems_unsigned16 taddr_m; + rtems_unsigned16 taddr_l; + rtems_unsigned16 pad_ptr; + rtems_unsigned16 _pad0; + rtems_unsigned16 _cf_range; + rtems_unsigned16 _max_b; + rtems_unsigned16 maxd1; + rtems_unsigned16 maxd2; + rtems_unsigned16 _maxd; + rtems_unsigned16 _dma_cnt; + rtems_unsigned32 octc; + rtems_unsigned32 colc; + rtems_unsigned32 broc; + rtems_unsigned32 mulc; + rtems_unsigned32 uspc; + rtems_unsigned32 frgc; + rtems_unsigned32 ospc; + rtems_unsigned32 jbrc; + rtems_unsigned32 p64c; + rtems_unsigned32 p65c; + rtems_unsigned32 p128c; + rtems_unsigned32 p256c; + rtems_unsigned32 p512c; + rtems_unsigned32 p1024c; + rtems_unsigned32 _cam_buf; + rtems_unsigned32 _pad1; + } ethernet; + } un; +} m8260FCCparms_t; + + +/* + * Receive and transmit function code register bits + * These apply to the function code registers of all devices, not just SCC. + */ +#define M8260_RFCR_BO(x) ((x)<<3) +#define M8260_RFCR_MOT (2<<3) +#define M8260_RFCR_LOCAL_BUS (2) +#define M8260_RFCR_60X_BUS (0) +#define M8260_TFCR_BO(x) ((x)<<3) +#define M8260_TFCR_MOT (2<<3) +#define M8260_TFCR_LOCAL_BUS (2) +#define M8260_TFCR_60X_BUS (0) + +/* +************************************************************************* +* Serial Management Controllers * +************************************************************************* +*/ +typedef struct m8260SMCparms_ { + rtems_unsigned16 rbase; + rtems_unsigned16 tbase; + rtems_unsigned8 rfcr; + rtems_unsigned8 tfcr; + rtems_unsigned16 mrblr; + rtems_unsigned32 _rstate; + rtems_unsigned32 _pad0; + rtems_unsigned16 _rbptr; + rtems_unsigned16 _pad1; + rtems_unsigned32 _pad2; + rtems_unsigned32 _tstate; + rtems_unsigned32 _pad3; + rtems_unsigned16 _tbptr; + rtems_unsigned16 _pad4; + rtems_unsigned32 _pad5; + union { + struct { + rtems_unsigned16 max_idl; + rtems_unsigned16 _idlc; + rtems_unsigned16 _brkln; + rtems_unsigned16 brkec; + rtems_unsigned16 brkcr; + rtems_unsigned16 _r_mask; + } uart; + struct { + rtems_unsigned16 _pad0[6]; + } transparent; + } un; + rtems_unsigned32 _pad6; +} m8260SMCparms_t; + +/* + * Mode register + */ +#define M8260_SMCMR_CLEN(x) ((x)<<11) /* Character length */ +#define M8260_SMCMR_2STOP (1<<10) /* 2 stop bits */ +#define M8260_SMCMR_PARITY (1<<9) /* Enable parity */ +#define M8260_SMCMR_EVEN (1<<8) /* Even parity */ +#define M8260_SMCMR_SM_GCI (0<<4) /* GCI Mode */ +#define M8260_SMCMR_SM_UART (2<<4) /* UART Mode */ +#define M8260_SMCMR_SM_TRANSPARENT (3<<4) /* Transparent Mode */ +#define M8260_SMCMR_DM_LOOPBACK (1<<2) /* Local loopback mode */ +#define M8260_SMCMR_DM_ECHO (2<<2) /* Echo mode */ +#define M8260_SMCMR_TEN (1<<1) /* Enable transmitter */ +#define M8260_SMCMR_REN (1<<0) /* Enable receiver */ + +/* + * Event and mask registers (SMCE, SMCM) + */ +#define M8260_SMCE_TXE (1<<4) +#define M8260_SMCE_BSY (1<<2) +#define M8260_SMCE_TX (1<<1) +#define M8260_SMCE_RX (1<<0) + +/* +************************************************************************* +* Serial Peripheral Interface * +************************************************************************* +*/ +typedef struct m8260SPIparms_ { + rtems_unsigned16 rbase; + rtems_unsigned16 tbase; + rtems_unsigned8 rfcr; + rtems_unsigned8 tfcr; + rtems_unsigned16 mrblr; + rtems_unsigned32 _rstate; + rtems_unsigned32 _pad0; + rtems_unsigned16 _rbptr; + rtems_unsigned16 _pad1; + rtems_unsigned32 _pad2; + rtems_unsigned32 _tstate; + rtems_unsigned32 _pad3; + rtems_unsigned16 _tbptr; + rtems_unsigned16 _pad4; + rtems_unsigned32 _pad5; +} m8260SPIparms_t; + +/* + * Mode register (SPMODE) + */ +#define M8260_SPMODE_LOOP (1<<14) /* Local loopback mode */ +#define M8260_SPMODE_CI (1<<13) /* Clock invert */ +#define M8260_SPMODE_CP (1<<12) /* Clock phase */ +#define M8260_SPMODE_DIV16 (1<<11) /* Divide BRGCLK by 16 */ +#define M8260_SPMODE_REV (1<<10) /* Reverse data */ +#define M8260_SPMODE_MASTER (1<<9) /* SPI is master */ +#define M8260_SPMODE_EN (1<<8) /* Enable SPI */ +#define M8260_SPMODE_CLEN(x) ((x)<<4) /* Character length */ +#define M8260_SPMODE_PM(x) (x) /* Prescaler modulus */ + +/* + * Mode register (SPCOM) + */ +#define M8260_SPCOM_STR (1<<7) /* Start transmit */ + +/* + * Event and mask registers (SPIE, SPIM) + */ +#define M8260_SPIE_MME (1<<5) /* Multi-master error */ +#define M8260_SPIE_TXE (1<<4) /* Tx error */ +#define M8260_SPIE_BSY (1<<2) /* Busy condition*/ +#define M8260_SPIE_TXB (1<<1) /* Tx buffer */ +#define M8260_SPIE_RXB (1<<0) /* Rx buffer */ + +/* +************************************************************************* +* SDMA (SCC, SMC, SPI) Buffer Descriptors * +************************************************************************* +*/ +typedef struct m8260BufferDescriptor_ { + rtems_unsigned16 status; + rtems_unsigned16 length; + volatile void *buffer; +} m8260BufferDescriptor_t; + +/* + * Bits in receive buffer descriptor status word + */ +#define M8260_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_LAST (1<<11) /* Ethernet, SPI */ +#define M8260_BD_CONTROL_CHAR (1<<11) /* SCC UART */ +#define M8260_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ +#define M8260_BD_ADDRESS (1<<10) /* SCC UART */ +#define M8260_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ +#define M8260_BD_MISS (1<<8) /* Ethernet */ +#define M8260_BD_IDLE (1<<8) /* SCC UART, SMC UART */ +#define M8260_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ +#define M8260_BD_LONG (1<<5) /* Ethernet, SCC HDLC */ +#define M8260_BD_BREAK (1<<5) /* SCC UART, SMC UART */ +#define M8260_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */ +#define M8260_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ +#define M8260_BD_SHORT (1<<3) /* Ethernet */ +#define M8260_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ +#define M8260_BD_ABORT (1<<3) /* SCC HDLC */ +#define M8260_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */ +#define M8260_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_COLLISION (1<<0) /* Ethernet */ +#define M8260_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ +#define M8260_BD_MASTER_ERROR (1<<0) /* SPI */ + +#define M8xx_BD_EMPTY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_WRAP (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_INTERRUPT (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_LAST (1<<11) /* Ethernet, SPI */ +#define M8xx_BD_CONTROL_CHAR (1<<11) /* SCC UART */ +#define M8xx_BD_FIRST_IN_FRAME (1<<10) /* Ethernet */ +#define M8xx_BD_ADDRESS (1<<10) /* SCC UART */ +#define M8xx_BD_CONTINUOUS (1<<9) /* SCC UART, SMC UART, SPI */ +#define M8xx_BD_MISS (1<<8) /* Ethernet */ +#define M8xx_BD_IDLE (1<<8) /* SCC UART, SMC UART */ +#define M8xx_BD_ADDRSS_MATCH (1<<7) /* SCC UART */ +#define M8xx_BD_LONG (1<<5) /* Ethernet, SCC HDLC */ +#define M8xx_BD_BREAK (1<<5) /* SCC UART, SMC UART */ +#define M8xx_BD_NONALIGNED (1<<4) /* Ethernet, SCC HDLC */ +#define M8xx_BD_FRAMING_ERROR (1<<4) /* SCC UART, SMC UART */ +#define M8xx_BD_SHORT (1<<3) /* Ethernet */ +#define M8xx_BD_PARITY_ERROR (1<<3) /* SCC UART, SMC UART */ +#define M8xx_BD_ABORT (1<<3) /* SCC HDLC */ +#define M8xx_BD_CRC_ERROR (1<<2) /* Ethernet, SCC HDLC */ +#define M8xx_BD_OVERRUN (1<<1) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_COLLISION (1<<0) /* Ethernet */ +#define M8xx_BD_CARRIER_LOST (1<<0) /* SCC UART, SMC UART */ +#define M8xx_BD_MASTER_ERROR (1<<0) /* SPI */ + +/* + * Bits in transmit buffer descriptor status word + * Many bits have the same meaning as those in receiver buffer descriptors. + */ +#define M8260_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8260_BD_PAD (1<<14) /* Ethernet */ +#define M8260_BD_CTS_REPORT (1<<11) /* SCC UART */ +#define M8260_BD_TX_CRC (1<<10) /* Ethernet */ +#define M8260_BD_DEFER (1<<9) /* Ethernet */ +#define M8260_BD_HEARTBEAT (1<<8) /* Ethernet */ +#define M8260_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ +#define M8260_BD_LATE_COLLISION (1<<7) /* Ethernet */ +#define M8260_BD_NO_STOP_BIT (1<<7) /* SCC UART */ +#define M8260_BD_RETRY_LIMIT (1<<6) /* Ethernet */ +#define M8260_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ +#define M8260_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */ +#define M8260_BD_CARRIER_LOST (1<<0) /* Ethernet */ +#define M8260_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */ + +#define M8xx_BD_READY (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */ +#define M8xx_BD_PAD (1<<14) /* Ethernet */ +#define M8xx_BD_CTS_REPORT (1<<11) /* SCC UART */ +#define M8xx_BD_TX_CRC (1<<10) /* Ethernet */ +#define M8xx_BD_DEFER (1<<9) /* Ethernet */ +#define M8xx_BD_HEARTBEAT (1<<8) /* Ethernet */ +#define M8xx_BD_PREAMBLE (1<<8) /* SCC UART, SMC UART */ +#define M8xx_BD_LATE_COLLISION (1<<7) /* Ethernet */ +#define M8xx_BD_NO_STOP_BIT (1<<7) /* SCC UART */ +#define M8xx_BD_RETRY_LIMIT (1<<6) /* Ethernet */ +#define M8xx_BD_RETRY_COUNT(x) (((x)&0x3C)>>2) /* Ethernet */ +#define M8xx_BD_UNDERRUN (1<<1) /* Ethernet, SPI, SCC HDLC */ +#define M8xx_BD_CARRIER_LOST (1<<0) /* Ethernet */ +#define M8xx_BD_CTS_LOST (1<<0) /* SCC UART, SCC HDLC */ + +/* +************************************************************************* +* IDMA Buffer Descriptors * +************************************************************************* +*/ +typedef struct m8260IDMABufferDescriptor_ { + rtems_unsigned16 status; + rtems_unsigned8 dfcr; + rtems_unsigned8 sfcr; + rtems_unsigned32 length; + void *source; + void *destination; +} m8260IDMABufferDescriptor_t; + +/* +************************************************************************* +* RISC Communication Processor Module Command Register (CR) * +************************************************************************* +*/ +#define M8260_CR_RST (1<<31) /* Reset communication processor */ + +#define M8260_CR_FCC1 ((4<<26)|(16<<21)) /* FCC1 page and code */ +#define M8260_CR_FCC1_ATM ((4<<26)|(14<<21)) /* FCC1 ATM mode page and code */ +#define M8260_CR_FCC2 ((5<<26)|(17<<21)) /* FCC2 page and code */ +#define M8260_CR_FCC2_ATM ((5<<26)|(14<<21)) /* FCC2 ATM mode page and code */ +#define M8260_CR_FCC3 ((6<<26)|(18<<21)) /* FCC3 page and code */ +#define M8260_CR_SCC1 ((0<<26)|(4<<21)) /* SCC1 page and code */ +#define M8260_CR_SCC2 ((1<<26)|(5<<21)) /* SCC2 page and code */ +#define M8260_CR_SCC3 ((2<<26)|(6<<21)) /* SCC3 page and code */ +#define M8260_CR_SCC4 ((3<<26)|(7<<21)) /* SCC4 page and code */ +#define M8260_CR_SMC1 ((7<<26)|(8<<21)) /* SMC1 page and code */ +#define M8260_CR_SMC2 ((8<<26)|(9<<21)) /* SMC2 page and code */ +#define M8260_CR_RAND ((10<<26)|(14<<21)) /* SMC2 page and code */ +#define M8260_CR_SPI ((9<<26)|(10<<21)) /* SPI page and code */ +#define M8260_CR_I2C ((10<<26)|(11<<21)) /* I2C page and code */ +#define M8260_CR_TMR ((10<<26)|(15<<21)) /* Timer page and code */ +#define M8260_CR_MCC1 ((7<<26)|(28<<21)) /* MCC1 page and code */ +#define M8260_CR_MCC2 ((8<<26)|(29<<21)) /* MCC2 page and code */ +#define M8260_CR_IDMA1 ((7<<26)|(20<<21)) /* IDMA1 page and code */ +#define M8260_CR_IDMA2 ((8<<26)|(21<<21)) /* IDMA2 page and code */ +#define M8260_CR_IDMA3 ((9<<26)|(22<<21)) /* IDMA3 page and code */ +#define M8260_CR_IDMA4 ((10<<26)|(23<<21)) /* IDMA4 page and code */ + +#define M8260_CR_FLG (1<<16) /* Command sempahore flag */ + +#define M8260_CR_MCC_CHAN(x) ((x)<<6) /* MCC channel number */ +#define M8260_CR_FCC_HDLC (0<<6) /* FCC HDLC/Transparent protocol code */ +#define M8260_CR_FCC_ATM (10<<6) /* FCC ATM protocol code */ +#define M8260_CR_FCC_ETH (12<<6) /* FCC Ethernet protocol code */ + +#define M8260_CR_OP_INIT_RX_TX (0) /* FCC, SCC, SMC UART, SMC GCI, SPI, I2C, MCC */ +#define M8260_CR_OP_INIT_RX (1) /* FCC, SCC, SMC UART, SPI, I2C, MCC */ +#define M8260_CR_OP_INIT_TX (2) /* FCC, SCC, SMC UART, SPI, I2C, MCC */ +#define M8260_CR_OP_INIT_HUNT (3) /* FCC, SCC, SMC UART */ +#define M8260_CR_OP_STOP_TX (4) /* FCC, SCC, SMC UART, MCC */ +#define M8260_CR_OP_GR_STOP_TX (5) /* FCC, SCC */ +#define M8260_CR_OP_RESTART_TX (6) /* FCC, SCC, SMC UART */ +#define M8260_CR_OP_CLOSE_RX_BD (7) /* FCC, SCC, SMC UART, SPI, I2C */ +#define M8260_CR_OP_SET_GRP_ADDR (8) /* FCC, SCC */ +#define M8260_CR_OP_SET_TIMER (8) /* Timer */ +#define M8260_CR_OP_GCI_TIMEOUT (9) /* SMC GCI */ +#define M8260_CR_OP_START_IDMA (9) /* IDMA */ +#define M8260_CR_OP_STOP_RX (9) /* MCC */ +#define M8260_CR_OP_ATM_TX (10) /* FCC */ +#define M8260_CR_OP_RESET_BCS (10) /* SCC */ +#define M8260_CR_OP_GCI_ABORT (10) /* SMC GCI */ +#define M8260_CR_OP_STOP_IDMA (11) /* IDMA */ +#define M8260_CR_OP_RANDOM (12) /* RAND */ + +/* +************************************************************************* +* System Protection Control Register (SYPCR) * +************************************************************************* +*/ +#define M8260_SYPCR_SWTC(x) ((x)<<16) /* Software watchdog timer count */ +#define M8260_SYPCR_BMT(x) ((x)<<8) /* Bus monitor timing */ +#define M8260_SYPCR_BME (1<<7) /* Bus monitor enable */ +#define M8260_SYPCR_SWF (1<<3) /* Software watchdog freeze */ +#define M8260_SYPCR_SWE (1<<2) /* Software watchdog enable */ +#define M8260_SYPCR_SWRI (1<<1) /* Watchdog reset/interrupt sel. */ +#define M8260_SYPCR_SWP (1<<0) /* Software watchdog prescale */ + +/* +************************************************************************* +* Memory Control Registers * +************************************************************************* +*/ +#define M8260_UPM_AMX_8col (0<<20) /* 8 column DRAM */ +#define M8260_UPM_AMX_9col (1<<20) /* 9 column DRAM */ +#define M8260_UPM_AMX_10col (2<<20) /* 10 column DRAM */ +#define M8260_UPM_AMX_11col (3<<20) /* 11 column DRAM */ +#define M8260_UPM_AMX_12col (4<<20) /* 12 column DRAM */ +#define M8260_UPM_AMX_13col (5<<20) /* 13 column DRAM */ +#define M8260_MSR_PER(x) (0x100<<(7-x)) /* Perity error bank (x) */ +#define M8260_MSR_WPER (1<<7) /* Write protection error */ +#define M8260_MPTPR_PTP(x) ((x)<<8) /* Periodic timer prescaler */ +#define M8260_BR_BA(x) ((x)&0xffff8000) /* Base address */ +#define M8260_BR_AT(x) ((x)<<12) /* Address type */ +#define M8260_BR_PS8 (1<<10) /* 8 bit port */ +#define M8260_BR_PS16 (2<<10) /* 16 bit port */ +#define M8260_BR_PS32 (0<<10) /* 32 bit port */ +#define M8260_BR_PARE (1<<9) /* Parity checking enable */ +#define M8260_BR_WP (1<<8) /* Write protect */ +#define M8260_BR_MS_GPCM (0<<6) /* GPCM */ +#define M8260_BR_MS_UPMA (2<<6) /* UPM A */ +#define M8260_BR_MS_UPMB (3<<6) /* UPM B */ +#define M8260_MEMC_BR_V (1<<0) /* Base/Option register are valid */ + +#define M8260_MEMC_OR_32K 0xffff8000 /* Address range */ +#define M8260_MEMC_OR_64K 0xffff0000 +#define M8260_MEMC_OR_128K 0xfffe0000 +#define M8260_MEMC_OR_256K 0xfffc0000 +#define M8260_MEMC_OR_512K 0xfff80000 +#define M8260_MEMC_OR_1M 0xfff00000 +#define M8260_MEMC_OR_2M 0xffe00000 +#define M8260_MEMC_OR_4M 0xffc00000 +#define M8260_MEMC_OR_8M 0xff800000 +#define M8260_MEMC_OR_16M 0xff000000 +#define M8260_MEMC_OR_32M 0xfe000000 +#define M8260_MEMC_OR_64M 0xfc000000 +#define M8260_MEMC_OR_128 0xf8000000 +#define M8260_MEMC_OR_256M 0xf0000000 +#define M8260_MEMC_OR_512M 0xe0000000 +#define M8260_MEMC_OR_1G 0xc0000000 +#define M8260_MEMC_OR_2G 0x80000000 +#define M8260_MEMC_OR_4G 0x00000000 +#define M8260_MEMC_OR_ATM(x) ((x)<<12) /* Address type mask */ +#define M8260_MEMC_OR_CSNT (1<<11) /* Chip select is negated early */ +#define M8260_MEMC_OR_SAM (1<<11) /* Address lines are multiplexed */ +#define M8260_MEMC_OR_ACS_NORM (0<<9) /* *CS asserted with addr lines */ +#define M8260_MEMC_OR_ACS_QRTR (2<<9) /* *CS asserted 1/4 after addr */ +#define M8260_MEMC_OR_ACS_HALF (3<<9) /* *CS asserted 1/2 after addr */ +#define M8260_MEMC_OR_BI (1<8) /* Burst inhibit */ +#define M8260_MEMC_OR_SCY(x) ((x)<<4) /* Cycle length in clocks */ +#define M8260_MEMC_OR_SETA (1<<3) /* *TA generated externally */ +#define M8260_MEMC_OR_TRLX (1<<2) /* Relaxed timing in GPCM */ +#define M8260_MEMC_OR_EHTR (1<<1) /* Extended hold time on reads */ + +/* +************************************************************************* +* UPM Registers (MxMR) * +************************************************************************* +*/ +#define M8260_MEMC_MMR_PTP(x) ((x)<<24) /* Periodic timer period */ +#define M8260_MEMC_MMR_PTE (1<<23) /* Periodic timer enable */ +#define M8260_MEMC_MMR_DSP(x) ((x)<<17) /* Disable timer period */ +#define M8260_MEMC_MMR_G0CL(x) ((x)<<13) /* General line 0 control */ +#define M8260_MEMC_MMR_UPWAIT (1<<12) /* GPL_x4 is UPWAITx */ +#define M8260_MEMC_MMR_RLF(x) ((x)<<8) /* Read loop field */ +#define M8260_MEMC_MMR_WLF(x) ((x)<<4) /* Write loop field */ +#define M8260_MEMC_MMR_TLF(x) ((x)<<0) /* Timer loop field */ +/* +************************************************************************* +* Memory Command Register (MCR) * +************************************************************************* +*/ +#define M8260_MEMC_MCR_WRITE (0<<30) /* WRITE command */ +#define M8260_MEMC_MCR_READ (1<<30) /* READ command */ +#define M8260_MEMC_MCR_RUN (2<<30) /* RUN command */ +#define M8260_MEMC_MCR_UPMA (0<<23) /* Cmd is for UPMA */ +#define M8260_MEMC_MCR_UPMB (1<<23) /* Cmd is for UPMB */ +#define M8260_MEMC_MCR_MB(x) ((x)<<13) /* Memory bank when RUN cmd */ +#define M8260_MEMC_MCR_MCLF(x) ((x)<<8) /* Memory command loop field */ +#define M8260_MEMC_MCR_MAD(x) (x) /* Machine address */ + + + +/* +************************************************************************* +* SI Mode Register (SIMODE) * +************************************************************************* +*/ +#define M8260_SI_SMC2_BITS 0xFFFF0000 /* All SMC2 bits */ +#define M8260_SI_SMC2_TDM (1<<31) /* Multiplexed SMC2 */ +#define M8260_SI_SMC2_BRG1 (0<<28) /* SMC2 clock souce */ +#define M8260_SI_SMC2_BRG2 (1<<28) +#define M8260_SI_SMC2_BRG3 (2<<28) +#define M8260_SI_SMC2_BRG4 (3<<28) +#define M8260_SI_SMC2_CLK5 (0<<28) +#define M8260_SI_SMC2_CLK6 (1<<28) +#define M8260_SI_SMC2_CLK7 (2<<28) +#define M8260_SI_SMC2_CLK8 (3<<28) +#define M8260_SI_SMC1_BITS 0x0000FFFF /* All SMC1 bits */ +#define M8260_SI_SMC1_TDM (1<<15) /* Multiplexed SMC1 */ +#define M8260_SI_SMC1_BRG1 (0<<12) /* SMC1 clock souce */ +#define M8260_SI_SMC1_BRG2 (1<<12) +#define M8260_SI_SMC1_BRG3 (2<<12) +#define M8260_SI_SMC1_BRG4 (3<<12) +#define M8260_SI_SMC1_CLK1 (0<<12) +#define M8260_SI_SMC1_CLK2 (1<<12) +#define M8260_SI_SMC1_CLK3 (2<<12) +#define M8260_SI_SMC1_CLK4 (3<<12) + +/* +************************************************************************* +* SDMA Configuration Register (SDCR) * +************************************************************************* +*/ +#define M8260_SDCR_FREEZE (2<<13) /* Freeze on next bus cycle */ +#define M8260_SDCR_RAID_5 (1<<0) /* Normal arbitration ID */ + +/* +************************************************************************* +* SDMA Status Register (SDSR) * +************************************************************************* +*/ +#define M8260_SDSR_SBER (1<<7) /* SDMA Channel bus error */ +#define M8260_SDSR_DSP2 (1<<1) /* DSP Chain 2 interrupt */ +#define M8260_SDSR_DSP1 (1<<0) /* DSP Chain 1 interrupt */ + +/* +************************************************************************* +* Baud (sic) Rate Generators * +************************************************************************* +*/ +#define M8260_BRG_RST (1<<17) /* Reset generator */ +#define M8260_BRG_EN (1<<16) /* Enable generator */ +#define M8260_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ +#define M8260_BRG_EXTC_CLK2 (1<<14) /* Source is CLK2 pin */ +#define M8260_BRG_EXTC_CLK6 (2<<14) /* Source is CLK6 pin */ +#define M8260_BRG_ATB (1<<13) /* Autobaud */ +#define M8260_BRG_115200 (21<<1) /* Assume 40 MHz clock */ +#define M8260_BRG_57600 (32<<1) +#define M8260_BRG_38400 (64<<1) +#define M8260_BRG_19200 (129<<1) +#define M8260_BRG_9600 (259<<1) +#define M8260_BRG_4800 (520<<1) +#define M8260_BRG_2400 (1040<<1) +#define M8260_BRG_1200 (2082<<1) +#define M8260_BRG_600 ((259<<1) | 1) +#define M8260_BRG_300 ((520<<1) | 1) +#define M8260_BRG_150 ((1040<<1) | 1) +#define M8260_BRG_75 ((2080<<1) | 1) + +#define M8xx_BRG_RST (1<<17) /* Reset generator */ +#define M8xx_BRG_EN (1<<16) /* Enable generator */ +#define M8xx_BRG_EXTC_BRGCLK (0<<14) /* Source is BRGCLK */ + +#define M8260_BRG1 (1<<7) +#define M8260_BRG2 (1<<6) +#define M8260_BRG3 (1<<5) +#define M8260_BRG4 (1<<4) +#define M8260_BRG5 (1<<3) +#define M8260_BRG6 (1<<2) +#define M8260_BRG7 (1<<1) +#define M8260_BRG8 (1<<0) + + + +#define M8260_TGCR_CAS4 (1<<15) /* Cascade timers 3 and 4 */ +#define M8260_TGCR_CAS2 (1<<7) /* Cascade timers 1 and 2 */ +#define M8260_TGCR_FRZ1 (1<<2) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_FRZ2 (1<<6) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_FRZ3 (1<<10) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_FRZ4 (1<<14) /* Halt timer if FREEZE asserted */ +#define M8260_TGCR_STP1 (1<<1) /* Stop timer */ +#define M8260_TGCR_STP2 (1<<5) /* Stop timer */ +#define M8260_TGCR_STP3 (1<<9) /* Stop timer */ +#define M8260_TGCR_STP4 (1<<13) /* Stop timer */ +#define M8260_TGCR_RST1 (1<<0) /* Enable timer */ +#define M8260_TGCR_RST2 (1<<4) /* Enable timer */ +#define M8260_TGCR_RST3 (1<<8) /* Enable timer */ +#define M8260_TGCR_RST4 (1<<12) /* Enable timer */ +#define M8260_TGCR_GM1 (1<<3) /* Gate Mode 1 for TMR1 or TMR2 */ +#define M8260_TGCR_GM2 (1<<11) /* Gate Mode 2 for TMR3 or TMR4 */ + +#define M8260_TMR_PS(x) ((x)<<8) /* Timer prescaler */ +#define M8260_TMR_CE_RISE (1<<6) /* Capture on rising edge */ +#define M8260_TMR_CE_FALL (2<<6) /* Capture on falling edge */ +#define M8260_TMR_CE_ANY (3<<6) /* Capture on any edge */ +#define M8260_TMR_OM_TOGGLE (1<<5) /* Toggle TOUTx pin */ +#define M8260_TMR_ORI (1<<4) /* Interrupt on reaching reference */ +#define M8260_TMR_RESTART (1<<3) /* Restart timer after reference */ +#define M8260_TMR_ICLK_INT (1<<1) /* Internal clock is timer source */ +#define M8260_TMR_ICLK_INT16 (2<<1) /* Internal clock/16 is tmr src */ +#define M8260_TMR_ICLK_TIN (3<<1) /* TIN pin is timer source */ +#define M8260_TMR_TGATE (1<<0) /* TGATE controls timer */ + +#ifdef REV_0_2 +#define M8260_PISCR_PS (1<<6) /* PIT Interrupt state */ +#else +#define M8260_PISCR_PS (1<<7) /* PIT Interrupt state */ +#endif +#define M8260_PISCR_PIE (1<<2) /* PIT interrupt enable */ +#define M8260_PISCR_PTF (1<<1) /* Stop timer when freeze asserted */ +#define M8260_PISCR_PTE (1<<0) /* PIT enable */ + +#if 0 +#define M8260_TBSCR_TBIRQ(x) (1<<(15-x)) /* TB interrupt level */ +#define M8260_TBSCR_REFA (1<<7) /* TB matches TBREFF0 */ +#define M8260_TBSCR_REFB (1<<6) /* TB matches TBREFF1 */ +#define M8260_TBSCR_REFAE (1<<3) /* Enable ints for REFA */ +#define M8260_TBSCR_REFBE (1<<2) /* Enable ints for REFB */ +#define M8260_TBSCR_TBF (1<<1) /* TB stops on FREEZE */ +#define M8260_TBSCR_TBE (1<<0) /* enable TB and decrementer */ +#endif + +#define M8260_TMCNTSC_SEC (1<<7) /* per second flag */ +#define M8260_TMCNTSC_ALR (1<<6) /* Alarm interrupt flag */ +#define M8260_TMCNTSC_SIE (1<<3) /* per second interrupt enable */ +#define M8260_TMCNTSC_ALE (1<<2) /* Alarm interrupt enable */ +#define M8260_TMCNTSC_TCF (1<<1) /* Time count frequency */ +#define M8260_TMCNTSC_TCE (1<<0) /* Time count enable */ + +#define M8260_SIMASK_PC0 (1<<31) +#define M8260_SIMASK_PC1 (1<<30) +#define M8260_SIMASK_PC2 (1<<29) +#define M8260_SIMASK_PC3 (1<<28) +#define M8260_SIMASK_PC4 (1<<27) +#define M8260_SIMASK_PC5 (1<<26) +#define M8260_SIMASK_PC6 (1<<25) +#define M8260_SIMASK_PC7 (1<<24) +#define M8260_SIMASK_PC8 (1<<23) +#define M8260_SIMASK_PC9 (1<<22) +#define M8260_SIMASK_PC10 (1<<21) +#define M8260_SIMASK_PC11 (1<<20) +#define M8260_SIMASK_PC12 (1<<19) +#define M8260_SIMASK_PC13 (1<<18) +#define M8260_SIMASK_PC14 (1<<17) +#define M8260_SIMASK_PC15 (1<<16) +#define M8260_SIMASK_IRQ1 (1<<14) +#define M8260_SIMASK_IRQ2 (1<<13) +#define M8260_SIMASK_IRQ3 (1<<12) +#define M8260_SIMASK_IRQ4 (1<<11) +#define M8260_SIMASK_IRQ5 (1<<10) +#define M8260_SIMASK_IRQ6 (1<<9) +#define M8260_SIMASK_IRQ7 (1<<8) +#define M8260_SIMASK_TMCNT (1<<2) +#define M8260_SIMASK_PIT (1<<1) + +#define M8260_SIMASK_FCC1 (1<<31) +#define M8260_SIMASK_FCC2 (1<<30) +#define M8260_SIMASK_FCC3 (1<<29) +#define M8260_SIMASK_MCC1 (1<<27) +#define M8260_SIMASK_MCC2 (1<<26) +#define M8260_SIMASK_SCC1 (1<<23) +#define M8260_SIMASK_SCC2 (1<<22) +#define M8260_SIMASK_SCC3 (1<<21) +#define M8260_SIMASK_SCC4 (1<<20) +#define M8260_SIMASK_I2C (1<<15) +#define M8260_SIMASK_SPI (1<<14) +#define M8260_SIMASK_RTT (1<<13) +#define M8260_SIMASK_SMC1 (1<<12) +#define M8260_SIMASK_SMC2 (1<<11) +#define M8260_SIMASK_IDMA1 (1<<10) +#define M8260_SIMASK_IDMA2 (1<<9) +#define M8260_SIMASK_IDMA3 (1<<8) +#define M8260_SIMASK_IDMA4 (1<<7) +#define M8260_SIMASK_SDMA (1<<6) +#define M8260_SIMASK_TIMER1 (1<<4) +#define M8260_SIMASK_TIMER2 (1<<3) +#define M8260_SIMASK_TIMER3 (1<<2) +#define M8260_SIMASK_TIMER4 (1<<1) + +#define M8260_SIUMCR_EARB (1<<31) +#define M8260_SIUMCR_EARP0 (0<<28) +#define M8260_SIUMCR_EARP1 (1<<28) +#define M8260_SIUMCR_EARP2 (2<<28) +#define M8260_SIUMCR_EARP3 (3<<28) +#define M8260_SIUMCR_EARP4 (4<<28) +#define M8260_SIUMCR_EARP5 (5<<28) +#define M8260_SIUMCR_EARP6 (6<<28) +#define M8260_SIUMCR_EARP7 (7<<28) +#define M8260_SIUMCR_DSHW (1<<23) +#define M8260_SIUMCR_DBGC0 (0<<21) +#define M8260_SIUMCR_DBGC1 (1<<21) +#define M8260_SIUMCR_DBGC2 (2<<21) +#define M8260_SIUMCR_DBGC3 (3<<21) +#define M8260_SIUMCR_DBPC0 (0<<19) +#define M8260_SIUMCR_DBPC1 (1<<19) +#define M8260_SIUMCR_DBPC2 (2<<19) +#define M8260_SIUMCR_DBPC3 (3<<19) +#define M8260_SIUMCR_FRC (1<<17) +#define M8260_SIUMCR_DLK (1<<16) +#define M8260_SIUMCR_PNCS (1<<15) +#define M8260_SIUMCR_OPAR (1<<14) +#define M8260_SIUMCR_DPC (1<<13) +#define M8260_SIUMCR_MPRE (1<<12) +#define M8260_SIUMCR_MLRC0 (0<<10) +#define M8260_SIUMCR_MLRC1 (1<<10) +#define M8260_SIUMCR_MLRC2 (2<<10) +#define M8260_SIUMCR_MLRC3 (3<<10) +#define M8260_SIUMCR_AEME (1<<9) +#define M8260_SIUMCR_SEME (1<<8) +#define M8260_SIUMCR_BSC (1<<7) +#define M8260_SIUMCR_GB5E (1<<6) +#define M8260_SIUMCR_B2DD (1<<5) +#define M8260_SIUMCR_B3DD (1<<4) + +/* +************************************************************************* +* MPC8260 DUAL-PORT RAM AND REGISTERS * +************************************************************************* +*/ +typedef struct m8260_ { + + /* + * CPM Dual-Port RAM + */ + rtems_unsigned8 dpram1[16384]; /* 0x0000 - 0x3FFF BD/data/ucode */ + rtems_unsigned8 cpm_pad0[16384]; /* 0x4000 - 0x7FFF Reserved */ + + m8260SCCparms_t scc1p; + rtems_unsigned8 pad_scc1[256-sizeof(m8260SCCparms_t)]; + m8260SCCparms_t scc2p; + rtems_unsigned8 pad_scc2[256-sizeof(m8260SCCparms_t)]; + m8260SCCparms_t scc3p; + rtems_unsigned8 pad_scc3[256-sizeof(m8260SCCparms_t)]; + m8260SCCparms_t scc4p; + rtems_unsigned8 pad_scc4[256-sizeof(m8260SCCparms_t)]; + + m8260FCCparms_t fcc1p; + rtems_unsigned8 pad_fcc1[256-sizeof(m8260FCCparms_t)]; + m8260FCCparms_t fcc2p; + rtems_unsigned8 pad_fcc2[256-sizeof(m8260FCCparms_t)]; + m8260FCCparms_t fcc3p; + rtems_unsigned8 pad_fcc3[256-sizeof(m8260FCCparms_t)]; + + rtems_unsigned8 mcc1p[128]; + rtems_unsigned8 pad_mcc1[124]; + rtems_unsigned16 smc1_base; + rtems_unsigned16 idma1_base; + rtems_unsigned8 mcc2p[128]; + rtems_unsigned8 pad_mcc2[124]; + rtems_unsigned16 smc2_base; + rtems_unsigned16 idma2_base; + rtems_unsigned8 pad_spi[252]; + rtems_unsigned16 spi_base; + rtems_unsigned16 idma3_base; + rtems_unsigned8 pad_risc[224]; + rtems_unsigned8 risc_timers[16]; + rtems_unsigned16 rev_num; + rtems_unsigned16 cpm_pad7; + rtems_unsigned32 cpm_pad8; + rtems_unsigned16 rand; + rtems_unsigned16 i2c_base; + rtems_unsigned16 idma4_base; + rtems_unsigned8 cpm_pad9[1282]; + + rtems_unsigned8 cpm_pad1[8192]; /* 0x9000 - 0xAFFF Reserved */ + + m8260SMCparms_t smc1p; + m8260SMCparms_t smc2p; + rtems_unsigned8 dpram3[4096-2*sizeof(m8260SMCparms_t)]; + + rtems_unsigned8 cpm_pad2[16384]; /* 0xC000 - 0xFFFF Reserved */ + + + /* + * General SIU Block + */ + rtems_unsigned32 siumcr; + rtems_unsigned32 sypcr; + rtems_unsigned8 siu_pad0[6]; + rtems_unsigned16 swsr; + rtems_unsigned8 siu_pad1[20]; + rtems_unsigned32 bcr; + rtems_unsigned8 ppc_acr; + rtems_unsigned8 siu_pad4[3]; + rtems_unsigned32 ppc_alrh; + rtems_unsigned32 ppc_alr1; + rtems_unsigned8 lcl_acr; + rtems_unsigned8 siu_pad5[3]; + rtems_unsigned32 lcl_alrh; + rtems_unsigned32 lcl_alr1; + rtems_unsigned32 tescr1; + rtems_unsigned32 tescr2; + rtems_unsigned32 l_tescr1; + rtems_unsigned32 l_tescr2; + rtems_unsigned32 pdtea; + rtems_unsigned8 pdtem; + rtems_unsigned8 siu_pad2[3]; + rtems_unsigned32 ldtea; + rtems_unsigned8 ldtem; + rtems_unsigned8 siu_pad3[163]; + + + /* + * Memory Controller Block + */ + m8260MEMCRegisters_t memc[12]; + rtems_unsigned8 mem_pad0[8]; + rtems_unsigned32 mar; + rtems_unsigned8 mem_pad1[4]; + rtems_unsigned32 mamr; + rtems_unsigned32 mbmr; + rtems_unsigned32 mcmr; + rtems_unsigned32 mdmr; + rtems_unsigned8 mem_pad2[4]; + rtems_unsigned16 mptpr; + rtems_unsigned8 mem_pad5[2]; + rtems_unsigned32 mdr; + rtems_unsigned8 mem_pad3[4]; + rtems_unsigned32 psdmr; + rtems_unsigned32 lsdmr; + rtems_unsigned8 purt; + rtems_unsigned8 mem_pad6[3]; + rtems_unsigned8 psrt; + rtems_unsigned8 mem_pad7[3]; + rtems_unsigned8 lurt; + rtems_unsigned8 mem_pad8[3]; + rtems_unsigned8 lsrt; + rtems_unsigned8 mem_pad9[3]; + rtems_unsigned32 immr; + rtems_unsigned8 mem_pad4[84]; + + + /* + * System integration timers + */ + rtems_unsigned8 sit_pad0[32]; + rtems_unsigned16 tmcntsc; + rtems_unsigned8 sit_pad6[2]; + rtems_unsigned32 tmcnt; + rtems_unsigned32 tmcntsec; + rtems_unsigned32 tmcntal; + rtems_unsigned8 sit_pad2[16]; + rtems_unsigned16 piscr; + rtems_unsigned8 sit_pad5[2]; + rtems_unsigned32 pitc; + rtems_unsigned32 pitr; + rtems_unsigned8 sit_pad3[94]; + rtems_unsigned8 sit_pad4[2390]; + + + /* + * Interrupt Controller + */ + rtems_unsigned16 sicr; + rtems_unsigned8 ict_pad1[2]; + rtems_unsigned32 sivec; + rtems_unsigned32 sipnr_h; + rtems_unsigned32 sipnr_l; + rtems_unsigned32 siprr; + rtems_unsigned32 scprr_h; + rtems_unsigned32 scprr_l; + rtems_unsigned32 simr_h; + rtems_unsigned32 simr_l; + rtems_unsigned32 siexr; + rtems_unsigned8 ict_pad0[88]; + + + /* + * Clocks and Reset + */ + rtems_unsigned32 sccr; + rtems_unsigned8 clr_pad1[4]; + rtems_unsigned32 scmr; + rtems_unsigned8 clr_pad2[4]; + rtems_unsigned32 rsr; + rtems_unsigned32 rmr; + rtems_unsigned8 clr_pad0[104]; + + + /* + * Input/ Output Port + */ + rtems_unsigned32 pdira; + rtems_unsigned32 ppara; + rtems_unsigned32 psora; + rtems_unsigned32 podra; + rtems_unsigned32 pdata; + rtems_unsigned8 iop_pad0[12]; + rtems_unsigned32 pdirb; + rtems_unsigned32 pparb; + rtems_unsigned32 psorb; + rtems_unsigned32 podrb; + rtems_unsigned32 pdatb; + rtems_unsigned8 iop_pad1[12]; + rtems_unsigned32 pdirc; + rtems_unsigned32 pparc; + rtems_unsigned32 psorc; + rtems_unsigned32 podrc; + rtems_unsigned32 pdatc; + rtems_unsigned8 iop_pad2[12]; + rtems_unsigned32 pdird; + rtems_unsigned32 ppard; + rtems_unsigned32 psord; + rtems_unsigned32 podrd; + rtems_unsigned32 pdatd; + rtems_unsigned8 iop_pad3[12]; + + + /* + * CPM Timers + */ + rtems_unsigned8 tgcr1; + rtems_unsigned8 cpt_pad0[3]; + rtems_unsigned8 tgcr2; + rtems_unsigned8 cpt_pad1[11]; + rtems_unsigned16 tmr1; + rtems_unsigned16 tmr2; + rtems_unsigned16 trr1; + rtems_unsigned16 trr2; + rtems_unsigned16 tcr1; + rtems_unsigned16 tcr2; + rtems_unsigned16 tcn1; + rtems_unsigned16 tcn2; + rtems_unsigned16 tmr3; + rtems_unsigned16 tmr4; + rtems_unsigned16 trr3; + rtems_unsigned16 trr4; + rtems_unsigned16 tcr3; + rtems_unsigned16 tcr4; + rtems_unsigned16 tcn3; + rtems_unsigned16 tcn4; + rtems_unsigned16 ter1; + rtems_unsigned16 ter2; + rtems_unsigned16 ter3; + rtems_unsigned16 ter4; + rtems_unsigned8 cpt_pad2[608]; + + + /* + * DMA Block + */ + rtems_unsigned8 sdsr; + rtems_unsigned8 dma_pad0[3]; + rtems_unsigned8 sdmr; + rtems_unsigned8 dma_pad1[3]; + + rtems_unsigned8 idsr1; + rtems_unsigned8 dma_pad2[3]; + rtems_unsigned8 idmr1; + rtems_unsigned8 dma_pad3[3]; + rtems_unsigned8 idsr2; + rtems_unsigned8 dma_pad4[3]; + rtems_unsigned8 idmr2; + rtems_unsigned8 dma_pad5[3]; + rtems_unsigned8 idsr3; + rtems_unsigned8 dma_pad6[3]; + rtems_unsigned8 idmr3; + rtems_unsigned8 dma_pad7[3]; + rtems_unsigned8 idsr4; + rtems_unsigned8 dma_pad8[3]; + rtems_unsigned8 idmr4; + rtems_unsigned8 dma_pad9[707]; + + + /* + * FCC Block + */ + m8260FCCRegisters_t fcc1; + m8260FCCRegisters_t fcc2; + m8260FCCRegisters_t fcc3; + + rtems_unsigned8 fcc_pad0[656]; + + /* + * BRG 5-8 Block + */ + rtems_unsigned32 brgc5; + rtems_unsigned32 brgc6; + rtems_unsigned32 brgc7; + rtems_unsigned32 brgc8; + rtems_unsigned8 brg_pad0[608]; + + + /* + * I2C + */ + rtems_unsigned8 i2mod; + rtems_unsigned8 i2m_pad0[3]; + rtems_unsigned8 i2add; + rtems_unsigned8 i2m_pad1[3]; + rtems_unsigned8 i2brg; + rtems_unsigned8 i2m_pad2[3]; + rtems_unsigned8 i2com; + rtems_unsigned8 i2m_pad3[3]; + rtems_unsigned8 i2cer; + rtems_unsigned8 i2m_pad4[3]; + rtems_unsigned8 i2cmr; + rtems_unsigned8 i2m_pad5[331]; + + + /* + * CPM Block + */ + rtems_unsigned32 cpcr; + rtems_unsigned32 rccr; + rtems_unsigned8 cpm_pad3[14]; + rtems_unsigned16 rter; + rtems_unsigned8 cpm_pad[2]; + rtems_unsigned16 rtmr; + rtems_unsigned16 rtscr; + rtems_unsigned8 cpm_pad4[2]; + rtems_unsigned32 rtsr; + rtems_unsigned8 cpm_pad5[12]; + + + /* + * BRG 1-4 Block + */ + rtems_unsigned32 brgc1; + rtems_unsigned32 brgc2; + rtems_unsigned32 brgc3; + rtems_unsigned32 brgc4; + + + /* + * SCC Block + */ + m8260SCCRegisters_t scc1; + m8260SCCRegisters_t scc2; + m8260SCCRegisters_t scc3; + m8260SCCRegisters_t scc4; + + + /* + * SMC Block + */ + m8260SMCRegisters_t smc1; + m8260SMCRegisters_t smc2; + + + /* + * SPI Block + */ + rtems_unsigned16 spmode; + rtems_unsigned8 spi_pad0[4]; + rtems_unsigned8 spie; + rtems_unsigned8 spi_pad1[3]; + rtems_unsigned8 spim; + rtems_unsigned8 spi_pad2[2]; + rtems_unsigned8 spcom; + rtems_unsigned8 spi_pad3[82]; + + + /* + * CPM Mux Block + */ + rtems_unsigned8 cmxsi1cr; + rtems_unsigned8 cmx_pad0[1]; + rtems_unsigned8 cmxsi2cr; + rtems_unsigned8 cmx_pad1[1]; + rtems_unsigned32 cmxfcr; + rtems_unsigned32 cmxscr; + rtems_unsigned8 cmxsmr; + rtems_unsigned8 cmx_pad2[1]; + rtems_unsigned16 cmxuar; + rtems_unsigned8 cmx_pad3[16]; + + + /* + * SI & MCC Blocks + */ + m8260SIRegisters_t si1; + m8260MCCRegisters_t mcc1; + m8260SIRegisters_t si2; + m8260MCCRegisters_t mcc2; + + rtems_unsigned8 mcc_pad0[1152]; + + /* + * SI1 RAM + */ + rtems_unsigned8 si1txram[512]; + rtems_unsigned8 ram_pad0[512]; + rtems_unsigned8 si1rxram[512]; + rtems_unsigned8 ram_pad1[512]; + + + /* + * SI2 RAM + */ + rtems_unsigned8 si2txram[512]; + rtems_unsigned8 ram_pad2[512]; + rtems_unsigned8 si2rxram[512]; + rtems_unsigned8 ram_pad3[512]; + + +} m8260_t; + +extern volatile m8260_t m8260; +#endif /* ASM */ + +#endif /* __MPC8260_h */ diff --git a/c/src/lib/libcpu/powerpc/mpc8260/mmu/Makefile.am b/c/src/lib/libcpu/powerpc/mpc8260/mmu/Makefile.am new file mode 100644 index 0000000000..0b3a74def9 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/mmu/Makefile.am @@ -0,0 +1,29 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +PGM = ${ARCH}/mmu.rel + +## C sources +C_FILES = mmu.c + +clock_rel_OBJECTS = $(C_FILES:%.c=${ARCH}/%.o) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(top_srcdir)/../../../../../automake/compile.am +include $(top_srcdir)/../../../../../automake/lib.am + +# +# (OPTIONAL) Add local stuff here using += +# + +$(PGM): $(clock_rel_OBJECTS) + $(make-rel) + +all-local: ${ARCH} $(PGM) + +EXTRA_DIST = $(C_FILES) + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c b/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c new file mode 100644 index 0000000000..8f786fe267 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/mmu/mmu.c @@ -0,0 +1,130 @@ +/* + * mmu.c + * + * This file contains routines for initializing + * and manipulating the MMU on the MPC8xx. + * + * Copyright (c) 1999, National Research Council of Canada + * + * Trivially modified for mpc8260 21.3.2001 + * Andy Dachs + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + */ + +#include +#include +#include + +/* + * mmu_init + * + * This routine sets up the virtual memory maps on an MPC8xx. + * The MPC8xx does not support block address translation (BATs) + * and does not have segment registers. Thus, we must set up page + * translation. However, its MMU supports variable size pages + * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task. + * + * The MPC8xx has separate data and instruction 32-entry translation + * lookaside buffers (TLB). By mapping all of DRAM as one huge page, + * we can preload the TLBs and not have to be concerned with taking + * TLB miss exceptions. + * + * We set up the virtual memory map so that virtual address of a + * location is equal to its real address. + */ +void mmu_init( void ) +{ +#if 0 +/* so far we leave mmu uninitialised */ + + register unsigned32 reg1, i; + + /* + * Initialize the TLBs + * + * Instruction address translation and data address translation + * must be disabled during initialization (IR=0, DR=0 in MSR). + * We can assume the MSR has already been set this way. + */ + + /* + * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR) + * GPM [0] 0b0 = PowerPC mode + * PPM [1] 0b0 = Page resolution of protection + * CIDEF [2] 0b0/0b1 = Default cache-inhibit attribute = + * NO for IMMU, YES for DMMU! + * reserved/WTDEF [3] 0b0 = Default write-through attribute = not + * RSV4x [4] 0b0 = 4 entries not reserved + * reserved/TWAM [5] 0b0/0b1 = 4-Kbyte page hardware assist + * PPCS [6] 0b0 = Ignore user/supervisor state + * reserved [7-18] 0x00 + * xTLB_INDX [19-23] 31 = 0x1F + * reserved [24-31] 0x00 + * + * Note: It is important that cache-inhibit be set as the default for the + * data cache when the DMMU is disabled in order to prevent internal memory + * mapped registers from being cached accidentally when address translation + * is turned off at the start of exception processing. + */ + reg1 = M8xx_MI_CTR_ITLB_INDX(31); + _mtspr( M8xx_MI_CTR, reg1 ); + reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31); + _mtspr( M8xx_MD_CTR, reg1 ); + _isync; + + /* + * Invalidate all TLB entries in both TLBs. + * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so + * all 32 entries are invalidated. + */ + __asm__ volatile ("tlbia\n"::); + _isync; + + /* + * Set Current Address Space ID Register (M_CASID). + * Supervisor: CASID = 0 + */ + reg1 = 0; + _mtspr( M8xx_M_CASID, reg1 ); + + /* + * Initialize the MMU Access Protection Registers (MI_AP, MD_AP) + * We ignore the Access Protection Group (APG) mechanism globally + * by setting all of the Mx_AP fields to 0b01 : client access + * permission is defined by page protection bits. + */ + reg1 = 0x55555555; + _mtspr( M8xx_MI_AP, reg1 ); + _mtspr( M8xx_MD_AP, reg1 ); + + /* + * Load both 32-entry TLBs with values from the MMU_TLB_table + * which is defined in the BSP. + * Note the _TLB_Table must have at most 32 entries. This code + * makes no effort to enforce this restriction. + */ + for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) { + reg1 = MMU_TLB_table[i].mmu_epn; + _mtspr( M8xx_MI_EPN, reg1 ); + _mtspr( M8xx_MD_EPN, reg1 ); + reg1 = MMU_TLB_table[i].mmu_twc; + _mtspr( M8xx_MI_TWC, reg1 ); + _mtspr( M8xx_MD_TWC, reg1 ); + reg1 = MMU_TLB_table[i].mmu_rpn; /* RPN must be written last! */ + _mtspr( M8xx_MI_RPN, reg1 ); + _mtspr( M8xx_MD_RPN, reg1 ); + } + + /* + * Turn on address translation by setting MSR[IR] and MSR[DR]. + */ + _CPU_MSR_Value( reg1 ); + reg1 |= PPC_MSR_IR | PPC_MSR_DR; + _CPU_MSR_SET( reg1 ); + +#endif + +} diff --git a/c/src/lib/libcpu/powerpc/mpc8260/timer/Makefile.am b/c/src/lib/libcpu/powerpc/mpc8260/timer/Makefile.am new file mode 100644 index 0000000000..7886c6d3d3 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/timer/Makefile.am @@ -0,0 +1,29 @@ +## +## $Id$ +## + +AUTOMAKE_OPTIONS = foreign 1.4 + +PGM = ${ARCH}/timer.rel + +## C sources +C_FILES = timer.c + +timer_rel_OBJECTS = $(C_FILES:%.c=${ARCH}/%.o) + +include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg +include $(top_srcdir)/../../../../../automake/compile.am +include $(top_srcdir)/../../../../../automake/lib.am + +# +# (OPTIONAL) Add local stuff here using += +# + +$(PGM): $(timer_rel_OBJECTS) + $(make-rel) + +all-local: ${ARCH} $(PGM) + +EXTRA_DIST = $(C_FILES) + +include $(top_srcdir)/../../../../../automake/local.am diff --git a/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c new file mode 100644 index 0000000000..19f7abf075 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc8260/timer/timer.c @@ -0,0 +1,116 @@ +/* timer.c + * + * This file manages the interval timer on the PowerPC MPC860. + * NOTE: This is not the PIT, but rather the RTEMS interval + * timer + * We shall use the bottom 32 bits of the timebase register, + * + * The following was in the 403 version of this file. I don't + * know what it means. JTM 5/19/98 + * NOTE: It is important that the timer start/stop overhead be + * determined when porting or modifying this code. + * + * Author: Andy Dachs + * Surrey Satellite Technlogy Limited + * Modified for MPC8260 + * Derived from c/src/lib/libcpu/powerpc/mpc860/timer/timer.c: + * + * Author: Jay Monkman (jmonkman@frasca.com) + * Copywright (C) 1998 by Frasca International, Inc. + * + * Derived from c/src/lib/libcpu/ppc/ppc403/timer/timer.c: + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libcpu/hppa1_1/timer/timer.c: + * + * COPYRIGHT (c) 1989-1999. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +static volatile rtems_unsigned32 Timer_starting; +static rtems_boolean Timer_driver_Find_average_overhead; + +extern rtems_cpu_table Cpu_table; +#define rtems_cpu_configuration_get_timer_average_overhead() \ + (Cpu_table.timer_average_overhead) + +#define rtems_cpu_configuration_get_timer_least_valid() \ + (Cpu_table.timer_least_valid) + +/* + * This is so small that this code will be reproduced where needed. + */ +static inline rtems_unsigned32 get_itimer(void) +{ + rtems_unsigned32 ret; + + asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */ + + return ret; +} + +void Timer_initialize(void) +{ + /* set interrupt level and enable timebase. This should never */ + /* generate an interrupt however. */ + +/* + m860.tbscr |= M860_TBSCR_TBIRQ(4) | M860_TBSCR_TBE; +*/ + + + Timer_starting = get_itimer(); +} + +int Read_timer(void) +{ + rtems_unsigned32 clicks; + rtems_unsigned32 total; + + clicks = get_itimer(); + + total = clicks - Timer_starting; + + if ( Timer_driver_Find_average_overhead == 1 ) + return total; /* in XXX microsecond units */ + + else { + if ( total < rtems_cpu_configuration_get_timer_least_valid() ) { + return 0; /* below timer resolution */ + } + return (total - rtems_cpu_configuration_get_timer_average_overhead()); + } +} + +rtems_status_code Empty_function(void) +{ + return RTEMS_SUCCESSFUL; +} + +void Set_find_average_overhead(rtems_boolean find_flag) +{ + Timer_driver_Find_average_overhead = find_flag; +} -- cgit v1.2.3