From 05e75a4b050c613201556be9569c0539d6abc203 Mon Sep 17 00:00:00 2001 From: Gedare Bloom Date: Sun, 6 Nov 2011 16:48:36 +0000 Subject: 2011-11-06 gedare@rtems.org * shared/score/interrupt.S: Pass ISR correct pointer to interrupt frame --- c/src/lib/libcpu/sparc64/ChangeLog | 4 ++++ c/src/lib/libcpu/sparc64/shared/score/interrupt.S | 1 + 2 files changed, 5 insertions(+) (limited to 'c') diff --git a/c/src/lib/libcpu/sparc64/ChangeLog b/c/src/lib/libcpu/sparc64/ChangeLog index 3dc7e4ed4e..734d65ae26 100644 --- a/c/src/lib/libcpu/sparc64/ChangeLog +++ b/c/src/lib/libcpu/sparc64/ChangeLog @@ -1,3 +1,7 @@ +2011-11-06 gedare@rtems.org + + * shared/score/interrupt.S: Pass ISR correct pointer to interrupt frame + 2011-02-11 Ralf Corsépius * shared/cache/cache.c: diff --git a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S b/c/src/lib/libcpu/sparc64/shared/score/interrupt.S index a8169025ea..1f666116bb 100644 --- a/c/src/lib/libcpu/sparc64/shared/score/interrupt.S +++ b/c/src/lib/libcpu/sparc64/shared/score/interrupt.S @@ -161,6 +161,7 @@ PUBLIC(_ISR_Handler) mov %o1, %g2 ! get the trap # mov %o5, %g7 ! store the interrupted %sp (preserve) mov %sp, %o1 ! 2nd arg to ISR Handler = address of ISF + add %o1, STACK_BIAS, %o1 ! need to adjust for stack bias, 2nd arg = ISF /* * Increment ISR nest level and Thread dispatch disable level. -- cgit v1.2.3