From 78e529a660ad86c9eb2fac552fbc29c92ce09b58 Mon Sep 17 00:00:00 2001 From: Daniel Ramirez Date: Sun, 22 Dec 2013 13:49:52 -0600 Subject: arm_rtl22xx: added new doxygen --- .../lib/libbsp/arm/rtl22xx/console/lpc22xx_uart.h | 194 +++++++++++++----- c/src/lib/libbsp/arm/rtl22xx/include/bsp.h | 150 ++++++++++---- c/src/lib/libbsp/arm/rtl22xx/include/bsp.h~ | 218 +++++++++++++++++++++ 3 files changed, 479 insertions(+), 83 deletions(-) create mode 100644 c/src/lib/libbsp/arm/rtl22xx/include/bsp.h~ (limited to 'c/src') diff --git a/c/src/lib/libbsp/arm/rtl22xx/console/lpc22xx_uart.h b/c/src/lib/libbsp/arm/rtl22xx/console/lpc22xx_uart.h index 440a318d7e..f6ae249672 100644 --- a/c/src/lib/libbsp/arm/rtl22xx/console/lpc22xx_uart.h +++ b/c/src/lib/libbsp/arm/rtl22xx/console/lpc22xx_uart.h @@ -1,89 +1,187 @@ -/* - * Definitions for LPC22xx/LPC21xx +/** + * @file + * @ingroup rtl22xx_uart + * @brief UART support. */ #ifndef LPC22XX_UART_H #define LPC22XX_UART_H +/** + * @defgroup rtl22xx_uart UART Support + * @ingroup arm_rtl22xx + * @brief UART (Universal Asynchronous Reciever/Transmitter) Support + * @{ + */ + #define FIFODEEP 16 #define BD115200 115200 #define BD38400 38400 #define BD9600 9600 -#define U0_PINSEL (0x00000005) /* PINSEL0 Value for UART0 */ -#define U0_PINMASK (0x0000000F) /* PINSEL0 Mask for UART0 */ -#define U1_PINSEL (0x00050000) /* PINSEL0 Value for UART1 */ -#define U1_PINMASK (0x000F0000) /* PINSEL0 Mask for UART1 */ +/** @brief PINSEL0 Value for UART0 */ +#define U0_PINSEL (0x00000005) +/** @brief PINSEL0 Mask for UART0 */ +#define U0_PINMASK (0x0000000F) +/** @brief PINSEL0 Value for UART1 */ +#define U1_PINSEL (0x00050000) +/** @brief PINSEL0 Mask for UART1 */ +#define U1_PINMASK (0x000F0000) + +/** + * @name Uart line control register bit descriptions + * @{ + */ -/* Uart line control register bit descriptions */ #define LCR_WORDLENTH_BIT 0 #define LCR_STOPBITSEL_BIT 2 #define LCR_PARITYENBALE_BIT 3 #define LCR_PARITYSEL_BIT 4 #define LCR_BREAKCONTROL_BIT 6 #define LCR_DLAB_BIT 7 -// Line Control Register bit definitions -#define ULCR_CHAR_5 (0 << 0) // 5-bit character length -#define ULCR_CHAR_6 (1 << 0) // 6-bit character length -#define ULCR_CHAR_7 (2 << 0) // 7-bit character length -#define ULCR_CHAR_8 (3 << 0) // 8-bit character length -#define ULCR_STOP_0 (0 << 2) // no stop bits -#define ULCR_STOP_1 (1 << 2) // 1 stop bit -#define ULCR_PAR_NO (0 << 3) // No Parity -#define ULCR_PAR_ODD (1 << 3) // Odd Parity -#define ULCR_PAR_EVEN (3 << 3) // Even Parity -#define ULCR_PAR_MARK (5 << 3) // MARK "1" Parity -#define ULCR_PAR_SPACE (7 << 3) // SPACE "0" Paruty -#define ULCR_BREAK_ENABLE (1 << 6) // Output BREAK line condition -#define ULCR_DLAB_ENABLE (1 << 7) // Enable Divisor Latch Access -// Modem Control Register bit definitions -#define UMCR_DTR (1 << 0) // Data Terminal Ready -#define UMCR_RTS (1 << 1) // Request To Send -#define UMCR_LB (1 << 4) // Loopback - -// Line Status Register bit definitions -#define ULSR_RDR (1 << 0) // Receive Data Ready -#define ULSR_OE (1 << 1) // Overrun Error -#define ULSR_PE (1 << 2) // Parity Error -#define ULSR_FE (1 << 3) // Framing Error -#define ULSR_BI (1 << 4) // Break Interrupt -#define ULSR_THRE (1 << 5) // Transmit Holding Register Empty -#define ULSR_TEMT (1 << 6) // Transmitter Empty -#define ULSR_RXFE (1 << 7) // Error in Receive FIFO + +/** @} */ + +/** + * @name Line Control Register bit definitions + * @{ + */ + +/** @brief 5-bit character length */ +#define ULCR_CHAR_5 (0 << 0) +/** @brief 6-bit character length */ +#define ULCR_CHAR_6 (1 << 0) +/** @brief 7-bit character length */ +#define ULCR_CHAR_7 (2 << 0) +/** @brief 8-bit character length */ +#define ULCR_CHAR_8 (3 << 0) +/** @brief no stop bits */ +#define ULCR_STOP_0 (0 << 2) +/** @brief 1 stop bit */ +#define ULCR_STOP_1 (1 << 2) +/** @brief No Parity */ +#define ULCR_PAR_NO (0 << 3) +/** @brief Odd Parity */ +#define ULCR_PAR_ODD (1 << 3) +/** @brief Even Parity */ +#define ULCR_PAR_EVEN (3 << 3) +/** @brief MARK "1" Parity */ +#define ULCR_PAR_MARK (5 << 3) +/** @brief SPACE "0" Paruty */ +#define ULCR_PAR_SPACE (7 << 3) +/** @brief Output BREAK line condition */ +#define ULCR_BREAK_ENABLE (1 << 6) +/** @brief Enable Divisor Latch Access */ +#define ULCR_DLAB_ENABLE (1 << 7) + +/** @} */ + +/** + * @name Modem Control Register bit definitions + * @{ + */ + +/** @brief Data Terminal Ready */ +#define UMCR_DTR (1 << 0) +/** @brief Request To Send */ +#define UMCR_RTS (1 << 1) +/** @brief Loopback */ +#define UMCR_LB (1 << 4) + +/** @} */ + +/** + * @name Line Status Register bit definitions + * @{ + */ + +/** @brief Receive Data Ready */ +#define ULSR_RDR (1 << 0) +/** @brief Overrun Error */ +#define ULSR_OE (1 << 1) +/** @brief Parity Error */ +#define ULSR_PE (1 << 2) +/** @brief Framing Error */ +#define ULSR_FE (1 << 3) +/** @brief Break Interrupt */ +#define ULSR_BI (1 << 4) +/** @brief Transmit Holding Register Empty */ +#define ULSR_THRE (1 << 5) +/** @brief Transmitter Empty */ +#define ULSR_TEMT (1 << 6) +/** @brief Error in Receive FIFO */ +#define ULSR_RXFE (1 << 7) #define ULSR_ERR_MASK 0x1E -// Modem Status Register bit definitions -#define UMSR_DCTS (1 << 0) // Delta Clear To Send -#define UMSR_DDSR (1 << 1) // Delta Data Set Ready -#define UMSR_TERI (1 << 2) // Trailing Edge Ring Indicator -#define UMSR_DDCD (1 << 3) // Delta Data Carrier Detect -#define UMSR_CTS (1 << 4) // Clear To Send -#define UMSR_DSR (1 << 5) // Data Set Ready -#define UMSR_RI (1 << 6) // Ring Indicator -#define UMSR_DCD (1 << 7) // Data Carrier Detect - -/* Uart Interrupt Identification */ +/** @} */ + +/** + * @name Modem Status Register bit definitions + * @{ + */ + +/** @brief Delta Clear To Send */ +#define UMSR_DCTS (1 << 0) +/** @brief Delta Data Set Ready */ +#define UMSR_DDSR (1 << 1) +/** @brief Trailing Edge Ring Indicator */ +#define UMSR_TERI (1 << 2) +/** @brief Delta Data Carrier Detect */ +#define UMSR_DDCD (1 << 3) +/** @brief Clear To Send */ +#define UMSR_CTS (1 << 4) +/** @brief Data Set Ready */ +#define UMSR_DSR (1 << 5) +/** @brief Ring Indicator */ +#define UMSR_RI (1 << 6) +/** @brief Data Carrier Detect */ +#define UMSR_DCD (1 << 7) + +/** @} */ + +/** + * @name Uart Interrupt Identification + * @{ + */ + #define IIR_RSL 0x3 #define IIR_RDA 0x2 #define IIR_CTI 0x6 #define IIR_THRE 0x1 -/* Uart Interrupt Enable Type*/ +/** @} */ + +/** + * @name Uart Interrupt Enable Type + * @{ + */ + #define IER_RBR 0x1 #define IER_THRE 0x2 #define IER_RLS 0x4 -/* Uart Receiver Errors*/ +/** @} */ + +/** + * @name Uart Receiver Errors + * @{ + */ + #define RC_FIFO_OVERRUN_ERR 0x1 #define RC_OVERRUN_ERR 0x2 #define RC_PARITY_ERR 0x4 #define RC_FRAMING_ERR 0x8 #define RC_BREAK_IND 0x10 +/** @} */ + typedef enum { UART0 = 0, UART1 } LPC_UartChanel_t; + +/** @} */ + #endif diff --git a/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h b/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h index 936f93ac6a..06f3e8ef2b 100644 --- a/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h +++ b/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h @@ -1,3 +1,9 @@ +/** + * @file + * @ingroup arm_rtl22xx + * @brief Global BSP definitions. + */ + /* * Philips LPC22XX/LPC21xx BSP header file * @@ -17,6 +23,13 @@ extern "C" { #include #include +/** + * @defgroup arm_rtl22xx RTL22XX Support + * @ingroup bsp_arm + * @brief RTL22XX Support Package + * @{ + */ + #define BSP_SMALL_MEMORY 1 #include @@ -30,39 +43,67 @@ extern "C" { /* cclk=cco/(2*P) */ /* cco = cclk*2*P */ -/* system clk frequecy,<=60Mhz, defined in system configuration */ +/** @brief system clk frequecy,<=60Mhz, defined in system configuration */ #define LPC22xx_Fcclk CONFIG_ARM_CLK /* Fcco 156M~320Mhz*/ -/* system clk frequecy,<=60Mhz, defined in system configuration */ +/** @brief system clk frequecy,<=60Mhz, defined in system configuration */ #define LPC22xx_Fcclk CONFIG_ARM_CLK #define LPC22xx_Fcco LPC22xx_Fcclk * 4 -/*VPB clk frequency,1,1/2,1/4 times of Fcclk */ +/** @brief VPB clk frequency,1,1/2,1/4 times of Fcclk */ #define LPC22xx_Fpclk (LPC22xx_Fcclk /4) *1 -/* Fcclk range: 10MHz ~ MCU allowed frequency */ +/** + * @name Fcclk range: 10MHz ~ MCU allowed frequency + * @{ + */ + #define Fcclk_MIN 10000000L #define Fcclk_MAX 60000000L -/* Fcco range: 156MHz ~ 320MHz */ +/** @} */ + +/** + * @name Fcco range: 156MHz ~ 320MHz + * @{ + */ + #define Fcco_MIN 156000000L #define Fcco_MAX 320000000L +/** @} */ + #define PLLFEED_DATA1 0xAA #define PLLFEED_DATA2 0x55 -/* PLL PLLCON register bit descriptions */ +/** + * @name PLL PLLCON register bit descriptions + * @{ + */ + #define PLLCON_ENABLE_BIT 0 #define PLLCON_CONNECT_BIT 1 -/* PLL PLLSTAT register bit descriptions */ +/** @} */ + +/** + * @name PLL PLLSTAT register bit descriptions + * @{ + */ + #define PLLSTAT_ENABLE_BIT 8 #define PLLSTAT_CONNECT_BIT 9 #define PLLSTAT_LOCK_BIT 10 -/* PM Peripheral Type */ +/** @} */ + +/** + * @name PM Peripheral Type + * @{ + */ + #define PC_TIMER0 0x2 #define PC_TIMER1 0x4 #define PC_UART0 0x8 @@ -72,73 +113,112 @@ extern "C" { #define PC_SPI0 0x100 #define PC_RTC 0x200 -// OSC [Hz] +/** @} */ + +/** @brief OSC [Hz] */ #define FOSC 11059200 -// Core clk [Hz] +/** @brief Core clk [Hz] */ #define FCCLK FOSC<<2 + /** -* help file -*/ -/* System configure, Fosc Fcclk Fcco Fpclk must be defined*/ -#define Fosc 11059200 // osc freq,10MHz~25MHz, - // change to real one if needed -#define Fcclk (Fosc << 2) //system freq 2^n time of Fosc(1~32) <=60MHZ -#define Fcco (Fcclk <<2) //CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz -#define Fpclk (Fcclk >>2) * 1 //VPB freq only(Fcclk / 4) 1~4 + * @name System Configure + * @{ + */ + +/** @brief osc freq,10MHz~25MHz, change to a real one if needed */ +#define Fosc 11059200 +/** @brief system freq 2^n time of Fosc(1~32) <=60MHZ */ +#define Fcclk (Fosc << 2) +/** @brief CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz */ +#define Fcco (Fcclk <<2) +/** @brief VPB freq only(Fcclk / 4) 1~4 */ +#define Fpclk (Fcclk >>2) * 1 /* This was M. That is a BAD BAD public constant. I renamed it to * JOEL_M so it wouldn't conflict with user code. If you can find * a better name, fix this. But nothing I found uses it. */ + +/** @} */ + #define JOEL_M Fcclk / Fosc #define P_min Fcco_MIN / (2*Fcclk) + 1; #define P_max Fcco_MAX / (2*Fcclk); - - #define UART_BPS 115200 -// Time Precision time [us] +/** @brief Time Precision time [us] */ #define TIMER_PRECISION 10 -// I2C Speed [bit/s] +/** @brief I2C Speed [bit/s] */ #define I2CSPEED 20000 // 20 Kbit/s -// Uarts buffers size +/** + * @name Uarts buffers size + * @{ + */ + #define RXBUFSIZE 32 #define TXBUFSIZE 32 -// SPI Speed [bit/s] +/** @} */ + +/** @brief SPI Speed [bit/s] */ #define SPISPEED 1500000 // 1.5 Mbit/s -// SPI EEPROM CS pin (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface) +/** @brief SPI EEPROM CS pin + * + * (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface) + */ #define SPI_CS_PIN P0_13 #define SPI_CS_PIN_FUNC PINSEL0_bit.SPI_CS_PIN -// Flash definition +/** + * @name Flash definition + * @{ + */ + //#define FLASH_SIZE (0x200000-FLASH_BOOT) // Total area of Flash region in words 8 bit -#define FLASH_SIZE (0x80000-FLASH_BOOT) // Total area of Flash region in words 8 bit +/** @brief Total area of Flash region in words 8 bit */ +#define FLASH_SIZE (0x80000-FLASH_BOOT) //#define FLASH_SIZE (0x80000-FLASH_BOOT) // Total area of Flash region in words 8 bit #define FLASH_BEGIN 0x80000000 -#define FLASH_BASE (FLASH_BEGIN+FLASH_BOOT) //First 0x8000 bytes reserved for boot loader etc. +/** @brief First 0x8000 bytes reserved for boot loader etc. */ +#define FLASH_BASE (FLASH_BEGIN+FLASH_BOOT) + +/** @} */ + +/** + * @name SRAM definition + * @{ + */ -// SRAM definition -#define SRAM_SIZE 0x100000 // Total area of Flash region in words 8 bit -#define SRAM_BASE 0x81000000 //First 0x8000 bytes reserved for boot loader etc. +/** @brief Total area of Flash region in words 8 bit */ +#define SRAM_SIZE 0x100000 +/** @brief First 0x8000 bytes reserved for boot loader etc. */ +#define SRAM_BASE 0x81000000 -// CS8900A definition +/** @} */ + +/** @brief CS8900A definition */ #define CS8900A_BASE 0x82000000 -// RTL8019AS definition +/** @brief RTL8019AS definition */ #define RTL8019AS_BASE 0x82000000 struct rtems_bsdnet_ifconfig; int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, int attaching); -/* - * Network driver configuration +/** + * @name Network driver configuration + * @{ */ + #define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" #define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach +/** @} */ + +/** @} */ + #ifdef __cplusplus } #endif diff --git a/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h~ b/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h~ new file mode 100644 index 0000000000..2737be8226 --- /dev/null +++ b/c/src/lib/libbsp/arm/rtl22xx/include/bsp.h~ @@ -0,0 +1,218 @@ +/** + * @file + * @ingroup arm_rtl22xx + * @brief Global BSP definitions. + */ + +/* + * Philips LPC22XX/LPC21xx BSP header file + * + * by Ray,Xu + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. +*/ +#ifndef _BSP_H +#define _BSP_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * @defgroup arm_rtl22xx RTL22XX Support + * @ingroup bsp_arm + * @brief RTL22XX Support Package + * @{ + */ + +#define BSP_SMALL_MEMORY 1 + +#include +#include +#include +#include + +#define BSP_FEATURE_IRQ_EXTENSION + +#define CONFIG_ARM_CLK 60000000L +/* cclk=cco/(2*P) */ +/* cco = cclk*2*P */ + +/** @brief system clk frequecy,<=60Mhz, defined in system configuration */ +#define LPC22xx_Fcclk CONFIG_ARM_CLK + +/* Fcco 156M~320Mhz*/ +/** @brief system clk frequecy,<=60Mhz, defined in system configuration */ +#define LPC22xx_Fcclk CONFIG_ARM_CLK +#define LPC22xx_Fcco LPC22xx_Fcclk * 4 +/** @brief VPB clk frequency,1,1/2,1/4 times of Fcclk */ +#define LPC22xx_Fpclk (LPC22xx_Fcclk /4) *1 + + + +/** + * @name Fcclk range: 10MHz ~ MCU allowed frequency + * @{ + */ + +#define Fcclk_MIN 10000000L +#define Fcclk_MAX 60000000L + +/** @} */ + +/** + * @name Fcco range: 156MHz ~ 320MHz + * @{ + */ + +#define Fcco_MIN 156000000L +#define Fcco_MAX 320000000L + +/** @} */ + +#define PLLFEED_DATA1 0xAA +#define PLLFEED_DATA2 0x55 + +/** + * @name PLL PLLCON register bit descriptions + * @{ + */ + +#define PLLCON_ENABLE_BIT 0 +#define PLLCON_CONNECT_BIT 1 + +/** @} */ + +/** + * @name PLL PLLSTAT register bit descriptions + * @{ + */ + +#define PLLSTAT_ENABLE_BIT 8 +#define PLLSTAT_CONNECT_BIT 9 +#define PLLSTAT_LOCK_BIT 10 + +/** @} */ + +/** + * @name PM Peripheral Type + * @{ + */ + +#define PC_TIMER0 0x2 +#define PC_TIMER1 0x4 +#define PC_UART0 0x8 +#define PC_UART1 0x10 +#define PC_PWM0 0x20 +#define PC_I2C 0x80 +#define PC_SPI0 0x100 +#define PC_RTC 0x200 + +/** @} */ + +/** @brief OSC [Hz] */ +#define FOSC 11059200 +/** @brief Core clk [Hz] */ +#define FCCLK FOSC<<2 + +/** + * @name System Configure + * @{ + */ + +#define Fosc 11059200 /** @brief osc freq,10MHz~25MHz, change to a real one if needed */ +#define Fcclk (Fosc << 2) /** @brief system freq 2^n time of Fosc(1~32) <=60MHZ */ +#define Fcco (Fcclk <<2) /** @brief CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz */ +#define Fpclk (Fcclk >>2) * 1 /** @brief VPB freq only(Fcclk / 4) 1~4 */ +/* This was M. That is a BAD BAD public constant. I renamed it to + * JOEL_M so it wouldn't conflict with user code. If you can find + * a better name, fix this. But nothing I found uses it. + */ + +/** @} */ + +#define JOEL_M Fcclk / Fosc +#define P_min Fcco_MIN / (2*Fcclk) + 1; +#define P_max Fcco_MAX / (2*Fcclk); + +#define UART_BPS 115200 + +/** @brief Time Precision time [us] */ +#define TIMER_PRECISION 10 + +/** @brief I2C Speed [bit/s] */ +#define I2CSPEED 20000 // 20 Kbit/s + +/** + * @name Uarts buffers size + * @{ + */ + +#define RXBUFSIZE 32 +#define TXBUFSIZE 32 + +/** @} */ + +/** @brief SPI Speed [bit/s] */ +#define SPISPEED 1500000 // 1.5 Mbit/s +/** @brief SPI EEPROM CS pin + * + * (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface) + */ +#define SPI_CS_PIN P0_13 +#define SPI_CS_PIN_FUNC PINSEL0_bit.SPI_CS_PIN + +/** + * @name Flash definition + * @{ + */ + +//#define FLASH_SIZE (0x200000-FLASH_BOOT) // Total area of Flash region in words 8 bit +#define FLASH_SIZE (0x80000-FLASH_BOOT) /** @brief Total area of Flash region in words 8 bit */ +//#define FLASH_SIZE (0x80000-FLASH_BOOT) // Total area of Flash region in words 8 bit +#define FLASH_BEGIN 0x80000000 +#define FLASH_BASE (FLASH_BEGIN+FLASH_BOOT) /** @brief First 0x8000 bytes reserved for boot loader etc. */ + +/** @} */ + +/** + * @name SRAM definition + * @{ + */ + +#define SRAM_SIZE 0x100000 /** @brief Total area of Flash region in words 8 bit */ +#define SRAM_BASE 0x81000000 /** @brief First 0x8000 bytes reserved for boot loader etc. */ + +/** @} */ + +/** @brief CS8900A definition */ +#define CS8900A_BASE 0x82000000 +/** @brief RTL8019AS definition */ +#define RTL8019AS_BASE 0x82000000 + +struct rtems_bsdnet_ifconfig; +int cs8900_driver_attach (struct rtems_bsdnet_ifconfig *config, + int attaching); + +/** + * @name Network driver configuration + * @{ + */ + +#define RTEMS_BSP_NETWORK_DRIVER_NAME "eth0" +#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach + +/** @} */ + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif /* _BSP_H */ -- cgit v1.2.3