From 6094c1a4d9d34a1c9d70d8b5237fc0218b4a4ef8 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 11 Sep 2006 21:46:47 +0000 Subject: *** empty log message *** --- c/src/lib/libbsp/i386/shared/comm/i386_io.h | 26 +++-- c/src/libchip/network/i82586.c | 2 +- c/src/libchip/network/i82586reg.h | 68 +++++++------ c/src/libchip/network/if_dc.c | 30 +++--- c/src/libchip/network/smc91111.c | 2 +- c/src/libchip/network/smc91111.h | 144 ++++++++++++++-------------- 6 files changed, 141 insertions(+), 131 deletions(-) (limited to 'c/src') diff --git a/c/src/lib/libbsp/i386/shared/comm/i386_io.h b/c/src/lib/libbsp/i386/shared/comm/i386_io.h index a59392dcac..cd81c66096 100644 --- a/c/src/lib/libbsp/i386/shared/comm/i386_io.h +++ b/c/src/lib/libbsp/i386/shared/comm/i386_io.h @@ -1,18 +1,16 @@ /* -///////////////////////////////////////////////////////////////////////////// -// $Header$ -// -// Copyright (c) 2000 - Rosimildo da Silva. All Rights Reserved. -// -// MODULE DESCRIPTION: -// -// IO Functions for the PC platform equivalent to DOS/Linux. They make -// eaiser the porting of code from these platforms. -// -// by: Rosimildo da Silva: rdasilva@connecttel.com -// -///////////////////////////////////////////////////////////////////////////// -*/ + * $Id$ + * + * Copyright (c) 2000 - Rosimildo da Silva. All Rights Reserved. + * + * MODULE DESCRIPTION: + * + * IO Functions for the PC platform equivalent to DOS/Linux. They make + * eaiser the porting of code from these platforms. + * + * by: Rosimildo da Silva: rdasilva@connecttel.com + * + */ #ifndef i386_io_h__ #define i386_io_h__ diff --git a/c/src/libchip/network/i82586.c b/c/src/libchip/network/i82586.c index 38f6f8abf1..e97c7f6768 100644 --- a/c/src/libchip/network/i82586.c +++ b/c/src/libchip/network/i82586.c @@ -305,7 +305,7 @@ i82586_attach(struct rtems_bsdnet_ifconfig *config, int attaching) ifp = &sc->arpcom.ac_if; #if I82586_DEBUG - sc->sc_debug = 0; //IED_TINT | IED_XMIT; + sc->sc_debug = 0; /*IED_TINT | IED_XMIT; */ #endif if (attaching) diff --git a/c/src/libchip/network/i82586reg.h b/c/src/libchip/network/i82586reg.h index 6ee381b091..e093aff68f 100644 --- a/c/src/libchip/network/i82586reg.h +++ b/c/src/libchip/network/i82586reg.h @@ -84,17 +84,18 @@ */ +#if 0 /* * This is the master configuration block. * It tells the hardware where all the rest of the stuff is. - *- + */ struct __ie_sys_conf_ptr { - u_int16_t mbz; // must be zero - u_int8_t ie_bus_use; // true if 8-bit only - u_int8_t mbz2[5]; // must be zero - u_int32_t ie_iscp_ptr; // 24-bit physaddr of ISCP + u_int16_t mbz; /* must be zero */ + u_int8_t ie_bus_use; /* true if 8-bit only */ + u_int8_t mbz2[5]; /* must be zero */ + u_int32_t ie_iscp_ptr; /* 24-bit physaddr of ISCP */ }; - */ +#endif #define IE_SCP_SZ 12 #define IE_SCP_BUS_USE(base) ((base) + 2) #define IE_SCP_ISCP(base) ((base) + 8) @@ -105,26 +106,28 @@ struct __ie_sys_conf_ptr { */ #define IE_SCP_ADDR 0xfffff4 +#if 0 /* * The tells the hardware where all the rest of the stuff is, too. * FIXME: some of these should be re-commented after we figure out their * REAL function. - *- + */ struct __ie_int_sys_conf_ptr { u_int8_t ie_busy; // zeroed after init u_int8_t mbz; u_int16_t ie_scb_offset; // 16-bit physaddr of next struct caddr_t ie_base; // 24-bit physaddr for all 16-bit vars }; - */ +#endif #define IE_ISCP_SZ 8 #define IE_ISCP_BUSY(base) ((base) + 0) #define IE_ISCP_SCB(base) ((base) + 2) #define IE_ISCP_BASE(base) ((base) + 4) +#if 0 /* * This FINALLY tells the hardware what to do and where to put it. - *- + */ struct __ie_sys_ctl_block { u_int16_t ie_status; // status word u_int16_t ie_command; // command word @@ -135,7 +138,7 @@ struct __ie_sys_ctl_block { u_int16_t ie_err_resource; // Resource errors u_int16_t ie_err_overrun; // Overrun errors }; - */ +#endif #define IE_SCB_SZ 16 #define IE_SCB_STATUS(base) ((base) + 0) #define IE_SCB_CMD(base) ((base) + 2) @@ -186,9 +189,10 @@ struct __ie_sys_ctl_block { #define IE_RUS_NOSPACE 0x0020 /* receiver has no resources */ #define IE_RUS_READY 0x0040 /* receiver is ready */ +#if 0 /* * This is filled in partially by the chip, partially by us. - *- + */ struct __ie_recv_frame_desc { u_int16_t ie_fd_status; // status for this frame u_int16_t ie_fd_last; // end of frame list flag @@ -199,7 +203,7 @@ struct __ie_recv_frame_desc { u_int16_t ie_length; // 802 length/Ether type u_short mbz; // must be zero }; - */ +#endif #define IE_RFRAME_SZ 24 #define IE_RFRAME_ADDR(base,i) ((base) + (i) * IE_RFRAME_SZ) #define IE_RFRAME_STATUS(b,i) (IE_RFRAME_ADDR(b,i) + 0) @@ -229,9 +233,10 @@ struct __ie_recv_frame_desc { #define IE_FD_STATUSBITS \ "\20\20COMPLT\17BUSY\16OK\14CRC\13ALGN\12RNR\11OVR\10SHORT\7NOEOF" +#if 0 /* * linked list of buffers... - *- + */ struct __ie_recv_buf_desc { u_int16_t ie_rbd_status; // status for this buffer u_int16_t ie_rbd_next; // 16-pointer to next RBD @@ -239,7 +244,7 @@ struct __ie_recv_buf_desc { u_int16_t ie_rbd_length; // length of the buffer u_int16_t mbz; // must be zero }; - */ +#endif #define IE_RBD_SZ 12 #define IE_RBD_ADDR(base,i) ((base) + (i) * IE_RBD_SZ) #define IE_RBD_STATUS(b,i) (IE_RBD_ADDR(b,i) + 0) @@ -256,15 +261,16 @@ struct __ie_recv_buf_desc { #define IE_RBD_EOL 0x8000 /* last buffer */ +#if 0 /* * All commands share this in common. - *- + */ struct __ie_cmd_common { u_int16_t ie_cmd_status; // status of this command u_int16_t ie_cmd_cmd; // command word u_int16_t ie_cmd_link; // link to next command }; - */ +#endif #define IE_CMD_COMMON_SZ 6 #define IE_CMD_COMMON_STATUS(base) ((base) + 0) #define IE_CMD_COMMON_CMD(base) ((base) + 2) @@ -298,9 +304,10 @@ struct __ie_cmd_common { #define IE_CMD_NOP_LINK(b,i) (IE_CMD_NOP_ADDR(b,i) + 4) +#if 0 /* * This is the command to transmit a frame. - *- + */ struct __ie_xmit_cmd { struct __ie_cmd_common com; // common part #define __ie_xmit_status com.ie_cmd_status @@ -309,7 +316,7 @@ struct __ie_xmit_cmd { struct __ie_en_addr ie_xmit_addr; // destination address u_int16_t ie_xmit_length; // 802.3 length/Ether type field }; - */ +#endif #define IE_CMD_XMIT_SZ (IE_CMD_COMMON_SZ + 10) #define IE_CMD_XMIT_ADDR(base,i) ((base) + (i) * IE_CMD_XMIT_SZ) #define IE_CMD_XMIT_STATUS(b,i) \ @@ -334,15 +341,16 @@ struct __ie_xmit_cmd { #define IE_XS_NOCARRIER 0x0400 /* No Carrier */ #define IE_XS_LATECOLL 0x0800 /* Late collision */ +#if 0 /* * This is a buffer descriptor for a frame to be transmitted. - *- + */ struct __ie_xmit_buf { u_int16_t ie_xmit_flags; // see below u_int16_t ie_xmit_next; // 16-pointer to next desc caddr_t ie_xmit_buf; // 24-pointer to the actual buffer }; - */ +#endif #define IE_XBD_SZ 8 #define IE_XBD_ADDR(base,i) ((base) + (i) * IE_XBD_SZ) #define IE_XBD_FLAGS(b,i) (IE_XBD_ADDR(b,i) + 0) @@ -354,9 +362,10 @@ struct __ie_xmit_buf { is actually the length. */ +#if 0 /* * Multicast setup command. - *- + */ struct __ie_mcast_cmd { struct __ie_cmd_common com; // common part #define ie_mcast_status com.ie_cmd_status @@ -365,20 +374,21 @@ struct __ie_mcast_cmd { u_short ie_mcast_bytes; struct __ie_en_addr ie_mcast_addrs[IE_MAXMCAST + 1];// space for them }; - */ +#endif #define IE_CMD_MCAST_SZ (IE_CMD_COMMON_SZ + 2 /* + XXX */) #define IE_CMD_MCAST_BYTES(base) ((base) + IE_CMD_COMMON_SZ + 0) #define IE_CMD_MCAST_MADDR(base) ((base) + IE_CMD_COMMON_SZ + 2) +#if 0 /* * Time Domain Reflectometer command. - *- + */ struct __ie_tdr_cmd { struct __ie_cmd_common com; // common part #define ie_tdr_status com.ie_cmd_status u_short ie_tdr_time; // error bits and time }; - */ +#endif #define IE_CMD_TDR_SZ (IE_CMD_COMMON_SZ + 2) #define IE_CMD_TDR_TIME(base) ((base) + IE_CMD_COMMON_SZ + 0) @@ -388,21 +398,23 @@ struct __ie_tdr_cmd { #define IE_TDR_SHORT 0x1000 /* TDR detected a short circuit */ #define IE_TDR_TIME 0x07ff /* mask for reflection time */ +#if 0 /* * Initial Address Setup command - *- + */ struct __ie_iasetup_cmd { struct __ie_cmd_common com; #define ie_iasetup_status com.ie_cmd_status struct __ie_en_addr ie_address; }; - */ +#endif #define IE_CMD_IAS_SZ (IE_CMD_COMMON_SZ + 6) #define IE_CMD_IAS_EADDR(base) ((base) + IE_CMD_COMMON_SZ + 0) +#if 0 /* * Configuration command - *- + */ struct __ie_config_cmd { struct __ie_cmd_common com; // common part #define ie_config_status com.ie_cmd_status @@ -420,7 +432,7 @@ struct __ie_config_cmd { u_int8_t ie_min_len; // min frame length (0x40) u_int8_t ie_junk; // stuff for 82596 (0xff) }; - */ +#endif #define IE_CMD_CFG_SZ (IE_CMD_COMMON_SZ + 12) #define IE_CMD_CFG_CNT(base) ((base) + IE_CMD_COMMON_SZ + 0) #define IE_CMD_CFG_FIFO(base) ((base) + IE_CMD_COMMON_SZ + 1) diff --git a/c/src/libchip/network/if_dc.c b/c/src/libchip/network/if_dc.c index 13c3ef2502..649e5da1b0 100644 --- a/c/src/libchip/network/if_dc.c +++ b/c/src/libchip/network/if_dc.c @@ -137,8 +137,8 @@ #include /* moved to cpukit/include/rtems in CVS current ! */ -//#include "if_media.h" -//#include "pci.h" +/*#include "if_media.h" */ +/*#include "pci.h" */ #include #include /* @@ -1615,7 +1615,7 @@ struct dc_type *dc_devtype( int unitnum ) (unitnum - 1), &t->dc_bus, &t->dc_dev, &t->dc_fun); if (rc == PCIB_ERR_SUCCESS) { /* Check the PCI revision */ - //pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev); + /*pcib_conf_read32(t->dc_devsig, DC_PCI_CFRV, &rev); */ pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ DC_PCI_CFRV, &rev); rev &= 0xFF; @@ -1961,17 +1961,17 @@ rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) /* * Map control/status registers. */ - //sig = sc->dc_info->dc_devsig; + /*sig = sc->dc_info->dc_devsig; */ pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ PCI_COMMAND, &command); - //pcib_conf_read32(sig, PCI_COMMAND, &command); + /*pcib_conf_read32(sig, PCI_COMMAND, &command); */ command |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ PCI_COMMAND, command); - //pcib_conf_write32(sig, PCI_COMMAND, command); + /*pcib_conf_write32(sig, PCI_COMMAND, command); */ pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ PCI_COMMAND, &command); - //pcib_conf_read32(sig, PCI_COMMAND, &command); + /*pcib_conf_read32(sig, PCI_COMMAND, &command); */ #ifdef DC_USEIOSPACE if (!(command & PCI_COMMAND_IO)) { @@ -2002,14 +2002,14 @@ rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) #endif /* sc->membase is the address of the card's CSRs !!! */ - //pcib_conf_read32(sig, DC_PCI_CFBMA, &value); + /*pcib_conf_read32(sig, DC_PCI_CFBMA, &value); */ pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ DC_PCI_CFBMA, &value); sc->membase = value; /* Allocate interrupt */ memset(&sc->irqInfo, 0, sizeof(rtems_irq_connect_data)); - //pcib_conf_read32(sig, DC_PCI_CFIT, &value); + /*pcib_conf_read32(sig, DC_PCI_CFIT, &value); */ pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ DC_PCI_CFIT, &value); @@ -2057,7 +2057,7 @@ rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) /* Need this info to decide on a chip type. sc->dc_info = dc_devtype(dev); */ - //pcib_conf_read32(sig, DC_PCI_CFRV, &revision); + /*pcib_conf_read32(sig, DC_PCI_CFRV, &revision); */ pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ DC_PCI_CFRV, &revision); revision &= 0x000000FF; @@ -2082,12 +2082,12 @@ rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) sc->dc_flags |= DC_REDUCED_MII_POLL|DC_TX_STORENFWD; sc->dc_pmode = DC_PMODE_MII; /* Increase the latency timer value. */ - //pcib_conf_read32(sig, DC_PCI_CFLT, &command); + /*pcib_conf_read32(sig, DC_PCI_CFLT, &command); */ pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ DC_PCI_CFLT, &command); command &= 0xFFFF00FF; command |= 0x00008000; - //pcib_conf_write32(sig, DC_PCI_CFLT, command); + /*pcib_conf_write32(sig, DC_PCI_CFLT, command); */ pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ DC_PCI_CFLT, command); break; @@ -2176,7 +2176,7 @@ rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) sc->dc_cachesize = 0; } else { - //pcib_conf_read32(sig, DC_PCI_CFLT, &value); + /*pcib_conf_read32(sig, DC_PCI_CFLT, &value); */ pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ DC_PCI_CFLT, &value); sc->dc_cachesize = (u_int8_t)(value & 0xFF); @@ -2187,11 +2187,11 @@ rtems_dc_driver_attach(struct rtems_bsdnet_ifconfig *config, int attaching) /* Take 21143 out of snooze mode */ if (DC_IS_INTEL(sc)) { - //pcib_conf_read32(sig, DC_PCI_CFDD, &command); + /*pcib_conf_read32(sig, DC_PCI_CFDD, &command); */ pci_read_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ DC_PCI_CFDD, &command); command &= ~(DC_CFDD_SNOOZE_MODE|DC_CFDD_SLEEP_MODE); - //pcib_conf_write32(sig, DC_PCI_CFDD, command); + /*pcib_conf_write32(sig, DC_PCI_CFDD, command); */ pci_write_config_dword(t->dc_bus,t->dc_dev,t->dc_fun,\ DC_PCI_CFDD, command); } diff --git a/c/src/libchip/network/smc91111.c b/c/src/libchip/network/smc91111.c index 8cbe3c4544..767ca3fc93 100644 --- a/c/src/libchip/network/smc91111.c +++ b/c/src/libchip/network/smc91111.c @@ -105,7 +105,7 @@ rtems_isr lan91cxx_interrupt_handler(rtems_vector_number v) if (0 == event) return; - /*put_reg(cpd, LAN91CXX_INTERRUPT, irq ); *//* ack interrupts */ + /*put_reg(cpd, LAN91CXX_INTERRUPT, irq ); */ /* ack interrupts */ if (event & LAN91CXX_INTERRUPT_ERCV_INT) { db_printf("Early receive interrupt"); diff --git a/c/src/libchip/network/smc91111.h b/c/src/libchip/network/smc91111.h index 0201acd3d6..7cf047e42c 100644 --- a/c/src/libchip/network/smc91111.h +++ b/c/src/libchip/network/smc91111.h @@ -195,41 +195,41 @@ #define LAN91CXX_PHY_CTRL_LPBK (1 << 14) #define LAN91CXX_PHY_CTRL_RST (1 << 15) -// PHY Configuration Register 1 -#define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled -#define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled -#define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down -#define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler -#define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable -#define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled -#define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm) -#define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db -#define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust +/* PHY Configuration Register 1 */ +#define PHY_CFG1_LNKDIS 0x8000 /* 1=Rx Link Detect Function disabled */ +#define PHY_CFG1_XMTDIS 0x4000 /* 1=TP Transmitter Disabled */ +#define PHY_CFG1_XMTPDN 0x2000 /* 1=TP Transmitter Powered Down */ +#define PHY_CFG1_BYPSCR 0x0400 /* 1=Bypass scrambler/descrambler */ +#define PHY_CFG1_UNSCDS 0x0200 /* 1=Unscramble Idle Reception Disable */ +#define PHY_CFG1_EQLZR 0x0100 /* 1=Rx Equalizer Disabled */ +#define PHY_CFG1_CABLE 0x0080 /* 1=STP(150ohm), 0=UTP(100ohm) */ +#define PHY_CFG1_RLVL0 0x0040 /* 1=Rx Squelch level reduced by 4.5db */ +#define PHY_CFG1_TLVL_SHIFT 2 /* Transmit Output Level Adjust */ #define PHY_CFG1_TLVL_MASK 0x003C -#define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time +#define PHY_CFG1_TRF_MASK 0x0003 /* Transmitter Rise/Fall time */ -// PHY Configuration Register 2 +/* PHY Configuration Register 2 */ #define PHY_CFG2_REG 0x11 -#define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled -#define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled -#define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt) -#define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo - -// PHY Status Output (and Interrupt status) Register -#define PHY_INT_REG 0x12 // Status Output (Interrupt Status) -#define PHY_INT_INT 0x8000 // 1=bits have changed since last read -#define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected -#define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync -#define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx -#define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx -#define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx -#define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected -#define PHY_INT_JAB 0x0100 // 1=Jabber detected -#define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode -#define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex - -// PHY Interrupt/Status Mask Register -#define PHY_MASK_REG 0x13 // Interrupt Mask +#define PHY_CFG2_APOLDIS 0x0020 /* 1=Auto Polarity Correction disabled */ +#define PHY_CFG2_JABDIS 0x0010 /* 1=Jabber disabled */ +#define PHY_CFG2_MREG 0x0008 /* 1=Multiple register access (MII mgt) */ +#define PHY_CFG2_INTMDIO 0x0004 /* 1=Interrupt signaled with MDIO pulseo */ + +/* PHY Status Output (and Interrupt status) Register */ +#define PHY_INT_REG 0x12 /* Status Output (Interrupt Status) */ +#define PHY_INT_INT 0x8000 /* 1=bits have changed since last read */ +#define PHY_INT_LNKFAIL 0x4000 /* 1=Link Not detected */ +#define PHY_INT_LOSSSYNC 0x2000 /* 1=Descrambler has lost sync */ +#define PHY_INT_CWRD 0x1000 /* 1=Invalid 4B5B code detected on rx */ +#define PHY_INT_SSD 0x0800 /* 1=No Start Of Stream detected on rx */ +#define PHY_INT_ESD 0x0400 /* 1=No End Of Stream detected on rx */ +#define PHY_INT_RPOL 0x0200 /* 1=Reverse Polarity detected */ +#define PHY_INT_JAB 0x0100 /* 1=Jabber detected */ +#define PHY_INT_SPDDET 0x0080 /* 1=100Base-TX mode, 0=10Base-T mode */ +#define PHY_INT_DPLXDET 0x0040 /* 1=Device in Full Duplex */ + +/* PHY Interrupt/Status Mask Register */ +#define PHY_MASK_REG 0x13 /* Interrupt Mask */ #define LAN91CXX_RPCR_LEDA_LINK (0 << 2) #define LAN91CXX_RPCR_LEDA_TXRX (4 << 2) @@ -243,49 +243,49 @@ #define LAN91CXX_RPCR_DPLX (1 << 12) #define LAN91CXX_RPCR_SPEED (1 << 13) -// PHY Control Register +/* PHY Control Register */ #define PHY_CNTL_REG 0x00 -#define PHY_CNTL_RST 0x8000 // 1=PHY Reset -#define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback -#define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs -#define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation -#define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode -#define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled -#define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate -#define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex -#define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test - -// PHY Status Register +#define PHY_CNTL_RST 0x8000 /* 1=PHY Reset */ +#define PHY_CNTL_LPBK 0x4000 /* 1=PHY Loopback */ +#define PHY_CNTL_SPEED 0x2000 /* 1=100Mbps, 0=10Mpbs */ +#define PHY_CNTL_ANEG_EN 0x1000 /* 1=Enable Auto negotiation */ +#define PHY_CNTL_PDN 0x0800 /* 1=PHY Power Down mode */ +#define PHY_CNTL_MII_DIS 0x0400 /* 1=MII 4 bit interface disabled */ +#define PHY_CNTL_ANEG_RST 0x0200 /* 1=Reset Auto negotiate */ +#define PHY_CNTL_DPLX 0x0100 /* 1=Full Duplex, 0=Half Duplex */ +#define PHY_CNTL_COLTST 0x0080 /* 1= MII Colision Test */ + +/* PHY Status Register */ #define PHY_STAT_REG 0x01 -#define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable -#define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable -#define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable -#define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable -#define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable -#define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble -#define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed -#define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected -#define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable -#define PHY_STAT_LINK 0x0004 // 1=valid link -#define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition -#define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented -#define PHY_STAT_RESERVED 0x0780 // Reserved bits mask. - -// PHY Identifier Registers -#define PHY_ID1_REG 0x02 // PHY Identifier 1 -#define PHY_ID2_REG 0x03 // PHY Identifier 2 - -// PHY Auto-Negotiation Advertisement Register +#define PHY_STAT_CAP_T4 0x8000 /* 1=100Base-T4 capable */ +#define PHY_STAT_CAP_TXF 0x4000 /* 1=100Base-X full duplex capable */ +#define PHY_STAT_CAP_TXH 0x2000 /* 1=100Base-X half duplex capable */ +#define PHY_STAT_CAP_TF 0x1000 /* 1=10Mbps full duplex capable */ +#define PHY_STAT_CAP_TH 0x0800 /* 1=10Mbps half duplex capable */ +#define PHY_STAT_CAP_SUPR 0x0040 /* 1=recv mgmt frames with not preamble */ +#define PHY_STAT_ANEG_ACK 0x0020 /* 1=ANEG has completed */ +#define PHY_STAT_REM_FLT 0x0010 /* 1=Remote Fault detected */ +#define PHY_STAT_CAP_ANEG 0x0008 /* 1=Auto negotiate capable */ +#define PHY_STAT_LINK 0x0004 /* 1=valid link */ +#define PHY_STAT_JAB 0x0002 /* 1=10Mbps jabber condition */ +#define PHY_STAT_EXREG 0x0001 /* 1=extended registers implemented */ +#define PHY_STAT_RESERVED 0x0780 /* Reserved bits mask. */ + +/* PHY Identifier Registers */ +#define PHY_ID1_REG 0x02 /* PHY Identifier 1 */ +#define PHY_ID2_REG 0x03 /* PHY Identifier 2 */ + +/* PHY Auto-Negotiation Advertisement Register */ #define PHY_AD_REG 0x04 -#define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page -#define PHY_AD_ACK 0x4000 // 1=got link code word from remote -#define PHY_AD_RF 0x2000 // 1=advertise remote fault -#define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4 -#define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX -#define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX -#define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX -#define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX -#define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA +#define PHY_AD_NP 0x8000 /* 1=PHY requests exchange of Next Page */ +#define PHY_AD_ACK 0x4000 /* 1=got link code word from remote */ +#define PHY_AD_RF 0x2000 /* 1=advertise remote fault */ +#define PHY_AD_T4 0x0200 /* 1=PHY is capable of 100Base-T4 */ +#define PHY_AD_TX_FDX 0x0100 /* 1=PHY is capable of 100Base-TX FDPLX */ +#define PHY_AD_TX_HDX 0x0080 /* 1=PHY is capable of 100Base-TX HDPLX */ +#define PHY_AD_10_FDX 0x0040 /* 1=PHY is capable of 10Base-T FDPLX */ +#define PHY_AD_10_HDX 0x0020 /* 1=PHY is capable of 10Base-T HDPLX */ +#define PHY_AD_CSMA 0x0001 /* 1=PHY is capable of 802.3 CMSA */ static int debugflag_out = 0; -- cgit v1.2.3