From 5e77d12951fa5ce199fecebd56650558313c8aad Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 14 Jun 2000 20:32:44 +0000 Subject: Patch from John Cotton to correct cache routine naming to follow RTEMS package/object.method rule. This patch also eliminated calls to the obsolete routine m68k_enable_caching. --- c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c | 2 +- c/src/lib/libbsp/m68k/idp/startup/bspstart.c | 2 +- c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c | 2 +- c/src/lib/libbsp/m68k/mvme147/startup/bspstart.c | 2 +- c/src/lib/libbsp/m68k/mvme147s/startup/bspstart.c | 2 +- c/src/lib/libbsp/powerpc/mbx8xx/network/network.c | 8 +- c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c | 4 +- c/src/lib/libcpu/i386/cache.c | 43 +++---- c/src/lib/libcpu/i386/cache_.h | 4 +- c/src/lib/libcpu/i386/page.c | 4 +- c/src/lib/libcpu/m68k/shared/cache/cache.c | 56 ++++----- c/src/lib/libcpu/m68k/shared/cache/cache_.h | 12 +- .../mpc8xx/console-generic/console-generic.c | 16 +-- c/src/lib/libcpu/powerpc/shared/src/cache.c | 36 +++--- c/src/lib/libcpu/powerpc/shared/src/cache_.h | 8 +- c/src/lib/libcpu/shared/include/cache.h | 32 +++--- c/src/lib/libcpu/shared/src/cache_aligned_malloc.c | 6 +- c/src/lib/libcpu/shared/src/cache_manager.c | 125 +++++++++++---------- 18 files changed, 177 insertions(+), 187 deletions(-) (limited to 'c/src') diff --git a/c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c b/c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c index 8f4b3118b6..092f0ec44d 100644 --- a/c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/dmv152/startup/bspstart.c @@ -84,7 +84,7 @@ void bsp_start( void ) * yet been supported on this target. */ - m68k_enable_caching(); + rtems_cache_enable_instruction(); /* * we only use a hook to get the C library initialized. diff --git a/c/src/lib/libbsp/m68k/idp/startup/bspstart.c b/c/src/lib/libbsp/m68k/idp/startup/bspstart.c index 867090700b..b8a894aed6 100644 --- a/c/src/lib/libbsp/m68k/idp/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/idp/startup/bspstart.c @@ -90,7 +90,7 @@ void bsp_start( void ) m68k_set_vbr( &M68Kvec ); - m68k_enable_caching(); + rtems_cache_enable_instruction(); /* * we only use a hook to get the C library initialized. diff --git a/c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c b/c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c index 9818739c0f..3f85c637a4 100644 --- a/c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/mvme136/startup/bspstart.c @@ -73,7 +73,7 @@ void bsp_start( void ) (*(rtems_unsigned8 *)0xfffb0067) = 0x7f; /* make VME access round-robin */ - m68k_enable_caching(); + rtems_cache_enable_instruction(); /* * we only use a hook to get the C library initialized. diff --git a/c/src/lib/libbsp/m68k/mvme147/startup/bspstart.c b/c/src/lib/libbsp/m68k/mvme147/startup/bspstart.c index f1b0dd3bb3..2b48e7b985 100644 --- a/c/src/lib/libbsp/m68k/mvme147/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/mvme147/startup/bspstart.c @@ -79,7 +79,7 @@ void bsp_start( void ) (*(rtems_unsigned8 *)0xfffe2001) = 0x08; /* make VME access round-robin */ - m68k_enable_caching(); + rtems_cache_enable_instruction(); /* * we only use a hook to get the C library initialized. diff --git a/c/src/lib/libbsp/m68k/mvme147s/startup/bspstart.c b/c/src/lib/libbsp/m68k/mvme147s/startup/bspstart.c index 9306768e5c..26b66b6d00 100644 --- a/c/src/lib/libbsp/m68k/mvme147s/startup/bspstart.c +++ b/c/src/lib/libbsp/m68k/mvme147s/startup/bspstart.c @@ -139,7 +139,7 @@ void bsp_start( void ) vme_lcsr->master_configuration = 1; /* Disable D32 transfers : they don't work on my VMEbus rack */ - m68k_enable_caching(); + rtems_cache_enable_instruction(); /* * we only use a hook to get the C library initialized. diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c b/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c index aaa477282f..431737639b 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/network/network.c @@ -746,7 +746,7 @@ scc_rxDaemon (void *arg) /* * Invalidate the buffer for this descriptor */ - rtems_invalidate_multiple_data_cache_lines(rxBd->buffer, rxBd->length); + rtems_cache_invalidate_multiple_data_lines(rxBd->buffer, rxBd->length); m = sc->rxMbuf[rxBdIndex]; m->m_len = m->m_pkthdr.len = rxBd->length - @@ -882,7 +882,7 @@ fec_rxDaemon (void *arg) /* * Invalidate the buffer for this descriptor */ - rtems_invalidate_multiple_data_cache_lines(rxBd->buffer, rxBd->length); + rtems_cache_invalidate_multiple_data_lines(rxBd->buffer, rxBd->length); m = sc->rxMbuf[rxBdIndex]; m->m_len = m->m_pkthdr.len = rxBd->length - @@ -1022,7 +1022,7 @@ scc_sendpacket (struct ifnet *ifp, struct mbuf *m) /* * Flush the buffer for this descriptor */ - rtems_flush_multiple_data_cache_lines(txBd->buffer, txBd->length); + rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length); sc->txMbuf[sc->txBdHead] = m; nAdded++; @@ -1150,7 +1150,7 @@ fec_sendpacket (struct ifnet *ifp, struct mbuf *m) /* * Flush the buffer for this descriptor */ - rtems_flush_multiple_data_cache_lines(txBd->buffer, txBd->length); + rtems_cache_flush_multiple_data_lines(txBd->buffer, txBd->length); sc->txMbuf[sc->txBdHead] = m; nAdded++; diff --git a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c index 2180df9b44..32061a9545 100644 --- a/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c +++ b/c/src/lib/libbsp/powerpc/mbx8xx/startup/bspstart.c @@ -136,11 +136,11 @@ void bsp_start(void) * Enable instruction and data caches. Do not force writethrough mode. */ #ifdef INSTRUCTION_CACHE_ENABLE - rtems_enable_inst_cache(); + rtems_cache_enable_instruction(); #endif #ifdef DATA_CACHE_ENABLE - rtems_enable_data_cache(); + rtems_cache_enable_data(); #endif /* diff --git a/c/src/lib/libcpu/i386/cache.c b/c/src/lib/libcpu/i386/cache.c index 976f00e5e1..57dfee283d 100644 --- a/c/src/lib/libcpu/i386/cache.c +++ b/c/src/lib/libcpu/i386/cache.c @@ -15,7 +15,7 @@ void _CPU_disable_cache() { regCr0.cr0.page_level_cache_disable = 1; regCr0.cr0.no_write_through = 1; i386_set_cr0( regCr0.i ); - rtems_flush_entire_data_cache(); + rtems_cache_flush_entire_data(); } /* @@ -29,7 +29,7 @@ void _CPU_enable_cache() { regCr0.cr0.page_level_cache_disable = 0; regCr0.cr0.no_write_through = 0; i386_set_cr0( regCr0.i ); - /*rtems_flush_entire_data_cache();*/ + /*rtems_cache_flush_entire_data();*/ } /* @@ -38,56 +38,49 @@ void _CPU_enable_cache() { * management routines. If a given function has no meaning for the CPU, * it does nothing by default. * - * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for - * each CPU. The routines below should be implemented per CPU, + * FIXME: The routines below should be implemented per CPU, * to accomodate the capabilities of each. */ -/* FIXME: I don't belong here. */ -#define I386_CACHE_ALIGNMENT 16 - #if defined(I386_CACHE_ALIGNMENT) -#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT - -void _CPU_flush_1_data_cache_line(const void *d_addr) {} -void _CPU_invalidate_1_data_cache_line(const void *d_addr) {} -void _CPU_freeze_data_cache(void) {} -void _CPU_unfreeze_data_cache(void) {} -void _CPU_invalidate_1_inst_cache_line ( const void *d_addr ) {} -void _CPU_freeze_inst_cache(void) {} -void _CPU_unfreeze_inst_cache(void) {} - -void _CPU_flush_entire_data_cache(void) +void _CPU_cache_flush_1_data_line(const void *d_addr) {} +void _CPU_cache_invalidate_1_data_line(const void *d_addr) {} +void _CPU_cache_freeze_data(void) {} +void _CPU_cache_unfreeze_data(void) {} +void _CPU_cache_invalidate_1_instruction_line ( const void *d_addr ) {} +void _CPU_cache_freeze_instruction(void) {} +void _CPU_cache_unfreeze_instruction(void) {} + +void _CPU_cache_flush_entire_data(void) { asm volatile ("wbinvd"); } -void _CPU_invalidate_entire_data_cache(void) +void _CPU_cache_invalidate_entire_data(void) { asm volatile ("invd"); } -void _CPU_enable_data_cache(void) +void _CPU_cache_enable_data(void) { _CPU_enable_cache(); } -void _CPU_disable_data_cache(void) +void _CPU_cache_disable_data(void) { _CPU_disable_cache(); } -void _CPU_invalidate_entire_inst_cache(void) +void _CPU_cache_invalidate_entire_instruction(void) { asm volatile ("invd"); } -void _CPU_enable_inst_cache(void) +void _CPU_cache_enable_instruction(void) { _CPU_enable_cache(); } -void _CPU_disable_inst_cache( void ) +void _CPU_cache_disable_instruction( void ) { _CPU_disable_cache(); } diff --git a/c/src/lib/libcpu/i386/cache_.h b/c/src/lib/libcpu/i386/cache_.h index c660c720d3..2450e5e4be 100644 --- a/c/src/lib/libcpu/i386/cache_.h +++ b/c/src/lib/libcpu/i386/cache_.h @@ -6,8 +6,8 @@ #define __i386_CACHE_h #define I386_CACHE_ALIGNMENT 16 -#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT +#define CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT +#define CPU_INSTRUCTION_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT #include diff --git a/c/src/lib/libcpu/i386/page.c b/c/src/lib/libcpu/i386/page.c index e5cceeed23..c44ab3a393 100644 --- a/c/src/lib/libcpu/i386/page.c +++ b/c/src/lib/libcpu/i386/page.c @@ -45,7 +45,7 @@ extern rtems_unsigned32 rtemsFreeMemStart; void _CPU_disable_paging() { cr0 regCr0; - rtems_flush_entire_data_cache(); + rtems_cache_flush_entire_data(); regCr0.i = i386_get_cr0(); regCr0.cr0.paging = 0; i386_set_cr0( regCr0.i ); @@ -60,7 +60,7 @@ void _CPU_enable_paging() { regCr0.i = i386_get_cr0(); regCr0.cr0.paging = 1; i386_set_cr0( regCr0.i ); - rtems_flush_entire_data_cache(); + rtems_cache_flush_entire_data(); } diff --git a/c/src/lib/libcpu/m68k/shared/cache/cache.c b/c/src/lib/libcpu/m68k/shared/cache/cache.c index ce98f006c6..60f3a63d4c 100644 --- a/c/src/lib/libcpu/m68k/shared/cache/cache.c +++ b/c/src/lib/libcpu/m68k/shared/cache/cache.c @@ -52,10 +52,10 @@ /* Only the mc68030 has a data cache; it is writethrough only. */ -void _CPU_flush_1_data_cache_line ( const void * d_addr ) {} -void _CPU_flush_entire_data_cache ( const void * d_addr ) {} +void _CPU_cache_flush_1_data_line ( const void * d_addr ) {} +void _CPU_cache_flush_entire_data ( const void * d_addr ) {} -void _CPU_invalidate_1_data_cache_line ( +void _CPU_cache_invalidate_1_data_line ( const void * d_addr ) { void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); @@ -63,26 +63,26 @@ void _CPU_invalidate_1_data_cache_line ( _CPU_CACR_OR(0x00000400); } -void _CPU_invalidate_entire_data_cache ( void ) +void _CPU_cache_invalidate_entire_data ( void ) { _CPU_CACR_OR( 0x00000800 ); } -void _CPU_freeze_data_cache ( void ) +void _CPU_cache_freeze_data ( void ) { _CPU_CACR_OR( 0x00000200 ); } -void _CPU_unfreeze_data_cache ( void ) +void _CPU_cache_unfreeze_data ( void ) { _CPU_CACR_AND( 0xFFFFFDFF ); } -void _CPU_enable_data_cache ( void ) +void _CPU_cache_enable_data ( void ) { _CPU_CACR_OR( 0x00000100 ); } -void _CPU_disable_data_cache ( void ) +void _CPU_cache_disable_data ( void ) { _CPU_CACR_AND( 0xFFFFFEFF ); } @@ -91,7 +91,7 @@ void _CPU_disable_data_cache ( void ) /* Both the 68020 and 68030 have instruction caches */ -void _CPU_invalidate_1_inst_cache_line ( +void _CPU_cache_invalidate_1_instruction_line ( const void * d_addr ) { void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); @@ -99,27 +99,27 @@ void _CPU_invalidate_1_inst_cache_line ( _CPU_CACR_OR( 0x00000004 ); } -void _CPU_invalidate_entire_inst_cache ( void ) +void _CPU_cache_invalidate_entire_instruction ( void ) { _CPU_CACR_OR( 0x00000008 ); } -void _CPU_freeze_inst_cache ( void ) +void _CPU_cache_freeze_instruction ( void ) { _CPU_CACR_OR( 0x00000002); } -void _CPU_unfreeze_inst_cache ( void ) +void _CPU_cache_unfreeze_instruction ( void ) { _CPU_CACR_AND( 0xFFFFFFFD ); } -void _CPU_enable_inst_cache ( void ) +void _CPU_cache_enable_instruction ( void ) { _CPU_CACR_OR( 0x00000001 ); } -void _CPU_disable_inst_cache ( void ) +void _CPU_cache_disable_instruction ( void ) { _CPU_CACR_AND( 0xFFFFFFFE ); } @@ -128,63 +128,63 @@ void _CPU_disable_inst_cache ( void ) #elif ( defined(__mc68040__) || defined (__mc68060__) ) /* Cannot be frozen */ -void _CPU_freeze_data_cache ( void ) {} -void _CPU_unfreeze_data_cache ( void ) {} -void _CPU_freeze_inst_cache ( void ) {} -void _CPU_unfreeze_inst_cache ( void ) {} +void _CPU_cache_freeze_data ( void ) {} +void _CPU_cache_unfreeze_data ( void ) {} +void _CPU_cache_freeze_instruction ( void ) {} +void _CPU_cache_unfreeze_instruction ( void ) {} -void _CPU_flush_1_data_cache_line ( +void _CPU_cache_flush_1_data_line ( const void * d_addr ) { void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); asm volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) ); } -void _CPU_invalidate_1_data_cache_line ( +void _CPU_cache_invalidate_1_data_line ( const void * d_addr ) { void * p_address = (void *) _CPU_virtual_to_physical( d_addr ); asm volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) ); } -void _CPU_flush_entire_data_cache ( void ) +void _CPU_cache_flush_entire_data ( void ) { asm volatile ( "cpusha %%dc" :: ); } -void _CPU_invalidate_entire_data_cache ( void ) +void _CPU_cache_invalidate_entire_data ( void ) { asm volatile ( "cinva %%dc" :: ); } -void _CPU_enable_data_cache ( void ) +void _CPU_cache_enable_data ( void ) { _CPU_CACR_OR( 0x80000000 ); } -void _CPU_disable_data_cache ( void ) +void _CPU_cache_disable_data ( void ) { _CPU_CACR_AND( 0x7FFFFFFF ); } -void _CPU_invalidate_1_inst_cache_line ( +void _CPU_cache_invalidate_1_instruction_line ( const void * i_addr ) { void * p_address = (void *) _CPU_virtual_to_physical( i_addr ); asm volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) ); } -void _CPU_invalidate_entire_inst_cache ( void ) +void _CPU_cache_invalidate_entire_instruction ( void ) { asm volatile ( "cinva %%ic" :: ); } -void _CPU_enable_inst_cache ( void ) +void _CPU_cache_enable_instruction ( void ) { _CPU_CACR_OR( 0x00008000 ); } -void _CPU_disable_inst_cache ( void ) +void _CPU_cache_disable_instruction ( void ) { _CPU_CACR_AND( 0xFFFF7FFF ); } diff --git a/c/src/lib/libcpu/m68k/shared/cache/cache_.h b/c/src/lib/libcpu/m68k/shared/cache/cache_.h index 13406b3c49..a8d507a798 100644 --- a/c/src/lib/libcpu/m68k/shared/cache/cache_.h +++ b/c/src/lib/libcpu/m68k/shared/cache/cache_.h @@ -6,21 +6,21 @@ #define __M68K_CACHE_h #if defined(__mc68020__) -#define M68K_INST_CACHE_ALIGNMENT 16 +#define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 #elif defined(__mc68030__) -#define M68K_INST_CACHE_ALIGNMENT 16 +#define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 #define M68K_DATA_CACHE_ALIGNMENT 16 #elif ( defined(__mc68040__) || defined (__mc68060__) ) -#define M68K_INST_CACHE_ALIGNMENT 16 +#define M68K_INSTRUCTION_CACHE_ALIGNMENT 16 #define M68K_DATA_CACHE_ALIGNMENT 16 #endif #if defined(M68K_DATA_CACHE_ALIGNMENT) -#define _CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT +#define CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT #endif -#if defined(M68K_INST_CACHE_ALIGNMENT) -#define _CPU_INST_CACHE_ALIGNMENT M68K_INST_CACHE_ALIGNMENT +#if defined(M68K_INSTRUCTION_CACHE_ALIGNMENT) +#define CPU_INSTRUCTION_CACHE_ALIGNMENT M68K_INSTRUCTION_CACHE_ALIGNMENT #endif #include diff --git a/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c index 0f25b297b4..3349c86dd1 100644 --- a/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c +++ b/c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c @@ -399,7 +399,7 @@ m8xx_scc2_interrupt_handler (rtems_vector_number v) /* Check that the buffer is ours */ if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_invalidate_multiple_data_cache_lines( + rtems_cache_invalidate_multiple_data_lines( (const void *) RxBd[SCC2_MINOR]->buffer, RxBd[SCC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( @@ -442,7 +442,7 @@ m8xx_scc3_interrupt_handler (rtems_vector_number v) /* Check that the buffer is ours */ if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_invalidate_multiple_data_cache_lines( + rtems_cache_invalidate_multiple_data_lines( (const void *) RxBd[SCC3_MINOR]->buffer, RxBd[SCC3_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( @@ -484,7 +484,7 @@ m8xx_scc4_interrupt_handler (rtems_vector_number v) /* Check that the buffer is ours */ if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_invalidate_multiple_data_cache_lines( + rtems_cache_invalidate_multiple_data_lines( (const void *) RxBd[SCC4_MINOR]->buffer, RxBd[SCC4_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( @@ -526,7 +526,7 @@ m8xx_smc1_interrupt_handler (rtems_vector_number v) /* Check that the buffer is ours */ if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_invalidate_multiple_data_cache_lines( + rtems_cache_invalidate_multiple_data_lines( (const void *) RxBd[SMC1_MINOR]->buffer, RxBd[SMC1_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( @@ -568,7 +568,7 @@ m8xx_smc2_interrupt_handler (rtems_vector_number v) /* Check that the buffer is ours */ if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) { - rtems_invalidate_multiple_data_cache_lines( + rtems_cache_invalidate_multiple_data_lines( (const void *) RxBd[SMC2_MINOR]->buffer, RxBd[SMC2_MINOR]->length ); nb_overflow = rtems_termios_enqueue_raw_characters( @@ -984,7 +984,7 @@ m8xx_uart_pollRead( if (RxBd[minor]->status & M8xx_BD_EMPTY) { return -1; } - rtems_invalidate_multiple_data_cache_lines( + rtems_cache_invalidate_multiple_data_lines( (const void *) RxBd[minor]->buffer, RxBd[minor]->length ); @@ -1004,7 +1004,7 @@ m8xx_uart_write( int len ) { - rtems_flush_multiple_data_cache_lines( buf, len ); + rtems_cache_flush_multiple_data_lines( buf, len ); TxBd[minor]->buffer = (char *) buf; TxBd[minor]->length = len; TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT; @@ -1023,7 +1023,7 @@ m8xx_uart_pollWrite( while (TxBd[minor]->status & M8xx_BD_READY) continue; txBuf[minor] = *buf++; - rtems_flush_multiple_data_cache_lines( + rtems_cache_flush_multiple_data_lines( (const void *) TxBd[minor]->buffer, TxBd[minor]->length ); diff --git a/c/src/lib/libcpu/powerpc/shared/src/cache.c b/c/src/lib/libcpu/powerpc/shared/src/cache.c index 4bc824904e..bbd7000b0a 100644 --- a/c/src/lib/libcpu/powerpc/shared/src/cache.c +++ b/c/src/lib/libcpu/powerpc/shared/src/cache.c @@ -42,7 +42,7 @@ ); \ } while (0) -void _CPU_enable_data_cache ( +void _CPU_cache_enable_data ( void ) { unsigned32 value; @@ -51,7 +51,7 @@ void _CPU_enable_data_cache ( PPC_Set_HID0( value ); } -void _CPU_disable_data_cache ( +void _CPU_cache_disable_data ( void ) { unsigned32 value; @@ -60,7 +60,7 @@ void _CPU_disable_data_cache ( PPC_Set_HID0( value ); } -void _CPU_enable_inst_cache ( +void _CPU_cache_enable_inst ( void ) { unsigned32 value; @@ -69,7 +69,7 @@ void _CPU_enable_inst_cache ( PPC_Set_HID0( value ); } -void _CPU_disable_inst_cache ( +void _CPU_cache_disable_inst ( void ) { unsigned32 value; @@ -85,26 +85,26 @@ void _CPU_disable_inst_cache ( #define isync \ __asm__ volatile ("isync\n"::) -void _CPU_flush_1_data_cache_line( +void _CPU_cache_flush_1_data_line( const void * _address ) { register const void *__address = _address; asm volatile ( "dcbf 0,%0" :: "r" (__address) ); } -void _CPU_invalidate_1_data_cache_line( +void _CPU_cache_invalidate_1_data_line( const void * _address ) { register const void *__address = _address; asm volatile ( "dcbi 0,%0" :: "r" (__address) ); } -void _CPU_flush_entire_data_cache ( void ) {} -void _CPU_invalidate_entire_data_cache ( void ) {} -void _CPU_freeze_data_cache ( void ) {} -void _CPU_unfreeze_data_cache ( void ) {} +void _CPU_cache_flush_entire_data ( void ) {} +void _CPU_cache_invalidate_entire_data ( void ) {} +void _CPU_cache_freeze_data ( void ) {} +void _CPU_cache_unfreeze_data ( void ) {} -void _CPU_enable_data_cache ( void ) +void _CPU_cache_enable_data ( void ) { unsigned32 r1; r1 = (0x2<<24); @@ -112,7 +112,7 @@ void _CPU_enable_data_cache ( void ) isync; } -void _CPU_disable_data_cache ( void ) +void _CPU_cache_disable_data ( void ) { unsigned32 r1; r1 = (0x4<<24); @@ -120,18 +120,18 @@ void _CPU_disable_data_cache ( void ) isync; } -void _CPU_invalidate_1_inst_cache_line( +void _CPU_cache_invalidate_1_inst_line( const void * _address ) { register const void *__address = _address; asm volatile ( "icbi 0,%0" :: "r" (__address) ); } -void _CPU_invalidate_entire_inst_cache ( void ) {} -void _CPU_freeze_inst_cache ( void ) {} -void _CPU_unfreeze_inst_cache ( void ) {} +void _CPU_cache_invalidate_entire_inst ( void ) {} +void _CPU_cache_freeze_inst ( void ) {} +void _CPU_cache_unfreeze_inst ( void ) {} -void _CPU_enable_inst_cache ( void ) +void _CPU_cache_enable_inst ( void ) { unsigned32 r1; r1 = (0x2<<24); @@ -139,7 +139,7 @@ void _CPU_enable_inst_cache ( void ) isync; } -void _CPU_disable_inst_cache ( void ) +void _CPU_cache_disable_inst ( void ) { unsigned32 r1; r1 = (0x4<<24); diff --git a/c/src/lib/libcpu/powerpc/shared/src/cache_.h b/c/src/lib/libcpu/powerpc/shared/src/cache_.h index ab14ca9c40..bff8874587 100644 --- a/c/src/lib/libcpu/powerpc/shared/src/cache_.h +++ b/c/src/lib/libcpu/powerpc/shared/src/cache_.h @@ -15,13 +15,13 @@ */ #if defined(ppc603) /* And possibly others */ -#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT +#define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT +#define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT #elif ( defined(mpc860) || defined(mpc821) ) -#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT -#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT +#define CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT +#define CPU_INSTRUCTION_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT #endif diff --git a/c/src/lib/libcpu/shared/include/cache.h b/c/src/lib/libcpu/shared/include/cache.h index d2ec92686d..8c00cb38bd 100644 --- a/c/src/lib/libcpu/shared/include/cache.h +++ b/c/src/lib/libcpu/shared/include/cache.h @@ -9,24 +9,20 @@ #include -void _CPU_disable_cache(); -void _CPU_enable_cache(); - -void _CPU_flush_1_data_cache_line(const void *d_addr); -void _CPU_invalidate_1_data_cache_line(const void *d_addr); -void _CPU_freeze_data_cache(void); -void _CPU_unfreeze_data_cache(void); -void _CPU_invalidate_1_inst_cache_line(const void *d_addr); -void _CPU_freeze_inst_cache(void); -void _CPU_unfreeze_inst_cache(void); - -void _CPU_flush_entire_data_cache(void); -void _CPU_invalidate_entire_data_cache(void); -void _CPU_enable_data_cache(void); -void _CPU_disable_data_cache(void); -void _CPU_invalidate_entire_inst_cache(void); -void _CPU_enable_inst_cache(void); -void _CPU_disable_inst_cache(void); +void _CPU_cache_flush_1_data_line(const void *d_addr); +void _CPU_cache_invalidate_1_data_line(const void *d_addr); +void _CPU_cache_freeze_data(void); +void _CPU_cache_unfreeze_data(void); +void _CPU_cache_invalidate_1_instruction_line(const void *d_addr); +void _CPU_cache_freeze_instruction(void); +void _CPU_cache_unfreeze_instruction(void); +void _CPU_cache_flush_entire_data(void); +void _CPU_cache_invalidate_entire_data(void); +void _CPU_cache_enable_data(void); +void _CPU_cache_disable_data(void); +void _CPU_cache_invalidate_entire_instruction(void); +void _CPU_cache_enable_instruction(void); +void _CPU_cache_disable_instruction(void); #endif /* end of include file */ diff --git a/c/src/lib/libcpu/shared/src/cache_aligned_malloc.c b/c/src/lib/libcpu/shared/src/cache_aligned_malloc.c index 3289317132..62ea4f7d4b 100644 --- a/c/src/lib/libcpu/shared/src/cache_aligned_malloc.c +++ b/c/src/lib/libcpu/shared/src/cache_aligned_malloc.c @@ -32,10 +32,10 @@ void *rtems_cache_aligned_malloc ( * Arrange to have the user storage start on the first cache * block beyond the header. */ -#if defined(_CPU_DATA_CACHE_ALIGNMENT) +#if defined(CPU_DATA_CACHE_ALIGNMENT) return (void *) ((((unsigned long) - malloc( nbytes + _CPU_DATA_CACHE_ALIGNMENT - 1 )) - + _CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(_CPU_DATA_CACHE_ALIGNMENT - 1)) ); + malloc( nbytes + CPU_DATA_CACHE_ALIGNMENT - 1 )) + + CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(CPU_DATA_CACHE_ALIGNMENT - 1)) ); #else return malloc( nbytes ); #endif diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c index e55cf7ea05..9f4b746761 100644 --- a/c/src/lib/libcpu/shared/src/cache_manager.c +++ b/c/src/lib/libcpu/shared/src/cache_manager.c @@ -11,17 +11,18 @@ * * The functions in this file implement the API to the RTEMS Cache Manager and * are divided into data cache and instruction cache functions. Data cache - * functions are only declared if a data cache is supported. Instruction - * cache functions are only declared if an instruction cache is supported. - * Support for a particular cache exists only if _CPU_x_CACHE_ALIGNMENT is - * defined, where x E {DATA, INST}. These definitions are found in the CPU - * dependent source files in the supercore, often + * functions only have bodies if a data cache is supported. Instruction + * cache functions only have bodies if an instruction cache is supported. + * Support for a particular cache exists only if CPU_x_CACHE_ALIGNMENT is + * defined, where x E {DATA, INSTRUCTION}. These definitions are found in + * the Cache Manager Wrapper header files, often * - * rtems/c/src/exec/score/cpu/CPU/rtems/score/CPU.h + * rtems/c/src/lib/libcpu/CPU/cache_.h * * The functions below are implemented with CPU dependent inline routines - * also found in the above file. In the event that a CPU does not support a - * specific function, the CPU dependent routine does nothing (but does exist). + * found in the cache.c files for each CPU. In the event that a CPU does + * not support a specific function for a cache it has, the CPU dependent + * routine does nothing (but does exist). * * At this point, the Cache Manager makes no considerations, and provides no * support for BSP specific issues such as a secondary cache. In such a system, @@ -45,9 +46,9 @@ * back and then perform the copybacks. */ void -rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes ) +rtems_cache_flush_multiple_data_lines( const void * d_addr, size_t n_bytes ) { -#if defined(_CPU_DATA_CACHE_ALIGNMENT) +#if defined(CPU_DATA_CACHE_ALIGNMENT) const void * final_address; /* @@ -57,10 +58,10 @@ rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes ) */ final_address = (void *)((size_t)d_addr + n_bytes - 1); - d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1)); + d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); while( d_addr <= final_address ) { - _CPU_flush_1_data_cache_line( d_addr ); - d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT); + _CPU_cache_flush_1_data_line( d_addr ); + d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); } #endif } @@ -73,9 +74,9 @@ rtems_flush_multiple_data_cache_lines( const void * d_addr, size_t n_bytes ) */ void -rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes ) +rtems_cache_invalidate_multiple_data_lines( const void * d_addr, size_t n_bytes ) { -#if defined(_CPU_DATA_CACHE_ALIGNMENT) +#if defined(CPU_DATA_CACHE_ALIGNMENT) const void * final_address; /* @@ -85,10 +86,10 @@ rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes */ final_address = (void *)((size_t)d_addr + n_bytes - 1); - d_addr = (void *)((size_t)d_addr & ~(_CPU_DATA_CACHE_ALIGNMENT - 1)); + d_addr = (void *)((size_t)d_addr & ~(CPU_DATA_CACHE_ALIGNMENT - 1)); while( final_address > d_addr ) { - _CPU_invalidate_1_data_cache_line( d_addr ); - d_addr = (void *)((size_t)d_addr + _CPU_DATA_CACHE_ALIGNMENT); + _CPU_cache_invalidate_1_data_line( d_addr ); + d_addr = (void *)((size_t)d_addr + CPU_DATA_CACHE_ALIGNMENT); } #endif } @@ -99,13 +100,13 @@ rtems_invalidate_multiple_data_cache_lines( const void * d_addr, size_t n_bytes * It flushes the entire cache. */ void -rtems_flush_entire_data_cache( void ) +rtems_cache_flush_entire_data( void ) { -#if defined(_CPU_DATA_CACHE_ALIGNMENT) +#if defined(CPU_DATA_CACHE_ALIGNMENT) /* * Call the CPU-specific routine */ - _CPU_flush_entire_data_cache(); + _CPU_cache_flush_entire_data(); #endif } @@ -115,14 +116,14 @@ rtems_flush_entire_data_cache( void ) * invalidate. It invalidates the entire cache. */ void -rtems_invalidate_entire_data_cache( void ) +rtems_cache_invalidate_entire_data( void ) { -#if defined(_CPU_DATA_CACHE_ALIGNMENT) +#if defined(CPU_DATA_CACHE_ALIGNMENT) /* * Call the CPU-specific routine */ - _CPU_invalidate_entire_data_cache(); + _CPU_cache_invalidate_entire_data(); #endif } @@ -131,10 +132,10 @@ rtems_invalidate_entire_data_cache( void ) * This function returns the data cache granularity. */ int -rtems_get_data_cache_line_size( void ) +rtems_cache_get_data_line_size( void ) { -#if defined(_CPU_DATA_CACHE_ALIGNMENT) - return _CPU_DATA_CACHE_ALIGNMENT; +#if defined(CPU_DATA_CACHE_ALIGNMENT) + return CPU_DATA_CACHE_ALIGNMENT; #else return 0; #endif @@ -146,10 +147,10 @@ rtems_get_data_cache_line_size( void ) * are not replaced. */ void -rtems_freeze_data_cache( void ) +rtems_cache_freeze_data( void ) { -#if defined(_CPU_DATA_CACHE_ALIGNMENT) - _CPU_freeze_data_cache(); +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _CPU_cache_freeze_data(); #endif } @@ -157,30 +158,30 @@ rtems_freeze_data_cache( void ) /* * This function unfreezes the instruction cache. */ -void rtems_unfreeze_data_cache( void ) +void rtems_cache_unfreeze_data( void ) { -#if defined(_CPU_DATA_CACHE_ALIGNMENT) - _CPU_unfreeze_data_cache(); +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _CPU_cache_unfreeze_data(); #endif } /* Turn on the data cache. */ void -rtems_enable_data_cache( void ) +rtems_cache_enable_data( void ) { -#if defined(_CPU_DATA_CACHE_ALIGNMENT) - _CPU_enable_data_cache(); +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _CPU_cache_enable_data(); #endif } /* Turn off the data cache. */ void -rtems_disable_data_cache( void ) +rtems_cache_disable_data( void ) { -#if defined(_CPU_DATA_CACHE_ALIGNMENT) - _CPU_disable_data_cache(); +#if defined(CPU_DATA_CACHE_ALIGNMENT) + _CPU_cache_disable_data(); #endif } @@ -196,9 +197,9 @@ rtems_disable_data_cache( void ) * and then perform the invalidations. */ void -rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes ) +rtems_cache_invalidate_multiple_instruction_lines( const void * i_addr, size_t n_bytes ) { -#if defined(_CPU_INST_CACHE_ALIGNMENT) +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) const void * final_address; /* @@ -208,10 +209,10 @@ rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes */ final_address = (void *)((size_t)i_addr + n_bytes - 1); - i_addr = (void *)((size_t)i_addr & ~(_CPU_INST_CACHE_ALIGNMENT - 1)); + i_addr = (void *)((size_t)i_addr & ~(CPU_INSTRUCTION_CACHE_ALIGNMENT - 1)); while( final_address > i_addr ) { - _CPU_invalidate_1_inst_cache_line( i_addr ); - i_addr = (void *)((size_t)i_addr + _CPU_INST_CACHE_ALIGNMENT); + _CPU_cache_invalidate_1_instruction_line( i_addr ); + i_addr = (void *)((size_t)i_addr + CPU_INSTRUCTION_CACHE_ALIGNMENT); } #endif } @@ -222,14 +223,14 @@ rtems_invalidate_multiple_inst_cache_lines( const void * i_addr, size_t n_bytes * invalidate. It invalidates the entire cache. */ void -rtems_invalidate_entire_inst_cache( void ) +rtems_cache_invalidate_entire_instruction( void ) { -#if defined(_CPU_INST_CACHE_ALIGNMENT) +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) /* * Call the CPU-specific routine */ - _CPU_invalidate_entire_inst_cache(); + _CPU_cache_invalidate_entire_instruction(); #endif } @@ -238,10 +239,10 @@ rtems_invalidate_entire_inst_cache( void ) * This function returns the instruction cache granularity. */ int -rtems_get_inst_cache_line_size( void ) +rtems_cache_get_instruction_line_size( void ) { -#if defined(_CPU_INST_CACHE_ALIGNMENT) - return _CPU_INST_CACHE_ALIGNMENT; +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) + return CPU_INSTRUCTION_CACHE_ALIGNMENT; #else return 0; #endif @@ -253,10 +254,10 @@ rtems_get_inst_cache_line_size( void ) * are not replaced. */ void -rtems_freeze_inst_cache( void ) +rtems_cache_freeze_instruction( void ) { -#if defined(_CPU_INST_CACHE_ALIGNMENT) - _CPU_freeze_inst_cache(); +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) + _CPU_cache_freeze_instruction(); #endif } @@ -264,29 +265,29 @@ rtems_freeze_inst_cache( void ) /* * This function unfreezes the instruction cache. */ -void rtems_unfreeze_inst_cache( void ) +void rtems_cache_unfreeze_instruction( void ) { -#if defined(_CPU_INST_CACHE_ALIGNMENT) - _CPU_unfreeze_inst_cache(); +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) + _CPU_cache_unfreeze_instruction(); #endif } /* Turn on the instruction cache. */ void -rtems_enable_inst_cache( void ) +rtems_cache_enable_instruction( void ) { -#if defined(_CPU_INST_CACHE_ALIGNMENT) - _CPU_enable_inst_cache(); +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) + _CPU_cache_enable_instruction(); #endif } /* Turn off the instruction cache. */ void -rtems_disable_inst_cache( void ) +rtems_cache_disable_instruction( void ) { -#if defined(_CPU_INST_CACHE_ALIGNMENT) - _CPU_disable_inst_cache(); +#if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT) + _CPU_cache_disable_instruction(); #endif } -- cgit v1.2.3