From 5e657e2363affc873a5510a48f238e3242b29216 Mon Sep 17 00:00:00 2001 From: Thomas Doerfler Date: Fri, 9 Apr 2010 12:30:39 +0000 Subject: Documentation. Fixed mask defines. --- c/src/lib/libcpu/arm/ChangeLog | 4 + c/src/lib/libcpu/arm/shared/include/arm-cp15.h | 346 ++++++++++++++----------- 2 files changed, 203 insertions(+), 147 deletions(-) (limited to 'c/src') diff --git a/c/src/lib/libcpu/arm/ChangeLog b/c/src/lib/libcpu/arm/ChangeLog index c5e38a1d1d..4cc6232b5d 100644 --- a/c/src/lib/libcpu/arm/ChangeLog +++ b/c/src/lib/libcpu/arm/ChangeLog @@ -1,3 +1,7 @@ +2010-04-08 Sebastian Huber + + * shared/include/arm-cp15.h: Documentation. Fixed mask defines. + 2010-03-03 Sebastian Huber * shared/include/cache.h: Fixed _CPU_cache_disable_data(). diff --git a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h index 3f0036f6c6..78d32a398b 100644 --- a/c/src/lib/libcpu/arm/shared/include/arm-cp15.h +++ b/c/src/lib/libcpu/arm/shared/include/arm-cp15.h @@ -1,13 +1,13 @@ /** * @file * - * @ingroup arm + * @ingroup ScoreCPUARMCP15 * * @brief ARM co-processor 15 (CP15) API. */ /* - * Copyright (c) 2009 + * Copyright (c) 2009, 2010 * embedded brains GmbH * Obere Lagerstr. 30 * D-82178 Puchheim @@ -28,14 +28,36 @@ extern "C" { #endif /* __cplusplus */ +#define ARM_CP15_CACHE_PREPARE_MVA(mva) \ + ((const void *) (((uint32_t) (mva)) & ~0x1fU)) + +#define ARM_CP15_TLB_PREPARE_MVA(mva) \ + ((const void *) (((uint32_t) (mva)) & ~0x3fU)) + +/** + * @defgroup ScoreCPUARMCP15 ARM Co-Processor 15 Support + * + * @ingroup ScoreCPUARM + * + * @brief ARM co-processor 15 (CP15) support. + * + * @{ + */ + +/** + * @name MMU Defines + * + * @{ + */ + #define ARM_MMU_SECT_BASE_SHIFT 20 -#define ARM_MMU_SECT_BASE_MASK 0xfffU +#define ARM_MMU_SECT_BASE_MASK (0xfffU << ARM_MMU_SECT_BASE_SHIFT) #define ARM_MMU_SECT_DOMAIN_SHIFT 5 -#define ARM_MMU_SECT_DOMAIN_MASK 0xfU +#define ARM_MMU_SECT_DOMAIN_MASK (0xfU << ARM_MMU_SECT_DOMAIN_SHIFT) #define ARM_MMU_SECT_AP_1 (1U << 11) #define ARM_MMU_SECT_AP_0 (1U << 10) #define ARM_MMU_SECT_AP_SHIFT 10 -#define ARM_MMU_SECT_AP_MASK 0x3U +#define ARM_MMU_SECT_AP_MASK (0x3U << ARM_MMU_SECT_AP_SHIFT) #define ARM_MMU_SECT_C (1U << 3) #define ARM_MMU_SECT_B (1U << 2) #define ARM_MMU_SECT_DEFAULT 0x12U @@ -48,29 +70,48 @@ extern "C" { #define ARM_MMU_TRANSLATION_TABLE_ENTRY_SIZE 4U #define ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT 4096U -static inline uint32_t arm_cp15_get_id_code(void) -{ - ARM_SWITCH_REGISTERS; - uint32_t val; +/** @} */ - asm volatile ( - ARM_SWITCH_TO_ARM - "mrc p15, 0, %[val], c0, c0, 0\n" - ARM_SWITCH_BACK - : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT - ); +/** + * @name Control Register Defines + * + * @{ + */ - return val; -} +#define ARM_CP15_CTRL_L4 (1U << 15) +#define ARM_CP15_CTRL_RR (1U << 14) +#define ARM_CP15_CTRL_V (1U << 13) +#define ARM_CP15_CTRL_I (1U << 12) +#define ARM_CP15_CTRL_R (1U << 9) +#define ARM_CP15_CTRL_S (1U << 8) +#define ARM_CP15_CTRL_B (1U << 7) +#define ARM_CP15_CTRL_C (1U << 2) +#define ARM_CP15_CTRL_A (1U << 1) +#define ARM_CP15_CTRL_M (1U << 0) -static inline uint32_t arm_cp15_get_cache_type(void) +/** @} */ + +/** + * @name Domain Access Control Defines + * + * @{ + */ + +#define ARM_CP15_DAC_NO_ACCESS 0x0U +#define ARM_CP15_DAC_CLIENT 0x1U +#define ARM_CP15_DAC_MANAGER 0x3U +#define ARM_CP15_DAC_DOMAIN(index, val) ((val) << (2 * index)) + +/** @} */ + +static inline uint32_t arm_cp15_get_id_code(void) { ARM_SWITCH_REGISTERS; uint32_t val; asm volatile ( ARM_SWITCH_TO_ARM - "mrc p15, 0, %[val], c0, c0, 1\n" + "mrc p15, 0, %[val], c0, c0, 0\n" ARM_SWITCH_BACK : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT ); @@ -93,17 +134,6 @@ static inline uint32_t arm_cp15_get_tcm_status(void) return val; } -#define ARM_CP15_CTRL_L4 (1U << 15) -#define ARM_CP15_CTRL_RR (1U << 14) -#define ARM_CP15_CTRL_V (1U << 13) -#define ARM_CP15_CTRL_I (1U << 12) -#define ARM_CP15_CTRL_R (1U << 9) -#define ARM_CP15_CTRL_S (1U << 8) -#define ARM_CP15_CTRL_B (1U << 7) -#define ARM_CP15_CTRL_C (1U << 2) -#define ARM_CP15_CTRL_A (1U << 1) -#define ARM_CP15_CTRL_M (1U << 0) - static inline uint32_t arm_cp15_get_control(void) { ARM_SWITCH_REGISTERS; @@ -135,6 +165,12 @@ static inline void arm_cp15_set_control(uint32_t val) ); } +/** + * @name MMU Functions + * + * @{ + */ + static inline uint32_t *arm_cp15_get_translation_table_base(void) { ARM_SWITCH_REGISTERS; @@ -163,11 +199,6 @@ static inline void arm_cp15_set_translation_table_base(uint32_t *base) ); } -#define ARM_CP15_DAC_NO_ACCESS 0x0U -#define ARM_CP15_DAC_CLIENT 0x1U -#define ARM_CP15_DAC_MANAGER 0x3U -#define ARM_CP15_DAC_DOMAIN(index, val) ((val) << (2 * index)) - static inline uint32_t arm_cp15_get_domain_access_control(void) { ARM_SWITCH_REGISTERS; @@ -280,130 +311,169 @@ static inline void arm_cp15_set_fault_address(const void *mva) ); } -#define ARM_CP15_CACHE_PREPARE_MVA(mva) \ - ((const void *) (((uint32_t) (mva)) & ~0x1fU)) - -static inline void arm_cp15_cache_invalidate(void) +static inline void arm_cp15_tlb_invalidate(void) { ARM_SWITCH_REGISTERS; uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[sbz], c7, c7, 0\n" + "mcr p15, 0, %[sbz], c8, c7, 0\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT : [sbz] "r" (sbz) - : "memory" ); } -static inline void arm_cp15_instruction_cache_invalidate(void) +static inline void arm_cp15_tlb_invalidate_entry(const void *mva) +{ + ARM_SWITCH_REGISTERS; + + mva = ARM_CP15_TLB_PREPARE_MVA(mva); + + asm volatile ( + ARM_SWITCH_TO_ARM + "mcr p15, 0, %[mva], c8, c7, 1\n" + ARM_SWITCH_BACK + : ARM_SWITCH_OUTPUT + : [mva] "r" (mva) + ); +} + +static inline void arm_cp15_tlb_instruction_invalidate(void) { ARM_SWITCH_REGISTERS; uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[sbz], c7, c5, 0\n" + "mcr p15, 0, %[sbz], c8, c5, 0\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT : [sbz] "r" (sbz) - : "memory" ); } -static inline void arm_cp15_instruction_cache_invalidate_line(const void *mva) +static inline void arm_cp15_tlb_instruction_invalidate_entry(const void *mva) { ARM_SWITCH_REGISTERS; - mva = ARM_CP15_CACHE_PREPARE_MVA(mva); + mva = ARM_CP15_TLB_PREPARE_MVA(mva); asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[mva], c7, c5, 1\n" + "mcr p15, 0, %[mva], c8, c5, 1\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT : [mva] "r" (mva) - : "memory" ); } -static inline void arm_cp15_instruction_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) +static inline void arm_cp15_tlb_data_invalidate(void) { ARM_SWITCH_REGISTERS; + uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[set_and_way], c7, c5, 2\n" + "mcr p15, 0, %[sbz], c8, c6, 0\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [set_and_way] "r" (set_and_way) - : "memory" + : [sbz] "r" (sbz) ); } -static inline void arm_cp15_instruction_cache_prefetch_line(const void *mva) +static inline void arm_cp15_tlb_data_invalidate_entry(const void *mva) { ARM_SWITCH_REGISTERS; - mva = ARM_CP15_CACHE_PREPARE_MVA(mva); + mva = ARM_CP15_TLB_PREPARE_MVA(mva); asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[mva], c7, c13, 1\n" + "mcr p15, 0, %[mva], c8, c6, 1\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT : [mva] "r" (mva) ); } -static inline void arm_cp15_data_cache_invalidate(void) +static inline void arm_cp15_tlb_lockdown_entry(const void *mva) { - ARM_SWITCH_REGISTERS; - uint32_t sbz = 0; + uint32_t arm_switch_reg; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[sbz], c7, c6, 0\n" + "add %[arm_switch_reg], pc, #16\n" + "mcr p15, 0, %[arm_switch_reg], c7, c13, 1\n" + "mcr p15, 0, %[mva], c8, c7, 1\n" + "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" + "orr %[arm_switch_reg], #0x1\n" + "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" + "ldr %[mva], [%[mva]]\n" + "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" + "bic %[arm_switch_reg], #0x1\n" + "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" ARM_SWITCH_BACK - : ARM_SWITCH_OUTPUT - : [sbz] "r" (sbz) - : "memory" + : [mva] "=r" (mva), [arm_switch_reg] "=&r" (arm_switch_reg) + : "[mva]" (mva) ); } -static inline void arm_cp15_data_cache_invalidate_line(const void *mva) +/** @} */ + +/** + * @name Cache Functions + * + * @{ + */ + +static inline uint32_t arm_cp15_get_cache_type(void) { ARM_SWITCH_REGISTERS; + uint32_t val; - mva = ARM_CP15_CACHE_PREPARE_MVA(mva); + asm volatile ( + ARM_SWITCH_TO_ARM + "mrc p15, 0, %[val], c0, c0, 1\n" + ARM_SWITCH_BACK + : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT + ); + + return val; +} + +static inline void arm_cp15_cache_invalidate(void) +{ + ARM_SWITCH_REGISTERS; + uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[mva], c7, c6, 1\n" + "mcr p15, 0, %[sbz], c7, c7, 0\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [mva] "r" (mva) + : [sbz] "r" (sbz) : "memory" ); } -static inline void arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) +static inline void arm_cp15_instruction_cache_invalidate(void) { ARM_SWITCH_REGISTERS; + uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[set_and_way], c7, c6, 2\n" + "mcr p15, 0, %[sbz], c7, c5, 0\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [set_and_way] "r" (set_and_way) + : [sbz] "r" (sbz) : "memory" ); } -static inline void arm_cp15_data_cache_clean_line(const void *mva) +static inline void arm_cp15_instruction_cache_invalidate_line(const void *mva) { ARM_SWITCH_REGISTERS; @@ -411,7 +481,7 @@ static inline void arm_cp15_data_cache_clean_line(const void *mva) asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[mva], c7, c10, 1\n" + "mcr p15, 0, %[mva], c7, c5, 1\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT : [mva] "r" (mva) @@ -419,13 +489,13 @@ static inline void arm_cp15_data_cache_clean_line(const void *mva) ); } -static inline void arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way) +static inline void arm_cp15_instruction_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) { ARM_SWITCH_REGISTERS; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[set_and_way], c7, c10, 2\n" + "mcr p15, 0, %[set_and_way], c7, c5, 2\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT : [set_and_way] "r" (set_and_way) @@ -433,209 +503,191 @@ static inline void arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_an ); } -static inline void arm_cp15_data_cache_test_and_clean(void) +static inline void arm_cp15_instruction_cache_prefetch_line(const void *mva) { ARM_SWITCH_REGISTERS; + mva = ARM_CP15_CACHE_PREPARE_MVA(mva); + asm volatile ( ARM_SWITCH_TO_ARM - "1:\n" - "mrc p15, 0, r15, c7, c10, 3\n" - "bne 1b\n" + "mcr p15, 0, %[mva], c7, c13, 1\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : - : "memory" + : [mva] "r" (mva) ); } -static inline void arm_cp15_data_cache_clean_and_invalidate_line(const void *mva) +static inline void arm_cp15_data_cache_invalidate(void) { ARM_SWITCH_REGISTERS; - - mva = ARM_CP15_CACHE_PREPARE_MVA(mva); + uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[mva], c7, c14, 1\n" + "mcr p15, 0, %[sbz], c7, c6, 0\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [mva] "r" (mva) + : [sbz] "r" (sbz) : "memory" ); } -static inline void arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(uint32_t set_and_way) +static inline void arm_cp15_data_cache_invalidate_line(const void *mva) { ARM_SWITCH_REGISTERS; + mva = ARM_CP15_CACHE_PREPARE_MVA(mva); + asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[set_and_way], c7, c14, 2\n" + "mcr p15, 0, %[mva], c7, c6, 1\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [set_and_way] "r" (set_and_way) + : [mva] "r" (mva) : "memory" ); } -static inline void arm_cp15_data_cache_test_and_clean_and_invalidate(void) +static inline void arm_cp15_data_cache_invalidate_line_by_set_and_way(uint32_t set_and_way) { ARM_SWITCH_REGISTERS; asm volatile ( ARM_SWITCH_TO_ARM - "1:\n" - "mrc p15, 0, r15, c7, c14, 3\n" - "bne 1b\n" + "mcr p15, 0, %[set_and_way], c7, c6, 2\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : + : [set_and_way] "r" (set_and_way) : "memory" ); } -static inline void arm_cp15_drain_write_buffer(void) +static inline void arm_cp15_data_cache_clean_line(const void *mva) { ARM_SWITCH_REGISTERS; - uint32_t sbz = 0; + + mva = ARM_CP15_CACHE_PREPARE_MVA(mva); asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[sbz], c7, c10, 4\n" + "mcr p15, 0, %[mva], c7, c10, 1\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [sbz] "r" (sbz) + : [mva] "r" (mva) : "memory" ); } -static inline void arm_cp15_wait_for_interrupt(void) +static inline void arm_cp15_data_cache_clean_line_by_set_and_way(uint32_t set_and_way) { ARM_SWITCH_REGISTERS; - uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[sbz], c7, c0, 4\n" + "mcr p15, 0, %[set_and_way], c7, c10, 2\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [sbz] "r" (sbz) + : [set_and_way] "r" (set_and_way) : "memory" ); } -#define ARM_CP15_TLB_PREPARE_MVA(mva) \ - ((const void *) (((uint32_t) (mva)) & ~0x3fU)) - -static inline void arm_cp15_tlb_invalidate(void) +static inline void arm_cp15_data_cache_test_and_clean(void) { ARM_SWITCH_REGISTERS; - uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[sbz], c8, c7, 0\n" + "1:\n" + "mrc p15, 0, r15, c7, c10, 3\n" + "bne 1b\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [sbz] "r" (sbz) + : + : "memory" ); } -static inline void arm_cp15_tlb_invalidate_entry(const void *mva) +static inline void arm_cp15_data_cache_clean_and_invalidate_line(const void *mva) { ARM_SWITCH_REGISTERS; - mva = ARM_CP15_TLB_PREPARE_MVA(mva); + mva = ARM_CP15_CACHE_PREPARE_MVA(mva); asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[mva], c8, c7, 1\n" + "mcr p15, 0, %[mva], c7, c14, 1\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT : [mva] "r" (mva) + : "memory" ); } -static inline void arm_cp15_tlb_instruction_invalidate(void) +static inline void arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way(uint32_t set_and_way) { ARM_SWITCH_REGISTERS; - uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[sbz], c8, c5, 0\n" + "mcr p15, 0, %[set_and_way], c7, c14, 2\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [sbz] "r" (sbz) + : [set_and_way] "r" (set_and_way) + : "memory" ); } -static inline void arm_cp15_tlb_instruction_invalidate_entry(const void *mva) +static inline void arm_cp15_data_cache_test_and_clean_and_invalidate(void) { ARM_SWITCH_REGISTERS; - mva = ARM_CP15_TLB_PREPARE_MVA(mva); - asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[mva], c8, c5, 1\n" + "1:\n" + "mrc p15, 0, r15, c7, c14, 3\n" + "bne 1b\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [mva] "r" (mva) + : + : "memory" ); } -static inline void arm_cp15_tlb_data_invalidate(void) +/** @} */ + +static inline void arm_cp15_drain_write_buffer(void) { ARM_SWITCH_REGISTERS; uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[sbz], c8, c6, 0\n" + "mcr p15, 0, %[sbz], c7, c10, 4\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT : [sbz] "r" (sbz) + : "memory" ); } -static inline void arm_cp15_tlb_data_invalidate_entry(const void *mva) +static inline void arm_cp15_wait_for_interrupt(void) { ARM_SWITCH_REGISTERS; - - mva = ARM_CP15_TLB_PREPARE_MVA(mva); + uint32_t sbz = 0; asm volatile ( ARM_SWITCH_TO_ARM - "mcr p15, 0, %[mva], c8, c6, 1\n" + "mcr p15, 0, %[sbz], c7, c0, 4\n" ARM_SWITCH_BACK : ARM_SWITCH_OUTPUT - : [mva] "r" (mva) + : [sbz] "r" (sbz) + : "memory" ); } -static inline void arm_cp15_tlb_lockdown_entry(const void *mva) -{ - uint32_t arm_switch_reg; - - asm volatile ( - ARM_SWITCH_TO_ARM - "add %[arm_switch_reg], pc, #16\n" - "mcr p15, 0, %[arm_switch_reg], c7, c13, 1\n" - "mcr p15, 0, %[mva], c8, c7, 1\n" - "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" - "orr %[arm_switch_reg], #0x1\n" - "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" - "ldr %[mva], [%[mva]]\n" - "mrc p15, 0, %[arm_switch_reg], c10, c0, 0\n" - "bic %[arm_switch_reg], #0x1\n" - "mcr p15, 0, %[arm_switch_reg], c10, c0, 0\n" - ARM_SWITCH_BACK - : [mva] "=r" (mva), [arm_switch_reg] "=&r" (arm_switch_reg) - : "[mva]" (mva) - ); -} +/** @} */ #ifdef __cplusplus } -- cgit v1.2.3