From 552d4a9ce576cd58e6143c999f4362e821349bba Mon Sep 17 00:00:00 2001 From: Daniel Hellstrom Date: Wed, 6 Mar 2013 15:08:31 +0100 Subject: GRPCI: initialize cache-line-size and latency timer In some GRPCI cores not setting the cache line size could result in long prefetches on the AMBA bus which would lead to bad performance when doing PCI reads to GRPCI target interface (DMA). --- c/src/lib/libbsp/sparc/shared/pci/grpci.c | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'c/src') diff --git a/c/src/lib/libbsp/sparc/shared/pci/grpci.c b/c/src/lib/libbsp/sparc/shared/pci/grpci.c index 0b781d3bdf..eb188bbae1 100644 --- a/c/src/lib/libbsp/sparc/shared/pci/grpci.c +++ b/c/src/lib/libbsp/sparc/shared/pci/grpci.c @@ -449,6 +449,13 @@ int grpci_hw_init(struct grpci_priv *priv) /* Translate I/O accesses 1:1 */ priv->regs->iomap = priv->pci_io & 0xffff0000; + /* Setup Latency Timer and cache line size. Default cache line + * size will result in poor performance (256 word fetches), 0xff + * will set it according to the max size of the PCI FIFO. + */ + grpci_cfg_w8(host, PCI_CACHE_LINE_SIZE, 0xff); + grpci_cfg_w8(host, PCI_LATENCY_TIMER, 0x40); + /* set as bus master and enable pci memory responses */ grpci_cfg_r32(host, PCI_COMMAND, &data); data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); -- cgit v1.2.3