From f198c63d6a1d172aef422353e42b41f8cb128275 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Fri, 6 Sep 1996 18:11:41 +0000 Subject: new file for MIPS port by Craig Lebakken (lebakken@minn.net) and Derrick Ostertag (ostertag@transition.com). --- c/src/lib/libbsp/mips/p4000/README | 47 ++ c/src/lib/libbsp/mips/p4000/console/console.c | 270 ++++++ c/src/lib/libbsp/mips/p4000/console/led.S | 20 + c/src/lib/libbsp/mips/p4000/include/bsp.h | 120 +++ c/src/lib/libbsp/mips/p4000/include/coverhd.h | 116 +++ c/src/lib/libbsp/mips/p4000/liblnk/lnklib.S | 58 ++ c/src/lib/libbsp/mips/p4000/start/start.S | 298 +++++++ c/src/lib/libbsp/mips/p4000/startup/bspclean.c | 30 + c/src/lib/libbsp/mips/p4000/startup/ghlinkcmds | 15 + c/src/lib/libbsp/mips/p4000/startup/idtmem.S | 938 +++++++++++++++++++++ c/src/lib/libbsp/mips/p4000/startup/linkcmds | 69 ++ c/src/lib/libbsp/mips/p4000/startup/setvec.c | 51 ++ c/src/lib/libbsp/mips/p4000/times | 200 +++++ c/src/lib/libbsp/mips64orion/p4000/README | 47 ++ .../lib/libbsp/mips64orion/p4000/console/console.c | 270 ++++++ c/src/lib/libbsp/mips64orion/p4000/console/led.S | 20 + c/src/lib/libbsp/mips64orion/p4000/include/bsp.h | 120 +++ .../lib/libbsp/mips64orion/p4000/include/coverhd.h | 116 +++ c/src/lib/libbsp/mips64orion/p4000/liblnk/lnklib.S | 58 ++ c/src/lib/libbsp/mips64orion/p4000/start/start.S | 298 +++++++ .../libbsp/mips64orion/p4000/startup/bspclean.c | 30 + .../libbsp/mips64orion/p4000/startup/ghlinkcmds | 15 + .../lib/libbsp/mips64orion/p4000/startup/idtmem.S | 938 +++++++++++++++++++++ .../lib/libbsp/mips64orion/p4000/startup/linkcmds | 69 ++ .../lib/libbsp/mips64orion/p4000/startup/setvec.c | 51 ++ c/src/lib/libbsp/mips64orion/p4000/times | 200 +++++ c/src/lib/libcpu/mips/clock/ckinit.c | 245 ++++++ c/src/lib/libcpu/mips/clock/clock.S | 44 + c/src/lib/libcpu/mips/clock/clock.h | 24 + c/src/lib/libcpu/mips/timer/gettime.S | 34 + c/src/lib/libcpu/mips/timer/timer.c | 136 +++ c/src/lib/libcpu/mips64orion/clock/ckinit.c | 245 ++++++ c/src/lib/libcpu/mips64orion/clock/clock.S | 44 + c/src/lib/libcpu/mips64orion/clock/clock.h | 24 + c/src/lib/libcpu/mips64orion/timer/gettime.S | 34 + c/src/lib/libcpu/mips64orion/timer/timer.c | 136 +++ c/src/lib/start/mips64orion/idt_csu.S | 298 +++++++ 37 files changed, 5728 insertions(+) create mode 100644 c/src/lib/libbsp/mips/p4000/README create mode 100644 c/src/lib/libbsp/mips/p4000/console/console.c create mode 100644 c/src/lib/libbsp/mips/p4000/console/led.S create mode 100644 c/src/lib/libbsp/mips/p4000/include/bsp.h create mode 100644 c/src/lib/libbsp/mips/p4000/include/coverhd.h create mode 100644 c/src/lib/libbsp/mips/p4000/liblnk/lnklib.S create mode 100644 c/src/lib/libbsp/mips/p4000/start/start.S create mode 100644 c/src/lib/libbsp/mips/p4000/startup/bspclean.c create mode 100644 c/src/lib/libbsp/mips/p4000/startup/ghlinkcmds create mode 100644 c/src/lib/libbsp/mips/p4000/startup/idtmem.S create mode 100644 c/src/lib/libbsp/mips/p4000/startup/linkcmds create mode 100644 c/src/lib/libbsp/mips/p4000/startup/setvec.c create mode 100644 c/src/lib/libbsp/mips/p4000/times create mode 100644 c/src/lib/libbsp/mips64orion/p4000/README create mode 100644 c/src/lib/libbsp/mips64orion/p4000/console/console.c create mode 100644 c/src/lib/libbsp/mips64orion/p4000/console/led.S create mode 100644 c/src/lib/libbsp/mips64orion/p4000/include/bsp.h create mode 100644 c/src/lib/libbsp/mips64orion/p4000/include/coverhd.h create mode 100644 c/src/lib/libbsp/mips64orion/p4000/liblnk/lnklib.S create mode 100644 c/src/lib/libbsp/mips64orion/p4000/start/start.S create mode 100644 c/src/lib/libbsp/mips64orion/p4000/startup/bspclean.c create mode 100644 c/src/lib/libbsp/mips64orion/p4000/startup/ghlinkcmds create mode 100644 c/src/lib/libbsp/mips64orion/p4000/startup/idtmem.S create mode 100644 c/src/lib/libbsp/mips64orion/p4000/startup/linkcmds create mode 100644 c/src/lib/libbsp/mips64orion/p4000/startup/setvec.c create mode 100644 c/src/lib/libbsp/mips64orion/p4000/times create mode 100644 c/src/lib/libcpu/mips/clock/ckinit.c create mode 100644 c/src/lib/libcpu/mips/clock/clock.S create mode 100644 c/src/lib/libcpu/mips/clock/clock.h create mode 100644 c/src/lib/libcpu/mips/timer/gettime.S create mode 100644 c/src/lib/libcpu/mips/timer/timer.c create mode 100644 c/src/lib/libcpu/mips64orion/clock/ckinit.c create mode 100644 c/src/lib/libcpu/mips64orion/clock/clock.S create mode 100644 c/src/lib/libcpu/mips64orion/clock/clock.h create mode 100644 c/src/lib/libcpu/mips64orion/timer/gettime.S create mode 100644 c/src/lib/libcpu/mips64orion/timer/timer.c create mode 100644 c/src/lib/start/mips64orion/idt_csu.S (limited to 'c/src/lib') diff --git a/c/src/lib/libbsp/mips/p4000/README b/c/src/lib/libbsp/mips/p4000/README new file mode 100644 index 0000000000..31152f15ec --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/README @@ -0,0 +1,47 @@ +# +# README,v 1.2 1995/05/31 16:56:03 joel Exp +# +# @(#)README 08/20/96 1.2 +# + +BSP NAME: p4000 +BOARD: Algorithmics P4000 SBC +BUS: N/A +CPU FAMILY: mips +CPU: IDT 4650 +COPROCESSORS: N/A +MODE: 32 bit mode + +DEBUG MONITOR: IDT/SIM + +PERIPHERALS +=========== +TIMERS: 4650 internal + RESOLUTION: half of internal clock frequency +SERIAL PORTS: IDT/SIM controlled +REAL-TIME CLOCK: none +DMA: none +VIDEO: none +SCSI: none +NETWORKING: none + +DRIVER INFORMATION +================== +CLOCK DRIVER: 4650 internal +IOSUPP DRIVER: N/A +SHMSUPP: N/A +TIMER DRIVER: 4650 internal +TTY DRIVER: uses IDT/SIM + +STDIO +===== +PORT: Console port 0 +ELECTRICAL: RS-232 +BAUD: 9600 +BITS PER CHARACTER: 8 +PARITY: None +STOP BITS: 1 + +NOTES +===== + diff --git a/c/src/lib/libbsp/mips/p4000/console/console.c b/c/src/lib/libbsp/mips/p4000/console/console.c new file mode 100644 index 0000000000..cc52dc3c7c --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/console/console.c @@ -0,0 +1,270 @@ +/* + * This file contains the IDT 4650 console IO package. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/console/console.c: + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * console.c,v 1.4 1995/12/05 19:23:02 joel Exp + */ + + +#ifndef lint +static char _sccsid[] = "@(#)console.c 08/20/96 1.6\n"; +#endif + + +#include +#include +#include + +char idtsim_getchar( void ); +void idtsim_putchar( char c ); +void mips_leddisplay( char a, char b, char c, char d ); + + +/* console_initialize + * + * This routine initializes the console IO driver. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + */ + +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code status; + + status = rtems_io_register_name( + "/dev/console", + major, + (rtems_device_minor_number) 0 + ); + + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred(status); + + return RTEMS_SUCCESSFUL; +} + + +/* is_character_ready + * + * This routine returns TRUE if a character is available. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + */ + +rtems_boolean is_character_ready( + char *ch +) +{ + *ch = '\0'; /* return NULL for no particular reason */ + return(TRUE); +} + +/* inbyte + * + * This routine reads a character from the SOURCE. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + * character read from SOURCE + */ + +char inbyte( void ) +{ + /* + * If polling, wait until a character is available. + */ + + return idtsim_getchar(); +} + +/* outbyte + * + * This routine transmits a character out the SOURCE. It may support + * XON/XOFF flow control. + * + * Input parameters: + * ch - character to be transmitted + * + * Output parameters: NONE + */ + +void outbyte( + char ch +) +{ +#define NUM_LEDS 4 + static unsigned int cur_led = 0; + static unsigned char led_chars[NUM_LEDS]; + + /* + * If polling, wait for the transmitter to be ready. + * Check for flow control requests and process. + * Then output the character. + */ + + idtsim_putchar( ch ); + + /* print out first four alpha numeric characters in a line */ + if ( ch == '\n' ) + { + mips_leddisplay( led_chars[0], led_chars[1], led_chars[2], led_chars[3] ); + cur_led = 0; + } + else if ( isalnum( ch ) && cur_led < NUM_LEDS ) + { + led_chars[cur_led++] = ch; + } + +} + + +static int console_fd = -1; + +/* + * Open entry point + */ + +rtems_device_driver console_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ +#if 0 + int console_fd = open("tty0", 2); /* open for read/write */ +#endif + return RTEMS_SUCCESSFUL; +} + +/* + * Close entry point + */ + +rtems_device_driver console_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ +#if 0 + if ( console_fd ) + close( console_fd ); +#endif + return RTEMS_SUCCESSFUL; +} + +/* + * read bytes from the serial port. We only have stdin. + */ + +rtems_device_driver console_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + rtems_libio_rw_args_t *rw_args; + char *buffer; + int maximum; + int count = 0; + + rw_args = (rtems_libio_rw_args_t *) arg; + + buffer = rw_args->buffer; + maximum = rw_args->count; + + for (count = 0; count < maximum; count++) { + buffer[ count ] = inbyte(); + if (buffer[ count ] == '\n' || buffer[ count ] == '\r') { + buffer[ count++ ] = '\n'; + buffer[ count ] = 0; + break; + } + } + + rw_args->bytes_moved = count; + return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; +} + +/* + * write bytes to the serial port. Stdout and stderr are the same. + */ + +rtems_device_driver console_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + int count; + int maximum; + rtems_libio_rw_args_t *rw_args; + char *buffer; + + rw_args = (rtems_libio_rw_args_t *) arg; + + buffer = rw_args->buffer; + maximum = rw_args->count; + + for (count = 0; count < maximum; count++) { + if ( buffer[ count ] == '\n') { + outbyte('\r'); + } + outbyte( buffer[ count ] ); + } + + rw_args->bytes_moved = maximum; + return 0; +} + +/* + * IO Control entry point + */ + +rtems_device_driver console_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + return RTEMS_SUCCESSFUL; +} diff --git a/c/src/lib/libbsp/mips/p4000/console/led.S b/c/src/lib/libbsp/mips/p4000/console/led.S new file mode 100644 index 0000000000..b9b7b7e294 --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/console/led.S @@ -0,0 +1,20 @@ + +#include +#include +#include + + +FRAME(mips_leddisplay,sp,0,ra) + j ra + nop +ENDFRAME(mips_leddisplay) + +FRAME(sbddisplay,sp,0,ra) + j ra +ENDFRAME(sbddisplay) + + +FRAME(sbdblank,sp,0,ra) + j ra +ENDFRAME(sbdblank) + diff --git a/c/src/lib/libbsp/mips/p4000/include/bsp.h b/c/src/lib/libbsp/mips/p4000/include/bsp.h new file mode 100644 index 0000000000..1a9f6a5653 --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/include/bsp.h @@ -0,0 +1,120 @@ +/* bsp.h + * + * This include file contains all board IO definitions. + * + * XXX : put yours in here + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * bsp.h,v 1.4 1995/09/11 19:29:04 joel Exp + */ +/* @(#)bsp.h 03/15/96 1.1 */ + +#ifndef __NO_BSP_h +#define __NO_BSP_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +extern void WriteDisplay( char * string ); + +/* + * Define the time limits for RTEMS Test Suite test durations. + * Long test and short test duration limits are provided. These + * values are in seconds and need to be converted to ticks for the + * application. + * + */ + +#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ +#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 ) + +#define Cause_tm27_intr() + +#define Clear_tm27_intr() + +#define Lower_tm27_intr() + +extern unsigned32 mips_get_timer( void ); + +#define CPU_CLOCK_RATE_MHZ (50) +#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */ + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define delay( microseconds ) \ + { \ + unsigned32 _end_clock = mips_get_timer() + microseconds * CLOCKS_PER_MICROSECOND; \ + _end_clock %= 0x100000000; /* make sure result is 32 bits */ \ + \ + /* handle timer overflow, if necessary */ \ + while ( _end_clock < mips_get_timer() ); \ + \ + while ( _end_clock > mips_get_timer() ); \ + } + +/* Constants */ + +#define RAM_START 0 +#define RAM_END 0x100000 + +/* miscellaneous stuff assumed to exist */ + +extern rtems_configuration_table BSP_Configuration; + +/* + * Device Driver Table Entries + */ + +/* + * NOTE: Use the standard Console driver entry + */ + +/* + * NOTE: Use the standard Clock driver entry + */ + +/* + * How many libio files we want + */ + +#define BSP_LIBIO_MAX_FDS 20 + +/* functions */ + +void bsp_cleanup( void ); + +mips_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/mips/p4000/include/coverhd.h b/c/src/lib/libbsp/mips/p4000/include/coverhd.h new file mode 100644 index 0000000000..716faef06b --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/include/coverhd.h @@ -0,0 +1,116 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include all + * all calling overhead including passing of arguments. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * coverhd.h,v 1.2 1995/05/31 16:56:15 joel Exp + */ +/* @(#)coverhd.h 04/08/96 1.3 */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 5 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4 +#define CALLING_OVERHEAD_TASK_CREATE 6 +#define CALLING_OVERHEAD_TASK_IDENT 4 +#define CALLING_OVERHEAD_TASK_START 5 +#define CALLING_OVERHEAD_TASK_RESTART 4 +#define CALLING_OVERHEAD_TASK_DELETE 4 +#define CALLING_OVERHEAD_TASK_SUSPEND 4 +#define CALLING_OVERHEAD_TASK_RESUME 4 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5 +#define CALLING_OVERHEAD_TASK_MODE 4 +#define CALLING_OVERHEAD_TASK_GET_NOTE 5 +#define CALLING_OVERHEAD_TASK_SET_NOTE 5 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 9 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 5 +#define CALLING_OVERHEAD_CLOCK_GET 9 +#define CALLING_OVERHEAD_CLOCK_SET 8 +#define CALLING_OVERHEAD_CLOCK_TICK 3 + +#define CALLING_OVERHEAD_TIMER_CREATE 4 +#define CALLING_OVERHEAD_TIMER_IDENT 4 +#define CALLING_OVERHEAD_TIMER_DELETE 4 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 10 +#define CALLING_OVERHEAD_TIMER_RESET 4 +#define CALLING_OVERHEAD_TIMER_CANCEL 4 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 5 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 4 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 4 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 4 + +#define CALLING_OVERHEAD_EVENT_SEND 4 +#define CALLING_OVERHEAD_EVENT_RECEIVE 5 +#define CALLING_OVERHEAD_SIGNAL_CATCH 5 +#define CALLING_OVERHEAD_SIGNAL_SEND 4 +#define CALLING_OVERHEAD_PARTITION_CREATE 6 +#define CALLING_OVERHEAD_PARTITION_IDENT 4 +#define CALLING_OVERHEAD_PARTITION_DELETE 4 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 4 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 4 +#define CALLING_OVERHEAD_REGION_CREATE 6 +#define CALLING_OVERHEAD_REGION_IDENT 4 +#define CALLING_OVERHEAD_REGION_DELETE 4 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 5 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 4 +#define CALLING_OVERHEAD_PORT_CREATE 6 +#define CALLING_OVERHEAD_PORT_IDENT 4 +#define CALLING_OVERHEAD_PORT_DELETE 4 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 4 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 4 + +#define CALLING_OVERHEAD_IO_INITIALIZE 5 +#define CALLING_OVERHEAD_IO_OPEN 5 +#define CALLING_OVERHEAD_IO_CLOSE 5 +#define CALLING_OVERHEAD_IO_READ 5 +#define CALLING_OVERHEAD_IO_WRITE 5 +#define CALLING_OVERHEAD_IO_CONTROL 5 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3 + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/mips/p4000/liblnk/lnklib.S b/c/src/lib/libbsp/mips/p4000/liblnk/lnklib.S new file mode 100644 index 0000000000..fb8f28edbc --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/liblnk/lnklib.S @@ -0,0 +1,58 @@ +#include "iregdef.h" +#include "idtcpu.h" + +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl name; \ + .ent name; \ +name:; \ + .frame frm_reg,offset,ret_reg + +#define ENDFRAME(name) \ + .end name + +#define PROM_LINK(name,entry) \ + .globl name; \ + .ent name; \ +name: la $2,+entry; \ + j $2; \ + .end name + +#define PROM_ENTRY(x) (0xbfc00000+((x)*8)) + +#define PROM_RESET PROM_ENTRY(0) +#define PROM_NOT_IMP PROM_ENTRY(1) +#define PROM_RESTART PROM_ENTRY(2) +#define PROM_REINIT PROM_ENTRY(3) +#define PROM_GETCHAR PROM_ENTRY(11) +#define PROM_PUTCHAR PROM_ENTRY(12) +#define PROM_SHOWCHAR PROM_ENTRY(13) +#define PROM_PRINTF PROM_ENTRY(16) +#define PROM_RETURN PROM_ENTRY(17) + +#define PROM_RGETS PROM_ENTRY(25) +#define PROM_FLUSHCACHE PROM_ENTRY(28) +#define PROM_CLEARCACHE PROM_ENTRY(29) +#define PROM_SETJMP PROM_ENTRY(30) +#define PROM_LONGJMP PROM_ENTRY(31) + + .text + +PROM_LINK(idtsim_putchar, PROM_PUTCHAR) +PROM_LINK(idtsim_getchar, PROM_GETCHAR) +PROM_LINK(idtsim_showchar, PROM_SHOWCHAR) +PROM_LINK(idtsim__exit, PROM_RETURN) +PROM_LINK(idtsim_reinit, PROM_REINIT) +PROM_LINK(idtsim_restart, PROM_RESTART) +PROM_LINK(idtsim_reset, PROM_RESET) +PROM_LINK(idtsim_promexit, PROM_RETURN) +PROM_LINK(idtsim_setjmp, PROM_SETJMP) +PROM_LINK(idtsim_longjmp, PROM_LONGJMP) + +FRAME(idtsim_init_sbrk,sp,0,ra) + j ra +ENDFRAME(idtsim_init_sbrk) + +FRAME(idtsim_init_file,sp,0,ra) + j ra +ENDFRAME(idtsim_init_file) + diff --git a/c/src/lib/libbsp/mips/p4000/start/start.S b/c/src/lib/libbsp/mips/p4000/start/start.S new file mode 100644 index 0000000000..bbedf0c5dd --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/start/start.S @@ -0,0 +1,298 @@ +/* + +Based upon IDT provided code with the following release: + +This source code has been made available to you by IDT on an AS-IS +basis. Anyone receiving this source is licensed under IDT copyrights +to use it in any way he or she deems fit, including copying it, +modifying it, compiling it, and redistributing it either with or +without modifications. No license under IDT patents or patent +applications is to be implied by the copyright license. + +Any user of this software should understand that IDT cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work must +include the IDT copyright notice, this paragraph, and the preceeding +two paragraphs in the transferred software. + +COPYRIGHT IDT CORPORATION 1996 +LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + +*/ + +/************************************************************************* +** +** Copyright 1991-95 Integrated Device Technology, Inc. +** All Rights Reserved +** +** idt_csu.S -- IDT stand alone startup code +** +**************************************************************************/ +#include +#include +#include + + +.extern _fbss,4 /* this is defined by the linker */ +.extern end,4 /* this is defined by the linker */ + +.lcomm sim_mem_cfg_struct,12 + + .text + + +#define TMP_STKSIZE 1024 + +/************************************************************************** +** +** start - Typicl standalone start up code required for R3000/R4000 +** +** +** 1) Initialize the STATUS Register +** a) Clear parity error bit +** b) Set co_processor 1 usable bit ON +** c) Clear all IntMask Enables +** d) Set kernel/disabled mode +** 2) Initialize Cause Register +** a) clear software interrupt bits +** 3) Determine FPU installed or not +** if not, clear CoProcessor 1 usable bit +** 4) Clear bss area +** 5) MUST allocate temporary stack until memory size determined +** It MUST be uncached to prevent overwriting when caches are cleared +** 6) Install exception handlers +** 7) Determine memory and cache sizes +** 8) Establish permanent stack (cached or uncached as defined by bss) +** 9) Flush Instruction and Data caches +** 10) If there is a Translation Lookaside Buffer, Clear the TLB +** 11) Execute initialization code if the IDT/c library is to be used +** +** 12) Jump to user's "main()" +** 13) Jump to promexit +** +** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. +** This is used to mark code specific to R3xxx or R4xxx processors. +** IDT/C 6.x defines __mips to be the ISA level for which we're +** generating code. This is used to make sure the stack etc. is +** double word aligned, when using -mips3 (default) or -mips2, +** when compiling with IDT/C6.x +** +***************************************************************************/ + +FRAME(start,sp,0,ra) + + .set noreorder +#ifdef _R3000 + li v0,SR_PE|SR_CU1 /* reset parity error and set */ + /* cp1 usable */ +#endif +#ifdef _R4000 +#if __mips==3 || defined(R4650) + li v0,SR_CU1|SR_DE|SR_FR /* initally clear ERL, enable FPA 64bit regs*/ + /* 4650: Need fr to be set anyway */ +#else + li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPA 32bit regs*/ +#endif mips3 +#endif + + mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ + nop + mtc0 zero,C0_CAUSE /* clear software interrupts */ + nop + +#ifdef _R4000 + li v0,CFG_C_NONCOHERENT # initialise default cache mode + mtc0 v0,C0_CONFIG +#endif + +/* +** check to see if an fpu is really plugged in +*/ + li t3,0xaaaa5555 /* put a's and 5's in t3 */ + mtc1 t3,fp0 /* try to write them into fp0 */ + mtc1 zero,fp1 /* try to write zero in fp */ + mfc1 t0,fp0 + mfc1 t1,fp1 + nop + bne t0,t3,1f /* branch if no match */ + nop + bne t1,zero,1f /* double check for positive id */ + nop + /* We have a FPU. clear fcsr */ + ctc1 zero, fcr31 + j 2f /* status register already correct */ + nop +1: +#ifdef _R3000 + li v0, SR_PE /* reset parity error/NO cp1 usable */ +#endif + +#ifdef _R4000 + li v0,SR_DE /* clear ERL and disable FPA */ +#endif + + mtc0 v0, C0_SR /* reset status register */ +2: + la gp, _gp + + la v0,_fbss /* clear bss before using it */ + la v1,end /* end of bss */ +3: sw zero,0(v0) + bltu v0,v1,3b + add v0,4 + + +/************************************************************************ +** +** Temporary Stack - needed to handle stack saves until +** memory size is determined and permanent stack set +** +** MUST be uncached to avoid confusion at cache +** switching during memory sizing +** +*************************************************************************/ +#if __mips==3 + /* For MIPS 3, we need to be sure that the stack is aligned on a + * double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 11f /* Last three bits Zero, already aligned */ + nop + add v0, 4 +11: +#endif + + or v0, K1BASE /* switch to uncached */ + add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ + sub v1, v1, (4*4) /* overhead */ + move sp, v1 /* set sp to top of stack */ +4: sw zero, 0(v0) + bltu v0, v1, 4b /* clear out temp stack */ + add v0, 4 + + jal init_exc_vecs /* install exception handlers */ + nop /* MUST do before memory probes */ + + la v0, 5f + li v1, K1BASE /* force into uncached space */ + or v0, v1 /* during memory/cache probes */ + j v0 + nop +5: + la a0, sim_mem_cfg_struct + jal sim_mem_cfg /* Make SIM call to get mem size */ + nop + la a0, sim_mem_cfg_struct + lw a0, 0(a0) /* Get memory size from struct */ +#ifdef _R3000 + jal config_Icache + nop + jal config_Dcache /* determine size of D & I caches */ + nop +#endif +#ifdef _R4000 + jal config_cache /* determine size of D & I caches */ + nop +#endif + + move v0, a0 /* mem_size */ + +#if __mips==3 + /* For MIPS 3, we need to be sure that the stack (and hence v0 + * here) is aligned on a double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 12f /* Last three bits Zero, already aligned */ + nop + subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ +12: +#endif + + + +/************************************************************************** +** +** Permanent Stack - now know top of memory, put permanent stack there +** +***************************************************************************/ + + la t2, _fbss /* cache mode as linked */ + and t2, 0xF0000000 /* isolate segment */ + la t1, 6f + j t1 /* back to original cache mode */ + nop +6: + or v0, t2 /* stack back to original cache mode */ + addiu v0,v0,-16 /* overhead */ + move sp, v0 /* now replace count w top of memory */ + move v1, v0 + subu v1, P_STACKSIZE /* clear requested stack size */ + +7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ + bltu v1,v0,7b + add v1, 4 + .set reorder + +#ifdef _R3000 + jal flush_Icache + jal flush_Dcache /* flush Data & Instruction caches */ +#endif +#ifdef _R4000 + jal flush_cache_nowrite /* flush Data & Instruction caches */ +#endif + + + +/************************************************************************** +** +** If this chip supports a Translation Lookaside Buffer, clear it +** +***************************************************************************/ + + .set noreorder + mfc0 t1, C0_SR /* look at Status Register */ + nop + .set reorder +#ifdef _R3000 + li t2, SR_TS /* TLB Shutdown bit */ + and t1,t2 /* TLB Shutdown if 1 */ + bnez t1, 8f /* skip clearing if no TLB */ +#endif + +#ifndef R4650 + jal init_tlb /* clear the tlb */ +#endif + + +/************************************************************************ +** +** Initialization required if using IDT/c or libc.a, standard C Lib +** +** can SKIP if not necessary for application +** +************************************************************************/ +8: + + jal idtsim_init_sbrk + jal idtsim_init_file +/*********************** END I/O initialization **********************/ + + + jal main + + jal idtsim_promexit + +ENDFRAME(start) + + + .globl sim_mem_cfg +sim_mem_cfg: + .set noat + .set noreorder + li AT, (0xbfc00000+((55)*8)) + jr AT + nop + .set at + .set reorder diff --git a/c/src/lib/libbsp/mips/p4000/startup/bspclean.c b/c/src/lib/libbsp/mips/p4000/startup/bspclean.c new file mode 100644 index 0000000000..ecaff11004 --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/startup/bspclean.c @@ -0,0 +1,30 @@ +/* bsp_cleanup() + * + * This routine normally is part of start.s and usually returns + * control to a monitor. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * bspclean.c,v 1.2 1995/05/31 16:56:27 joel Exp + */ +#ifndef lint +static char _sccsid[] = "@(#)bspclean.c 03/15/96 1.1\n"; +#endif + + +#include +#include + +void bsp_cleanup( void ) +{ +} diff --git a/c/src/lib/libbsp/mips/p4000/startup/ghlinkcmds b/c/src/lib/libbsp/mips/p4000/startup/ghlinkcmds new file mode 100644 index 0000000000..cf2a80bf8d --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/startup/ghlinkcmds @@ -0,0 +1,15 @@ +-map +-sec +{ + .text 0x80010000 : + .data align(16) : + .rodata : + .fini : +# .sdata : + .symtab : + .strtab : + .debug : +# .sbss : + .bss align(8) : + .init 0xbfc00000 : +} diff --git a/c/src/lib/libbsp/mips/p4000/startup/idtmem.S b/c/src/lib/libbsp/mips/p4000/startup/idtmem.S new file mode 100644 index 0000000000..66c1a4ecbc --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/startup/idtmem.S @@ -0,0 +1,938 @@ +/* + +Based upon IDT provided code with the following release: + +This source code has been made available to you by IDT on an AS-IS +basis. Anyone receiving this source is licensed under IDT copyrights +to use it in any way he or she deems fit, including copying it, +modifying it, compiling it, and redistributing it either with or +without modifications. No license under IDT patents or patent +applications is to be implied by the copyright license. + +Any user of this software should understand that IDT cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work must +include the IDT copyright notice, this paragraph, and the preceeding +two paragraphs in the transferred software. + +COPYRIGHT IDT CORPORATION 1996 +LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + +*/ + +/************************************************************************ +** +** idtmem.s - memory and cache functions +** +** Copyright 1991 Integrated Device Technology, Inc. +** All Rights Reserved +** +**************************************************************************/ + +/* + * 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack + * to set mem_size. + */ + +#include "iregdef.h" +#include "idtcpu.h" +#include "idtmon.h" +#include "saunder.h" + + + .data +mem_size: + .word 0 +dcache_size: + .word 0 +icache_size: +#if defined(CPU_R3000) + .word MINCACHE +#endif +#if defined(CPU_R4000) + .word 0 +#endif + +#if defined(CPU_R4000) + .data +scache_size: + .word 0 +icache_linesize: + .word 0 +dcache_linesize: + .word 0 +scache_linesize: + .word 0 +#endif + + + .text + +#if defined (CPU_R3000) +#define CONFIGFRM ((2*4)+4) + +/************************************************************************* +** +** Config_Dcache() -- determine size of Data cache +** +**************************************************************************/ + +FRAME(config_Dcache,sp, CONFIGFRM, ra) + .set noreorder + subu sp,CONFIGFRM + sw ra,CONFIGFRM-4(sp) /* save return address */ + sw s0,4*4(sp) /* save s0 in first regsave slot */ + mfc0 s0,C0_SR /* save SR */ + nop + mtc0 zero,C0_SR /* disable interrupts */ + .set reorder + jal _size_cache /* returns Data cache size in v0 */ + sw v0, dcache_size /* save it */ + and s0, ~SR_PE /* do not clear PE */ + .set noreorder + mtc0 s0,C0_SR /* restore SR */ + nop + .set reorder + lw s0, 4*4(sp) /* restore s0 */ + lw ra,CONFIGFRM-4(sp) /* restore ra */ + addu sp,CONFIGFRM /* pop stack */ + j ra +ENDFRAME(config_Dcache) + + +/************************************************************************* +** +** Config_Icache() -- determine size of Instruction cache +** MUST be run in uncached mode/handled in idt_csu.s +** +**************************************************************************/ + +FRAME(config_Icache,sp, CONFIGFRM, ra) + .set noreorder + subu sp,CONFIGFRM + sw ra,CONFIGFRM-4(sp) /* save return address */ + sw s0,4*4(sp) /* save s0 in first regsave slot */ + mfc0 s0,C0_SR /* save SR */ + nop + mtc0 zero, C0_SR /* disable interrupts */ + li v0,SR_SWC /* swap caches/disable ints */ + mtc0 v0,C0_SR + nop + .set reorder + jal _size_cache /* returns instruction cache size */ + .set noreorder + mtc0 zero,C0_SR /* swap back caches */ + nop + and s0,~SR_PE /* do not inadvertantly clear PE */ + mtc0 s0,C0_SR /* restore SR */ + nop + .set reorder + sw v0, icache_size /* save it AFTER caches back */ + lw s0,4*4(sp) /* restore s0 */ + lw ra,CONFIGFRM-4(sp) /* restore ra */ + addu sp,CONFIGFRM /* pop stack */ + j ra +ENDFRAME(config_Icache) + +/************************************************************************ +** +** _size_cache() +** returns cache size in v0 +** +************************************************************************/ + +FRAME(_size_cache,sp,0,ra) + .set noreorder + mfc0 t0,C0_SR /* save current sr */ + nop + and t0,~SR_PE /* do not inadvertently clear PE */ + or v0,t0,SR_ISC /* isolate cache */ + mtc0 v0,C0_SR + /* + * First check if there is a cache there at all + */ + move v0,zero + li v1,0xa5a5a5a5 /* distinctive pattern */ + sw v1,K0BASE /* try to write into cache */ + lw t1,K0BASE /* try to read from cache */ + nop + mfc0 t2,C0_SR + nop + .set reorder + and t2,SR_CM + bne t2,zero,3f /* cache miss, must be no cache */ + bne v1,t1,3f /* data not equal -> no cache */ + /* + * Clear cache size boundries to known state. + */ + li v0,MINCACHE +1: + sw zero,K0BASE(v0) + sll v0,1 + ble v0,MAXCACHE,1b + + li v0,-1 + sw v0,K0BASE(zero) /* store marker in cache */ + li v0,MINCACHE /* MIN cache size */ + +2: lw v1,K0BASE(v0) /* Look for marker */ + bne v1,zero,3f /* found marker */ + sll v0,1 /* cache size * 2 */ + ble v0,MAXCACHE,2b /* keep looking */ + move v0,zero /* must be no cache */ + .set noreorder +3: mtc0 t0,C0_SR /* restore sr */ + j ra + nop +ENDFRAME(_size_cache) + .set reorder + + +#define FLUSHFRM (2*4) + +/*************************************************************************** +** +** flush_Dcache() - flush entire Data cache +** +****************************************************************************/ +FRAME(flush_Dcache,sp,FLUSHFRM,ra) + lw t2, dcache_size + .set noreorder + mfc0 t3,C0_SR /* save SR */ + nop + and t3,~SR_PE /* dont inadvertently clear PE */ + beq t2,zero,_Dflush_done /* no D cache, get out! */ + nop + li v0, SR_ISC /* isolate cache */ + mtc0 v0, C0_SR + nop + .set reorder + li t0,K0BASE /* set loop registers */ + or t1,t0,t2 + +2: sb zero,0(t0) + sb zero,4(t0) + sb zero,8(t0) + sb zero,12(t0) + sb zero,16(t0) + sb zero,20(t0) + sb zero,24(t0) + addu t0,32 + sb zero,-4(t0) + bne t0,t1,2b + + .set noreorder +_Dflush_done: + mtc0 t3,C0_SR /* restore Status Register */ + .set reorder + j ra +ENDFRAME(flush_Dcache) + + +/*************************************************************************** +** +** flush_Icache() - flush entire Instruction cache +** +** NOTE: Icache can only be flushed/cleared when uncached +** Code forces into uncached memory regardless of calling mode +** +****************************************************************************/ +FRAME(flush_Icache,sp,FLUSHFRM,ra) + lw t1,icache_size + .set noreorder + mfc0 t3,C0_SR /* save SR */ + nop + la v0,1f + li v1,K1BASE + or v0,v1 + j v0 /* force into non-cached space */ + nop +1: + and t3,~SR_PE /* dont inadvertently clear PE */ + beq t1,zero,_Iflush_done /* no i-cache get out */ + nop + li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */ + mtc0 v0,C0_SR + li t0,K0BASE + .set reorder + or t1,t0,t1 + +1: sb zero,0(t0) + sb zero,4(t0) + sb zero,8(t0) + sb zero,12(t0) + sb zero,16(t0) + sb zero,20(t0) + sb zero,24(t0) + addu t0,32 + sb zero,-4(t0) + bne t0,t1,1b + .set noreorder +_Iflush_done: + mtc0 t3,C0_SR /* un-isolate, enable interrupts */ + .set reorder + j ra +ENDFRAME(flush_Icache) + +/************************************************************************** +** +** clear_Dcache(base_addr, byte_count) - flush portion of Data cache +** +** a0 = base address of portion to be cleared +** a1 = byte count of length +** +***************************************************************************/ +FRAME(clear_Dcache,sp,0,ra) + + lw t2, dcache_size /* Data cache size */ + .set noreorder + mfc0 t3,C0_SR /* save SR */ + nop + and t3,~SR_PE /* dont inadvertently clear PE */ + nop + nop + .set reorder + /* + * flush data cache + */ + + .set noreorder + nop + li v0,SR_ISC /* isolate data cache */ + mtc0 v0,C0_SR + .set reorder + bltu t2,a1,1f /* cache is smaller than region */ + move t2,a1 +1: addu t2,a0 /* ending address + 1 */ + move t0,a0 + +1: sb zero,0(t0) + sb zero,4(t0) + sb zero,8(t0) + sb zero,12(t0) + sb zero,16(t0) + sb zero,20(t0) + sb zero,24(t0) + addu t0,32 + sb zero,-4(t0) + bltu t0,t2,1b + + .set noreorder + mtc0 t3,C0_SR /* un-isolate, enable interrupts */ + nop + .set reorder + j ra +ENDFRAME(clear_Dcache) + + +/************************************************************************** +** +** clear_Icache(base_addr, byte_count) - flush portion of Instruction cache +** +** a0 = base address of portion to be cleared +** a1 = byte count of length +** +** NOTE: Icache can only be flushed/cleared when uncached +** Code forces into uncached memory regardless of calling mode +** +***************************************************************************/ +FRAME(clear_Icache,sp,0,ra) + + lw t1, icache_size /* Instruction cache size */ + /* + * flush text cache + */ + .set noreorder + mfc0 t3,C0_SR /* save SR */ + nop + la v0,1f + li v1,K1BASE + or v0,v1 + j v0 /* force into non-cached space */ + nop +1: + and t3,~SR_PE /* dont inadvertently clear PE */ + nop + nop + li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */ + mtc0 v0,C0_SR + .set reorder + bltu t1,a1,1f /* cache is smaller than region */ + move t1,a1 +1: addu t1,a0 /* ending address + 1 */ + move t0,a0 + + sb zero,0(t0) + sb zero,4(t0) + sb zero,8(t0) + sb zero,12(t0) + sb zero,16(t0) + sb zero,20(t0) + sb zero,24(t0) + addu t0,32 + sb zero,-4(t0) + bltu t0,t1,1b + .set noreorder + mtc0 t3,C0_SR /* un-isolate, enable interrupts */ + nop + nop + nop /* allow time for caches to swap */ + .set reorder + j ra +ENDFRAME(clear_Icache) + + +/************************************************************************** +** +** get_mem_conf - get memory configuration +** +***************************************************************************/ + + +FRAME(get_mem_conf,sp,0,ra) + + lw t6, mem_size + sw t6, 0(a0) + lw t7, icache_size + sw t7, 4(a0) + lw t8, dcache_size + sw t8, 8(a0) + j ra + +ENDFRAME(get_mem_conf) +#endif /* defined CPU_R3000 */ + +#if defined(CPU_R4000) +#define LEAF(label) FRAME(label,sp,0,ra) +#define XLEAF(label) \ + .globl label ; \ +label: +#define END(label) ENDFRAME(label) + +/* + * cacheop macro to automate cache operations + * first some helpers... + */ +#define _mincache(size, maxsize) \ + bltu size,maxsize,8f ; \ + move size,maxsize ; \ +8: + +#define _align(tmp, minaddr, maxaddr, linesize) \ + subu tmp,linesize,1 ; \ + not tmp ; \ + and minaddr,tmp ; \ + addu maxaddr,-1 ; \ + and maxaddr,tmp + +/* This is a bit of a hack really because it relies on minaddr=a0 */ +#define _doop1(op1) \ + cache op1,0(a0) + +#define _doop2(op1, op2) \ + cache op1,0(a0) ; \ + cache op2,0(a0) + +/* specials for cache initialisation */ +#define _doop1lw1(op1) \ + cache op1,0(a0) ; \ + lw zero,0(a0) ; \ + cache op1,0(a0) + +#define _doop121(op1,op2) \ + cache op1,0(a0) ; \ + nop; \ + cache op2,0(a0) ; \ + nop; \ + cache op1,0(a0) + +#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \ + .set noreorder ; \ +7: _doop##tag##ops ; \ + bne minaddr,maxaddr,7b ; \ + addu minaddr,linesize ; \ + .set reorder + +/* finally the cache operation macros */ +#define icacheopn(kva, n, cache_size, cache_linesize, tag, ops) \ + _mincache(n, cache_size); \ + blez n,9f ; \ + addu n,kva ; \ + _align(t1, kva, n, cache_linesize) ; \ + _oploopn(kva, n, cache_linesize, tag, ops) ; \ +9: + +#define vcacheopn(kva, n, cache_size, cache_linesize, tag, ops) \ + blez n,9f ; \ + addu n,kva ; \ + _align(t1, kva, n, cache_linesize) ; \ + _oploopn(kva, n, cache_linesize, tag, ops) ; \ +9: + +#define icacheop(kva, n, cache_size, cache_linesize, op) \ + icacheopn(kva, n, cache_size, cache_linesize, 1, (op)) + +#define vcacheop(kva, n, cache_size, cache_linesize, op) \ + vcacheopn(kva, n, cache_size, cache_linesize, 1, (op)) + + .text + +/* + * static void _size_cache() R4000 + * + * Internal routine to determine cache sizes by looking at R4000 config + * register. Sizes are returned in registers, as follows: + * t2 icache size + * t3 dcache size + * t6 scache size + * t4 icache line size + * t5 dcache line size + * t7 scache line size + */ +LEAF(_size_cache) + mfc0 t0,C0_CONFIG + + and t1,t0,CFG_ICMASK + srl t1,CFG_ICSHIFT + li t2,0x1000 + sll t2,t1 + + and t1,t0,CFG_DCMASK + srl t1,CFG_DCSHIFT + li t3,0x1000 + sll t3,t1 + + li t4,32 + and t1,t0,CFG_IB + bnez t1,1f + li t4,16 +1: + + li t5,32 + and t1,t0,CFG_DB + bnez t1,1f + li t5,16 +1: + + move t6,zero # default to no scache + move t7,zero # + + and t1,t0,CFG_C_UNCACHED # test config register + bnez t1,1f # no scache if uncached/non-coherent + + li t6,0x100000 # assume 1Mb scache <<-NOTE + and t1,t0,CFG_SBMASK + srl t1,CFG_SBSHIFT + li t7,16 + sll t7,t1 +1: j ra +END(_size_cache) + + +/* + * void config_cache() R4000 + * + * Work out size of I, D & S caches, assuming they are already initialised. + */ +LEAF(config_cache) + lw t0,icache_size + bgtz t0,8f # already known? + move v0,ra + bal _size_cache + move ra,v0 + + sw t2,icache_size + sw t3,dcache_size + sw t6,scache_size + sw t4,icache_linesize + sw t5,dcache_linesize + sw t7,scache_linesize +8: j ra +END(config_cache) + + +/* + * void _init_cache() R4000 + */ +LEAF(_init_cache) + /* + * First work out the sizes + */ + move v0,ra + bal _size_cache + move ra,v0 + + /* + * The caches may be in an indeterminate state, + * so we force good parity into them by doing an + * invalidate, load/fill, invalidate for each line. + */ + + /* disable all i/u and cache exceptions */ + mfc0 v0,C0_SR + and v1,v0,~SR_IE + or v1,SR_DE + mtc0 v1,C0_SR + + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + /* assume bottom of RAM will generate good parity for the cache */ + li a0,PHYS_TO_K0(0) + move a2,t2 # icache_size + move a3,t4 # icache_linesize + move a1,a2 + icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill_I)) + + li a0,PHYS_TO_K0(0) + move a2,t3 # dcache_size + move a3,t5 # dcache_linesize + move a1,a2 + icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_D)) + + /* assume unified I & D in scache <<-NOTE */ + blez t6,1f + li a0,PHYS_TO_K0(0) + move a2,t6 + move a3,t7 + move a1,a2 + icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_SD)) + +1: mtc0 v0,C0_SR + j ra +END(_init_cache) + + +/* + * void flush_cache (void) R4000 + * + * Flush and invalidate all caches + */ +LEAF(flush_cache) + /* secondary cacheops do all the work if present */ + lw a2,scache_size + blez a2,1f + lw a3,scache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD) + b 2f + +1: + lw a2,icache_size + blez a2,2f + lw a3,icache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Invalidate_I) + + lw a2,dcache_size + lw a3,dcache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D) + +2: j ra +END(flush_cache) + +/* + * void flush_cache_nowrite (void) R4000 + * + * Invalidate all caches + */ +LEAF(flush_cache_nowrite) + mfc0 v0,C0_SR + and v1,v0,~SR_IE + mtc0 v1,C0_SR + + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + lw a2,icache_size + blez a2,2f + lw a3,icache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Invalidate_I) + + lw a2,dcache_size + lw a3,dcache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + + lw a2,scache_size + blez a2,2f + lw a3,scache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Store_Tag_SD) + +2: mtc0 v0,C0_SR + j ra +END(flush_cache_nowrite) + +/* + * void clean_cache (unsigned kva, size_t n) R4000 + * + * Writeback and invalidate address range in all caches + */ +LEAF(clean_cache) +XLEAF(clear_cache) + + /* secondary cacheops do all the work (if fitted) */ + lw a2,scache_size + blez a2,1f + lw a3,scache_linesize + vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD) + b 2f + +1: lw a2,icache_size + blez a2,2f + lw a3,icache_linesize + /* save kva & n for subsequent loop */ + move t8,a0 + move t9,a1 + vcacheop(a0,a1,a2,a3,Hit_Invalidate_I) + + lw a2,dcache_size + lw a3,dcache_linesize + /* restore kva & n */ + move a0,t8 + move a1,t9 + vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D) + +2: j ra +END(clean_cache) + +/* + * void clean_dcache (unsigned kva, size_t n) R4000 + * + * Writeback and invalidate address range in primary data cache + */ +LEAF(clean_dcache) + lw a2,dcache_size + blez a2,2f + lw a3,dcache_linesize + + vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D) + +2: j ra +END(clean_dcache) + +/* + * void clean_dcache_indexed (unsigned kva, size_t n) R4000 + * + * Writeback and invalidate indexed range in primary data cache + */ +LEAF(clean_dcache_indexed) + lw a2,dcache_size + blez a2,2f + lw a3,dcache_linesize + +#ifdef CPU_ORION + srl a2,1 # do one set (half cache) at a time + move t8,a0 # save kva & n + move t9,a1 + icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D) + + addu a0,t8,a2 # do next set + move a1,t9 # restore n +#endif + icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D) + +2: j ra +END(clean_dcache_indexed) + +/* + * void clean_dcache_nowrite (unsigned kva, size_t n) R4000 + * + * Invalidate an address range in primary data cache + */ +LEAF(clean_dcache_nowrite) + lw a2,dcache_size + blez a2,2f + lw a3,dcache_linesize + + vcacheop(a0,a1,a2,a3,Hit_Invalidate_D) + +2: j ra +END(clean_dcache_nowrite) + +/* + * void clean_dcache_nowrite_indexed (unsigned kva, size_t n) R4000 + * + * Invalidate indexed range in primary data cache + */ +LEAF(clean_dcache_nowrite_indexed) + mfc0 v0,C0_SR + and v1,v0,~SR_IE + mtc0 v1,C0_SR + + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + lw a2,dcache_size + blez a2,2f + lw a3,dcache_linesize + +#ifdef CPU_ORION + srl a2,1 # do one set (half cache) at a time + move t8,a0 # save kva & n + move t9,a1 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + + addu a0,t8,a2 # do next set + move a1,t9 # restore n +#endif + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + +2: mtc0 v0,C0_SR + j ra +END(clean_dcache_nowrite_indexed) + +/* + * void clean_icache (unsigned kva, size_t n) R4000 + * + * Invalidate address range in primary instruction cache + */ +LEAF(clean_icache) + lw a2,icache_size + blez a2,2f + lw a3,icache_linesize + + vcacheop(a0,a1,a2,a3,Hit_Invalidate_I) + +2: j ra +END(clean_icache) + +/* + * void clean_icache_indexed (unsigned kva, size_t n) R4000 + * + * Invalidate indexed range in primary instruction cache + */ +LEAF(clean_icache_indexed) + lw a2,icache_size + blez a2,2f + lw a3,icache_linesize + +#ifdef CPU_ORION + srl a2,1 # do one set (half cache) at a time + move t8,a0 # save kva & n + move t9,a1 + icacheop(a0,a1,a2,a3,Index_Invalidate_I) + + addu a0,t8,a2 # do next set + move a1,t9 # restore n +#endif + icacheop(a0,a1,a2,a3,Index_Invalidate_I) + +2: j ra +END(clean_icache_indexed) + + + +/* + * void clean_scache (unsigned kva, size_t n) R4000 + * + * Writeback and invalidate address range in secondary cache + */ +LEAF(clean_scache) + lw a2,scache_size + blez a2,2f + lw a3,scache_linesize + vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD) + +2: j ra +END(clean_scache) + +/* + * void clean_scache_indexed (unsigned kva, size_t n) R4000 + * + * Writeback and invalidate indexed range in secondary cache + */ +LEAF(clean_scache_indexed) + lw a2,scache_size + blez a2,2f + lw a3,scache_linesize + + icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD) + +2: j ra +END(clean_scache_indexed) + +/* + * void clean_scache_nowrite (unsigned kva, size_t n) R4000 + * + * Invalidate an address range in secondary cache + */ +LEAF(clean_scache_nowrite) + lw a2,scache_size + blez a2,2f + lw a3,scache_linesize + + vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD) + +2: j ra +END(clean_scache_nowrite) + +/* + * void clean_scache_nowrite_indexed (unsigned kva, size_t n) R4000 + * + * Invalidate indexed range in secondary cache + */ +LEAF(clean_scache_nowrite_indexed) + mfc0 v0,C0_SR + and v1,v0,~SR_IE + mtc0 v1,C0_SR + + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + lw a2,scache_size + blez a2,2f + lw a3,scache_linesize + + icacheop(a0,a1,a2,a3,Index_Store_Tag_SD) + +2: mtc0 v0,C0_SR + j ra +END(clean_scache_nowrite_indexed) + +/************************************************************************** +** +** get_mem_conf - get memory configuration R4000 +** +***************************************************************************/ + + +FRAME(get_mem_conf,sp,0,ra) + + lw t6, mem_size + sw t6, 0(a0) + lw t7, icache_size + sw t7, 4(a0) + lw t8, dcache_size + sw t8, 8(a0) + lw t7, scache_size + sw t7, 12(a0) + j ra + +ENDFRAME(get_mem_conf) + +#endif /* defined(CPU_R4000) */ + +/* + * void set_mem_size (mem_size) + * + * config_memory()'s memory size gets written into mem_size here. + * Now we don't need to call config_cache() with memory size - New to IDTC6.0 + */ +FRAME(set_memory_size,sp,0,ra) + sw a0, mem_size + j ra +ENDFRAME(set_memory_size) + + diff --git a/c/src/lib/libbsp/mips/p4000/startup/linkcmds b/c/src/lib/libbsp/mips/p4000/startup/linkcmds new file mode 100644 index 0000000000..e9d0566a12 --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/startup/linkcmds @@ -0,0 +1,69 @@ +/* @(#)linkcmds 04/08/96 1.2 */ +OUTPUT_FORMAT("elf32-bigmips") +OUTPUT_ARCH(mips) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +_DYNAMIC_LINK = 0; +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .text 0x80030000 : /* */ +/* .text 0xa0020000 : /* */ +/* .text 0x00020000 : /* */ + { + _ftext = . ; + *(.text) + CREATE_OBJECT_SYMBOLS + _etext = .; + } + .init ALIGN(8) : { *(.init) } =0 + .fini ALIGN(8) : { *(.fini) } =0 + .ctors ALIGN(8) : { *(.ctors) } + .dtors ALIGN(8) : { *(.dtors) } + .rodata ALIGN(8) : { *(.rodata) } + .rodata1 ALIGN(8) : + { + *(.rodata1) + . = ALIGN(8); + } + .reginfo . : { *(.reginfo) } + /* also: .hash .dynsym .dynstr .plt(if r/o) .rel.got */ + /* Read-write section, merged into data segment: */ + .data ALIGN(16) : + { + _fdata = . ; + *(.data) + CONSTRUCTORS + } + .data1 ALIGN(8) : { *(.data1) } + _gp = . + 0x8000; + .lit8 . : { *(.lit8) } + .lit4 . : { *(.lit4) } + /* also (before uninitialized portion): .dynamic .got .plt(if r/w) + (or does .dynamic go into its own segment?) */ + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata ALIGN(8) : { *(.sdata) } + _edata = .; + __bss_start = ALIGN(8); + _fbss = .; + .sbss ALIGN(8) : { *(.sbss) *(.scommon) } + .bss ALIGN(8) : + { + *(.bss) + *(COMMON) + _end = . ; + end = . ; + } + /* Debug sections. These should never be loadable, but they must have + zero addresses for the debuggers to work correctly. */ + .line 0 : { *(.line) } + .debug 0 : { *(.debug) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} + diff --git a/c/src/lib/libbsp/mips/p4000/startup/setvec.c b/c/src/lib/libbsp/mips/p4000/startup/setvec.c new file mode 100644 index 0000000000..1c6b581296 --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/startup/setvec.c @@ -0,0 +1,51 @@ +/* set_vector + * + * This routine installs an interrupt vector on the target Board/CPU. + * This routine is allowed to be as board dependent as necessary. + * + * INPUT: + * handler - interrupt handler entry point + * vector - vector number + * type - 0 indicates raw hardware connect + * 1 indicates RTEMS interrupt connect + * + * RETURNS: + * address of previous interrupt handler + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * setvec.c,v 1.2 1995/05/31 16:56:35 joel Exp + */ + +#ifndef lint +static char _sccsid[] = "@(#)setvec.c 04/25/96 1.2\n"; +#endif + +#include +#include + +#include + +mips_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +) +{ + mips_isr_entry previous_isr; + + if ( type ) + rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr ); + else { + /* XXX: install non-RTEMS ISR as "raw" interupt */ + rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr ); + } + return previous_isr; +} + diff --git a/c/src/lib/libbsp/mips/p4000/times b/c/src/lib/libbsp/mips/p4000/times new file mode 100644 index 0000000000..6a3dbfe1fb --- /dev/null +++ b/c/src/lib/libbsp/mips/p4000/times @@ -0,0 +1,200 @@ +# +# Timing Test Suite Results for the NO_BSP +# +# NOTE: This is just a template. The times are irrelevant since this BSP +# can only be compiled -- not executed. +# +# times,v 1.2 1995/12/07 15:44:23 joel Exp +# +# @(#)times 08/01/96 1.4 + +NOTE: To obtain the execution time in microseconds, divide the number of + cycles by the clock speed. For example, if rtems_semaphore create + is reported to be 1164 cycles, then at 66 Mhz it takes 17.64 + microseconds or 8.75 microseconds at 133 Mhz. + +Board: Algorithmics P4000i +CPU: IDT 4650 +Clock Speed: 100MHz +Memory Configuration: SRAM, DRAM, cache, etc +Wait States: + +Times Reported in: cycles +Timer Source: on-CPU cycle counter + +Column A:RTEMS compiled with 64 bit pointers and 64 bit unsigned32 types +Column B:RTEMS compiled with 32 bit pointers and 32 bit unsigned32 types + +# DESCRIPTION A B +== ================================================================= ==== ==== + 1 rtems_semaphore_create 788 759 + rtems_semaphore_delete 903 945 + rtems_semaphore_obtain: available 119 119 + rtems_semaphore_obtain: not available -- NO_WAIT 118 118 + rtems_semaphore_release: no waiting tasks 127 127 + + 2 rtems_semaphore_obtain: not available -- caller blocks 842 840 + + 3 rtems_semaphore_release: task readied -- preempts caller 777 751 + + 4 rtems_task_restart: blocked task -- preempts caller 1611 1595 + rtems_task_restart: ready task -- preempts caller 1253 1395 + rtems_semaphore_release: task readied -- returns to caller 365 345 + rtems_task_create 798 797 + rtems_task_start 464 460 + rtems_task_restart: suspended task -- returns to caller 517 517 + rtems_task_delete: suspended task 529 595 + rtems_task_restart: ready task -- returns to caller 527 525 + rtems_task_restart: blocked task -- returns to caller 707 684 + rtems_task_delete: blocked task 609 675 + + 5 rtems_task_suspend: calling task 549 549 + rtems_task_resume: task readied -- preempts caller 702 699 + + 6 rtems_task_restart: calling task 291 291 + rtems_task_suspend: returns to caller 195 194 + rtems_task_resume: task readied -- returns to caller 198 198 + rtems_task_delete: ready task 734 736 + + 7 rtems_task_restart: suspended task -- preempts caller 1049 990 + + 8 rtems_task_set_priority: obtain current priority 94 94 + rtems_task_set_priority: returns to caller 418 355 + rtems_task_mode: obtain current mode 44 43 + rtems_task_mode: no reschedule 0 49 + rtems_task_mode: reschedule -- returns to caller 0 232 + rtems_task_mode: reschedule -- preempts caller 0 687 + rtems_task_set_note 0 101 + rtems_task_get_note 0 103 + rtems_clock_set 0 237 + rtems_clock_get 0 16 + + 9 rtems_message_queue_create 3583 3432 + rtems_message_queue_send: no waiting tasks 252 252 + rtems_message_queue_urgent: no waiting tasks 252 252 + rtems_message_queue_receive: available 207 207 + rtems_message_queue_flush: no messages flushed 95 96 + rtems_message_queue_flush: messages flushed 110 110 + rtems_message_queue_delete 1044 1111 + +10 rtems_message_queue_receive: not available -- NO_WAIT 132 131 + rtems_message_queue_receive: not available -- caller blocks 884 892 + +11 rtems_message_queue_send: task readied -- preempts caller 397 817 + +12 rtems_message_queue_send: task readied -- returns to caller 397 397 + +13 rtems_message_queue_urgent: task readied -- preempts caller 816 817 + +14 rtems_message_queue_urgent: task readied -- returns to caller 397 398 + +15 rtems_event_receive: obtain current events 5 5 + rtems_event_receive: not available -- NO_WAIT 99 99 + rtems_event_receive: not available -- caller blocks 689 689 + rtems_event_send: no task readied 123 123 + rtems_event_receive: available 326 349 + rtems_event_send: task readied -- returns to caller 333 429 + +16 rtems_event_send: task readied -- preempts caller 843 838 + +17 rtems_task_set_priority: preempts caller 1002 991 + +18 rtems_task_delete: calling task 1171 1157 + +19 rtems_signal_catch 0 1306 + rtems_signal_send: returns to caller 0 1019 + rtems_signal_send: signal to self 0 496 + exit ASR overhead: returns to calling task 0 120 + exit ASR overhead: returns to preempting task 0 73 + +20 rtems_partition_create 1293 1306 + rtems_region_create 1010 1019 + rtems_partition_get_buffer: available 481 496 + rtems_partition_get_buffer: not available 120 120 + rtems_partition_return_buffer 587 460 + rtems_partition_delete 379 320 + rtems_region_get_segment: available 179 179 + rtems_region_get_segment: not available -- NO_WAIT 349 293 + rtems_region_return_segment: no waiting tasks 335 322 + rtems_region_get_segment: not available -- caller blocks 1603 1496 + rtems_region_return_segment: task readied -- preempts caller 1616 1533 + rtems_region_return_segment: task readied -- returns to caller 940 939 + rtems_region_delete 301 348 + rtems_io_initialize 9 10 + rtems_io_open 6 6 + rtems_io_close 6 6 + rtems_io_read 6 6 + rtems_io_write 6 5 + rtems_io_control 6 6 + +21 rtems_task_ident 1057 1058 + rtems_message_queue_ident 963 963 + rtems_semaphore_ident 1137 1136 + rtems_partition_ident 962 961 + rtems_region_ident 923 924 + rtems_port_ident 918 917 + rtems_timer_ident 942 941 + rtems_rate_monotonic_ident 924 925 + +22 rtems_message_queue_broadcast: task readied -- returns to caller 1084 1095 + rtems_message_queue_broadcast: no waiting tasks 147 148 + rtems_message_queue_broadcast: task readied -- preempts caller 1305 1268 + +23 rtems_timer_create 202 201 + rtems_timer_fire_after: inactive 261 261 + rtems_timer_fire_after: active 271 269 + rtems_timer_cancel: active 142 141 + rtems_timer_cancel: inactive 122 124 + rtems_timer_reset: inactive 222 222 + rtems_timer_reset: active 246 245 + rtems_timer_fire_when: inactive 312 311 + rtems_timer_fire_when: active 358 358 + rtems_timer_delete: active 263 263 + rtems_timer_delete: inactive 247 247 + rtems_task_wake_when 833 831 + +24 rtems_task_wake_after: yield -- returns to caller 99 98 + rtems_task_wake_after: yields -- preempts caller 479 478 + +25 rtems_clock_tick 313 318 + +26 _ISR_Disable 64 57 + _ISR_Flash 51 36 + _ISR_Enable 31 18 + _Thread_Disable_dispatch 53 37 + _Thread_Enable_dispatch 260 233 + _Thread_Set_state 446 463 + _Thread_Disptach (NO FP) 839 801 + context switch: no floating point contexts 673 653 + context switch: self 156 162 + context switch: to another task 84 70 + context switch: restore 1st FP task 1030 1013 + fp context switch: save idle, restore idle 969 948 + fp context switch: save idle, restore initialized 275 267 + fp context switch: save initialized, restore initialized 319 292 + _Thread_Resume 512 480 + _Thread_Unblock 121 139 + _Thread_Ready 199 203 + _Thread_Get 27 27 + _Semaphore_Get 20 21 + _Thread_Get: invalid id 5 5 + +27 interrupt entry overhead: returns to interrupted task 0 0 + interrupt exit overhead: returns to interrupted task 27 41 + interrupt entry overhead: returns to nested interrupt 0 0 + interrupt exit overhead: returns to nested interrupt 0 0 + interrupt entry overhead: returns to preempting task 0 0 + interrupt exit overhead: returns to preempting task 0 0 + +28 rtems_port_create 574 560 + rtems_port_external_to_internal 87 87 + rtems_port_internal_to_external 86 86 + rtems_port_delete 395 353 + +29 rtems_rate_monotonic_create 621 633 + rtems_rate_monotonic_period: initiate period -- returns to caller 773 694 + rtems_rate_monotonic_period: obtain status 295 284 + rtems_rate_monotonic_cancel 408 451 + rtems_rate_monotonic_delete: inactive 453 471 + rtems_rate_monotonic_delete: active 332 336 + rtems_rate_monotonic_period: conclude periods -- caller blocks 664 686 diff --git a/c/src/lib/libbsp/mips64orion/p4000/README b/c/src/lib/libbsp/mips64orion/p4000/README new file mode 100644 index 0000000000..31152f15ec --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/README @@ -0,0 +1,47 @@ +# +# README,v 1.2 1995/05/31 16:56:03 joel Exp +# +# @(#)README 08/20/96 1.2 +# + +BSP NAME: p4000 +BOARD: Algorithmics P4000 SBC +BUS: N/A +CPU FAMILY: mips +CPU: IDT 4650 +COPROCESSORS: N/A +MODE: 32 bit mode + +DEBUG MONITOR: IDT/SIM + +PERIPHERALS +=========== +TIMERS: 4650 internal + RESOLUTION: half of internal clock frequency +SERIAL PORTS: IDT/SIM controlled +REAL-TIME CLOCK: none +DMA: none +VIDEO: none +SCSI: none +NETWORKING: none + +DRIVER INFORMATION +================== +CLOCK DRIVER: 4650 internal +IOSUPP DRIVER: N/A +SHMSUPP: N/A +TIMER DRIVER: 4650 internal +TTY DRIVER: uses IDT/SIM + +STDIO +===== +PORT: Console port 0 +ELECTRICAL: RS-232 +BAUD: 9600 +BITS PER CHARACTER: 8 +PARITY: None +STOP BITS: 1 + +NOTES +===== + diff --git a/c/src/lib/libbsp/mips64orion/p4000/console/console.c b/c/src/lib/libbsp/mips64orion/p4000/console/console.c new file mode 100644 index 0000000000..cc52dc3c7c --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/console/console.c @@ -0,0 +1,270 @@ +/* + * This file contains the IDT 4650 console IO package. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/console/console.c: + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * console.c,v 1.4 1995/12/05 19:23:02 joel Exp + */ + + +#ifndef lint +static char _sccsid[] = "@(#)console.c 08/20/96 1.6\n"; +#endif + + +#include +#include +#include + +char idtsim_getchar( void ); +void idtsim_putchar( char c ); +void mips_leddisplay( char a, char b, char c, char d ); + + +/* console_initialize + * + * This routine initializes the console IO driver. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + */ + +rtems_device_driver console_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg +) +{ + rtems_status_code status; + + status = rtems_io_register_name( + "/dev/console", + major, + (rtems_device_minor_number) 0 + ); + + if (status != RTEMS_SUCCESSFUL) + rtems_fatal_error_occurred(status); + + return RTEMS_SUCCESSFUL; +} + + +/* is_character_ready + * + * This routine returns TRUE if a character is available. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + */ + +rtems_boolean is_character_ready( + char *ch +) +{ + *ch = '\0'; /* return NULL for no particular reason */ + return(TRUE); +} + +/* inbyte + * + * This routine reads a character from the SOURCE. + * + * Input parameters: NONE + * + * Output parameters: NONE + * + * Return values: + * character read from SOURCE + */ + +char inbyte( void ) +{ + /* + * If polling, wait until a character is available. + */ + + return idtsim_getchar(); +} + +/* outbyte + * + * This routine transmits a character out the SOURCE. It may support + * XON/XOFF flow control. + * + * Input parameters: + * ch - character to be transmitted + * + * Output parameters: NONE + */ + +void outbyte( + char ch +) +{ +#define NUM_LEDS 4 + static unsigned int cur_led = 0; + static unsigned char led_chars[NUM_LEDS]; + + /* + * If polling, wait for the transmitter to be ready. + * Check for flow control requests and process. + * Then output the character. + */ + + idtsim_putchar( ch ); + + /* print out first four alpha numeric characters in a line */ + if ( ch == '\n' ) + { + mips_leddisplay( led_chars[0], led_chars[1], led_chars[2], led_chars[3] ); + cur_led = 0; + } + else if ( isalnum( ch ) && cur_led < NUM_LEDS ) + { + led_chars[cur_led++] = ch; + } + +} + + +static int console_fd = -1; + +/* + * Open entry point + */ + +rtems_device_driver console_open( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ +#if 0 + int console_fd = open("tty0", 2); /* open for read/write */ +#endif + return RTEMS_SUCCESSFUL; +} + +/* + * Close entry point + */ + +rtems_device_driver console_close( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ +#if 0 + if ( console_fd ) + close( console_fd ); +#endif + return RTEMS_SUCCESSFUL; +} + +/* + * read bytes from the serial port. We only have stdin. + */ + +rtems_device_driver console_read( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + rtems_libio_rw_args_t *rw_args; + char *buffer; + int maximum; + int count = 0; + + rw_args = (rtems_libio_rw_args_t *) arg; + + buffer = rw_args->buffer; + maximum = rw_args->count; + + for (count = 0; count < maximum; count++) { + buffer[ count ] = inbyte(); + if (buffer[ count ] == '\n' || buffer[ count ] == '\r') { + buffer[ count++ ] = '\n'; + buffer[ count ] = 0; + break; + } + } + + rw_args->bytes_moved = count; + return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; +} + +/* + * write bytes to the serial port. Stdout and stderr are the same. + */ + +rtems_device_driver console_write( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + int count; + int maximum; + rtems_libio_rw_args_t *rw_args; + char *buffer; + + rw_args = (rtems_libio_rw_args_t *) arg; + + buffer = rw_args->buffer; + maximum = rw_args->count; + + for (count = 0; count < maximum; count++) { + if ( buffer[ count ] == '\n') { + outbyte('\r'); + } + outbyte( buffer[ count ] ); + } + + rw_args->bytes_moved = maximum; + return 0; +} + +/* + * IO Control entry point + */ + +rtems_device_driver console_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void * arg +) +{ + return RTEMS_SUCCESSFUL; +} diff --git a/c/src/lib/libbsp/mips64orion/p4000/console/led.S b/c/src/lib/libbsp/mips64orion/p4000/console/led.S new file mode 100644 index 0000000000..b9b7b7e294 --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/console/led.S @@ -0,0 +1,20 @@ + +#include +#include +#include + + +FRAME(mips_leddisplay,sp,0,ra) + j ra + nop +ENDFRAME(mips_leddisplay) + +FRAME(sbddisplay,sp,0,ra) + j ra +ENDFRAME(sbddisplay) + + +FRAME(sbdblank,sp,0,ra) + j ra +ENDFRAME(sbdblank) + diff --git a/c/src/lib/libbsp/mips64orion/p4000/include/bsp.h b/c/src/lib/libbsp/mips64orion/p4000/include/bsp.h new file mode 100644 index 0000000000..1a9f6a5653 --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/include/bsp.h @@ -0,0 +1,120 @@ +/* bsp.h + * + * This include file contains all board IO definitions. + * + * XXX : put yours in here + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * bsp.h,v 1.4 1995/09/11 19:29:04 joel Exp + */ +/* @(#)bsp.h 03/15/96 1.1 */ + +#ifndef __NO_BSP_h +#define __NO_BSP_h + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +extern void WriteDisplay( char * string ); + +/* + * Define the time limits for RTEMS Test Suite test durations. + * Long test and short test duration limits are provided. These + * values are in seconds and need to be converted to ticks for the + * application. + * + */ + +#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ +#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 ) + +#define Cause_tm27_intr() + +#define Clear_tm27_intr() + +#define Lower_tm27_intr() + +extern unsigned32 mips_get_timer( void ); + +#define CPU_CLOCK_RATE_MHZ (50) +#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */ + +/* + * Simple spin delay in microsecond units for device drivers. + * This is very dependent on the clock speed of the target. + */ + +#define delay( microseconds ) \ + { \ + unsigned32 _end_clock = mips_get_timer() + microseconds * CLOCKS_PER_MICROSECOND; \ + _end_clock %= 0x100000000; /* make sure result is 32 bits */ \ + \ + /* handle timer overflow, if necessary */ \ + while ( _end_clock < mips_get_timer() ); \ + \ + while ( _end_clock > mips_get_timer() ); \ + } + +/* Constants */ + +#define RAM_START 0 +#define RAM_END 0x100000 + +/* miscellaneous stuff assumed to exist */ + +extern rtems_configuration_table BSP_Configuration; + +/* + * Device Driver Table Entries + */ + +/* + * NOTE: Use the standard Console driver entry + */ + +/* + * NOTE: Use the standard Clock driver entry + */ + +/* + * How many libio files we want + */ + +#define BSP_LIBIO_MAX_FDS 20 + +/* functions */ + +void bsp_cleanup( void ); + +mips_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/mips64orion/p4000/include/coverhd.h b/c/src/lib/libbsp/mips64orion/p4000/include/coverhd.h new file mode 100644 index 0000000000..716faef06b --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/include/coverhd.h @@ -0,0 +1,116 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include all + * all calling overhead including passing of arguments. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * coverhd.h,v 1.2 1995/05/31 16:56:15 joel Exp + */ +/* @(#)coverhd.h 04/08/96 1.3 */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 5 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4 +#define CALLING_OVERHEAD_TASK_CREATE 6 +#define CALLING_OVERHEAD_TASK_IDENT 4 +#define CALLING_OVERHEAD_TASK_START 5 +#define CALLING_OVERHEAD_TASK_RESTART 4 +#define CALLING_OVERHEAD_TASK_DELETE 4 +#define CALLING_OVERHEAD_TASK_SUSPEND 4 +#define CALLING_OVERHEAD_TASK_RESUME 4 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5 +#define CALLING_OVERHEAD_TASK_MODE 4 +#define CALLING_OVERHEAD_TASK_GET_NOTE 5 +#define CALLING_OVERHEAD_TASK_SET_NOTE 5 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 9 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 5 +#define CALLING_OVERHEAD_CLOCK_GET 9 +#define CALLING_OVERHEAD_CLOCK_SET 8 +#define CALLING_OVERHEAD_CLOCK_TICK 3 + +#define CALLING_OVERHEAD_TIMER_CREATE 4 +#define CALLING_OVERHEAD_TIMER_IDENT 4 +#define CALLING_OVERHEAD_TIMER_DELETE 4 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 10 +#define CALLING_OVERHEAD_TIMER_RESET 4 +#define CALLING_OVERHEAD_TIMER_CANCEL 4 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 5 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 4 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 4 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 4 + +#define CALLING_OVERHEAD_EVENT_SEND 4 +#define CALLING_OVERHEAD_EVENT_RECEIVE 5 +#define CALLING_OVERHEAD_SIGNAL_CATCH 5 +#define CALLING_OVERHEAD_SIGNAL_SEND 4 +#define CALLING_OVERHEAD_PARTITION_CREATE 6 +#define CALLING_OVERHEAD_PARTITION_IDENT 4 +#define CALLING_OVERHEAD_PARTITION_DELETE 4 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 4 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 4 +#define CALLING_OVERHEAD_REGION_CREATE 6 +#define CALLING_OVERHEAD_REGION_IDENT 4 +#define CALLING_OVERHEAD_REGION_DELETE 4 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 5 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 4 +#define CALLING_OVERHEAD_PORT_CREATE 6 +#define CALLING_OVERHEAD_PORT_IDENT 4 +#define CALLING_OVERHEAD_PORT_DELETE 4 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 4 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 4 + +#define CALLING_OVERHEAD_IO_INITIALIZE 5 +#define CALLING_OVERHEAD_IO_OPEN 5 +#define CALLING_OVERHEAD_IO_CLOSE 5 +#define CALLING_OVERHEAD_IO_READ 5 +#define CALLING_OVERHEAD_IO_WRITE 5 +#define CALLING_OVERHEAD_IO_CONTROL 5 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3 + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/mips64orion/p4000/liblnk/lnklib.S b/c/src/lib/libbsp/mips64orion/p4000/liblnk/lnklib.S new file mode 100644 index 0000000000..fb8f28edbc --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/liblnk/lnklib.S @@ -0,0 +1,58 @@ +#include "iregdef.h" +#include "idtcpu.h" + +#define FRAME(name,frm_reg,offset,ret_reg) \ + .globl name; \ + .ent name; \ +name:; \ + .frame frm_reg,offset,ret_reg + +#define ENDFRAME(name) \ + .end name + +#define PROM_LINK(name,entry) \ + .globl name; \ + .ent name; \ +name: la $2,+entry; \ + j $2; \ + .end name + +#define PROM_ENTRY(x) (0xbfc00000+((x)*8)) + +#define PROM_RESET PROM_ENTRY(0) +#define PROM_NOT_IMP PROM_ENTRY(1) +#define PROM_RESTART PROM_ENTRY(2) +#define PROM_REINIT PROM_ENTRY(3) +#define PROM_GETCHAR PROM_ENTRY(11) +#define PROM_PUTCHAR PROM_ENTRY(12) +#define PROM_SHOWCHAR PROM_ENTRY(13) +#define PROM_PRINTF PROM_ENTRY(16) +#define PROM_RETURN PROM_ENTRY(17) + +#define PROM_RGETS PROM_ENTRY(25) +#define PROM_FLUSHCACHE PROM_ENTRY(28) +#define PROM_CLEARCACHE PROM_ENTRY(29) +#define PROM_SETJMP PROM_ENTRY(30) +#define PROM_LONGJMP PROM_ENTRY(31) + + .text + +PROM_LINK(idtsim_putchar, PROM_PUTCHAR) +PROM_LINK(idtsim_getchar, PROM_GETCHAR) +PROM_LINK(idtsim_showchar, PROM_SHOWCHAR) +PROM_LINK(idtsim__exit, PROM_RETURN) +PROM_LINK(idtsim_reinit, PROM_REINIT) +PROM_LINK(idtsim_restart, PROM_RESTART) +PROM_LINK(idtsim_reset, PROM_RESET) +PROM_LINK(idtsim_promexit, PROM_RETURN) +PROM_LINK(idtsim_setjmp, PROM_SETJMP) +PROM_LINK(idtsim_longjmp, PROM_LONGJMP) + +FRAME(idtsim_init_sbrk,sp,0,ra) + j ra +ENDFRAME(idtsim_init_sbrk) + +FRAME(idtsim_init_file,sp,0,ra) + j ra +ENDFRAME(idtsim_init_file) + diff --git a/c/src/lib/libbsp/mips64orion/p4000/start/start.S b/c/src/lib/libbsp/mips64orion/p4000/start/start.S new file mode 100644 index 0000000000..bbedf0c5dd --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/start/start.S @@ -0,0 +1,298 @@ +/* + +Based upon IDT provided code with the following release: + +This source code has been made available to you by IDT on an AS-IS +basis. Anyone receiving this source is licensed under IDT copyrights +to use it in any way he or she deems fit, including copying it, +modifying it, compiling it, and redistributing it either with or +without modifications. No license under IDT patents or patent +applications is to be implied by the copyright license. + +Any user of this software should understand that IDT cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work must +include the IDT copyright notice, this paragraph, and the preceeding +two paragraphs in the transferred software. + +COPYRIGHT IDT CORPORATION 1996 +LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + +*/ + +/************************************************************************* +** +** Copyright 1991-95 Integrated Device Technology, Inc. +** All Rights Reserved +** +** idt_csu.S -- IDT stand alone startup code +** +**************************************************************************/ +#include +#include +#include + + +.extern _fbss,4 /* this is defined by the linker */ +.extern end,4 /* this is defined by the linker */ + +.lcomm sim_mem_cfg_struct,12 + + .text + + +#define TMP_STKSIZE 1024 + +/************************************************************************** +** +** start - Typicl standalone start up code required for R3000/R4000 +** +** +** 1) Initialize the STATUS Register +** a) Clear parity error bit +** b) Set co_processor 1 usable bit ON +** c) Clear all IntMask Enables +** d) Set kernel/disabled mode +** 2) Initialize Cause Register +** a) clear software interrupt bits +** 3) Determine FPU installed or not +** if not, clear CoProcessor 1 usable bit +** 4) Clear bss area +** 5) MUST allocate temporary stack until memory size determined +** It MUST be uncached to prevent overwriting when caches are cleared +** 6) Install exception handlers +** 7) Determine memory and cache sizes +** 8) Establish permanent stack (cached or uncached as defined by bss) +** 9) Flush Instruction and Data caches +** 10) If there is a Translation Lookaside Buffer, Clear the TLB +** 11) Execute initialization code if the IDT/c library is to be used +** +** 12) Jump to user's "main()" +** 13) Jump to promexit +** +** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. +** This is used to mark code specific to R3xxx or R4xxx processors. +** IDT/C 6.x defines __mips to be the ISA level for which we're +** generating code. This is used to make sure the stack etc. is +** double word aligned, when using -mips3 (default) or -mips2, +** when compiling with IDT/C6.x +** +***************************************************************************/ + +FRAME(start,sp,0,ra) + + .set noreorder +#ifdef _R3000 + li v0,SR_PE|SR_CU1 /* reset parity error and set */ + /* cp1 usable */ +#endif +#ifdef _R4000 +#if __mips==3 || defined(R4650) + li v0,SR_CU1|SR_DE|SR_FR /* initally clear ERL, enable FPA 64bit regs*/ + /* 4650: Need fr to be set anyway */ +#else + li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPA 32bit regs*/ +#endif mips3 +#endif + + mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ + nop + mtc0 zero,C0_CAUSE /* clear software interrupts */ + nop + +#ifdef _R4000 + li v0,CFG_C_NONCOHERENT # initialise default cache mode + mtc0 v0,C0_CONFIG +#endif + +/* +** check to see if an fpu is really plugged in +*/ + li t3,0xaaaa5555 /* put a's and 5's in t3 */ + mtc1 t3,fp0 /* try to write them into fp0 */ + mtc1 zero,fp1 /* try to write zero in fp */ + mfc1 t0,fp0 + mfc1 t1,fp1 + nop + bne t0,t3,1f /* branch if no match */ + nop + bne t1,zero,1f /* double check for positive id */ + nop + /* We have a FPU. clear fcsr */ + ctc1 zero, fcr31 + j 2f /* status register already correct */ + nop +1: +#ifdef _R3000 + li v0, SR_PE /* reset parity error/NO cp1 usable */ +#endif + +#ifdef _R4000 + li v0,SR_DE /* clear ERL and disable FPA */ +#endif + + mtc0 v0, C0_SR /* reset status register */ +2: + la gp, _gp + + la v0,_fbss /* clear bss before using it */ + la v1,end /* end of bss */ +3: sw zero,0(v0) + bltu v0,v1,3b + add v0,4 + + +/************************************************************************ +** +** Temporary Stack - needed to handle stack saves until +** memory size is determined and permanent stack set +** +** MUST be uncached to avoid confusion at cache +** switching during memory sizing +** +*************************************************************************/ +#if __mips==3 + /* For MIPS 3, we need to be sure that the stack is aligned on a + * double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 11f /* Last three bits Zero, already aligned */ + nop + add v0, 4 +11: +#endif + + or v0, K1BASE /* switch to uncached */ + add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ + sub v1, v1, (4*4) /* overhead */ + move sp, v1 /* set sp to top of stack */ +4: sw zero, 0(v0) + bltu v0, v1, 4b /* clear out temp stack */ + add v0, 4 + + jal init_exc_vecs /* install exception handlers */ + nop /* MUST do before memory probes */ + + la v0, 5f + li v1, K1BASE /* force into uncached space */ + or v0, v1 /* during memory/cache probes */ + j v0 + nop +5: + la a0, sim_mem_cfg_struct + jal sim_mem_cfg /* Make SIM call to get mem size */ + nop + la a0, sim_mem_cfg_struct + lw a0, 0(a0) /* Get memory size from struct */ +#ifdef _R3000 + jal config_Icache + nop + jal config_Dcache /* determine size of D & I caches */ + nop +#endif +#ifdef _R4000 + jal config_cache /* determine size of D & I caches */ + nop +#endif + + move v0, a0 /* mem_size */ + +#if __mips==3 + /* For MIPS 3, we need to be sure that the stack (and hence v0 + * here) is aligned on a double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 12f /* Last three bits Zero, already aligned */ + nop + subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ +12: +#endif + + + +/************************************************************************** +** +** Permanent Stack - now know top of memory, put permanent stack there +** +***************************************************************************/ + + la t2, _fbss /* cache mode as linked */ + and t2, 0xF0000000 /* isolate segment */ + la t1, 6f + j t1 /* back to original cache mode */ + nop +6: + or v0, t2 /* stack back to original cache mode */ + addiu v0,v0,-16 /* overhead */ + move sp, v0 /* now replace count w top of memory */ + move v1, v0 + subu v1, P_STACKSIZE /* clear requested stack size */ + +7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ + bltu v1,v0,7b + add v1, 4 + .set reorder + +#ifdef _R3000 + jal flush_Icache + jal flush_Dcache /* flush Data & Instruction caches */ +#endif +#ifdef _R4000 + jal flush_cache_nowrite /* flush Data & Instruction caches */ +#endif + + + +/************************************************************************** +** +** If this chip supports a Translation Lookaside Buffer, clear it +** +***************************************************************************/ + + .set noreorder + mfc0 t1, C0_SR /* look at Status Register */ + nop + .set reorder +#ifdef _R3000 + li t2, SR_TS /* TLB Shutdown bit */ + and t1,t2 /* TLB Shutdown if 1 */ + bnez t1, 8f /* skip clearing if no TLB */ +#endif + +#ifndef R4650 + jal init_tlb /* clear the tlb */ +#endif + + +/************************************************************************ +** +** Initialization required if using IDT/c or libc.a, standard C Lib +** +** can SKIP if not necessary for application +** +************************************************************************/ +8: + + jal idtsim_init_sbrk + jal idtsim_init_file +/*********************** END I/O initialization **********************/ + + + jal main + + jal idtsim_promexit + +ENDFRAME(start) + + + .globl sim_mem_cfg +sim_mem_cfg: + .set noat + .set noreorder + li AT, (0xbfc00000+((55)*8)) + jr AT + nop + .set at + .set reorder diff --git a/c/src/lib/libbsp/mips64orion/p4000/startup/bspclean.c b/c/src/lib/libbsp/mips64orion/p4000/startup/bspclean.c new file mode 100644 index 0000000000..ecaff11004 --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/startup/bspclean.c @@ -0,0 +1,30 @@ +/* bsp_cleanup() + * + * This routine normally is part of start.s and usually returns + * control to a monitor. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * bspclean.c,v 1.2 1995/05/31 16:56:27 joel Exp + */ +#ifndef lint +static char _sccsid[] = "@(#)bspclean.c 03/15/96 1.1\n"; +#endif + + +#include +#include + +void bsp_cleanup( void ) +{ +} diff --git a/c/src/lib/libbsp/mips64orion/p4000/startup/ghlinkcmds b/c/src/lib/libbsp/mips64orion/p4000/startup/ghlinkcmds new file mode 100644 index 0000000000..cf2a80bf8d --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/startup/ghlinkcmds @@ -0,0 +1,15 @@ +-map +-sec +{ + .text 0x80010000 : + .data align(16) : + .rodata : + .fini : +# .sdata : + .symtab : + .strtab : + .debug : +# .sbss : + .bss align(8) : + .init 0xbfc00000 : +} diff --git a/c/src/lib/libbsp/mips64orion/p4000/startup/idtmem.S b/c/src/lib/libbsp/mips64orion/p4000/startup/idtmem.S new file mode 100644 index 0000000000..66c1a4ecbc --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/startup/idtmem.S @@ -0,0 +1,938 @@ +/* + +Based upon IDT provided code with the following release: + +This source code has been made available to you by IDT on an AS-IS +basis. Anyone receiving this source is licensed under IDT copyrights +to use it in any way he or she deems fit, including copying it, +modifying it, compiling it, and redistributing it either with or +without modifications. No license under IDT patents or patent +applications is to be implied by the copyright license. + +Any user of this software should understand that IDT cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work must +include the IDT copyright notice, this paragraph, and the preceeding +two paragraphs in the transferred software. + +COPYRIGHT IDT CORPORATION 1996 +LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + +*/ + +/************************************************************************ +** +** idtmem.s - memory and cache functions +** +** Copyright 1991 Integrated Device Technology, Inc. +** All Rights Reserved +** +**************************************************************************/ + +/* + * 950313: Ketan fixed bugs in mfc0/mtc0 hazards, and removed hack + * to set mem_size. + */ + +#include "iregdef.h" +#include "idtcpu.h" +#include "idtmon.h" +#include "saunder.h" + + + .data +mem_size: + .word 0 +dcache_size: + .word 0 +icache_size: +#if defined(CPU_R3000) + .word MINCACHE +#endif +#if defined(CPU_R4000) + .word 0 +#endif + +#if defined(CPU_R4000) + .data +scache_size: + .word 0 +icache_linesize: + .word 0 +dcache_linesize: + .word 0 +scache_linesize: + .word 0 +#endif + + + .text + +#if defined (CPU_R3000) +#define CONFIGFRM ((2*4)+4) + +/************************************************************************* +** +** Config_Dcache() -- determine size of Data cache +** +**************************************************************************/ + +FRAME(config_Dcache,sp, CONFIGFRM, ra) + .set noreorder + subu sp,CONFIGFRM + sw ra,CONFIGFRM-4(sp) /* save return address */ + sw s0,4*4(sp) /* save s0 in first regsave slot */ + mfc0 s0,C0_SR /* save SR */ + nop + mtc0 zero,C0_SR /* disable interrupts */ + .set reorder + jal _size_cache /* returns Data cache size in v0 */ + sw v0, dcache_size /* save it */ + and s0, ~SR_PE /* do not clear PE */ + .set noreorder + mtc0 s0,C0_SR /* restore SR */ + nop + .set reorder + lw s0, 4*4(sp) /* restore s0 */ + lw ra,CONFIGFRM-4(sp) /* restore ra */ + addu sp,CONFIGFRM /* pop stack */ + j ra +ENDFRAME(config_Dcache) + + +/************************************************************************* +** +** Config_Icache() -- determine size of Instruction cache +** MUST be run in uncached mode/handled in idt_csu.s +** +**************************************************************************/ + +FRAME(config_Icache,sp, CONFIGFRM, ra) + .set noreorder + subu sp,CONFIGFRM + sw ra,CONFIGFRM-4(sp) /* save return address */ + sw s0,4*4(sp) /* save s0 in first regsave slot */ + mfc0 s0,C0_SR /* save SR */ + nop + mtc0 zero, C0_SR /* disable interrupts */ + li v0,SR_SWC /* swap caches/disable ints */ + mtc0 v0,C0_SR + nop + .set reorder + jal _size_cache /* returns instruction cache size */ + .set noreorder + mtc0 zero,C0_SR /* swap back caches */ + nop + and s0,~SR_PE /* do not inadvertantly clear PE */ + mtc0 s0,C0_SR /* restore SR */ + nop + .set reorder + sw v0, icache_size /* save it AFTER caches back */ + lw s0,4*4(sp) /* restore s0 */ + lw ra,CONFIGFRM-4(sp) /* restore ra */ + addu sp,CONFIGFRM /* pop stack */ + j ra +ENDFRAME(config_Icache) + +/************************************************************************ +** +** _size_cache() +** returns cache size in v0 +** +************************************************************************/ + +FRAME(_size_cache,sp,0,ra) + .set noreorder + mfc0 t0,C0_SR /* save current sr */ + nop + and t0,~SR_PE /* do not inadvertently clear PE */ + or v0,t0,SR_ISC /* isolate cache */ + mtc0 v0,C0_SR + /* + * First check if there is a cache there at all + */ + move v0,zero + li v1,0xa5a5a5a5 /* distinctive pattern */ + sw v1,K0BASE /* try to write into cache */ + lw t1,K0BASE /* try to read from cache */ + nop + mfc0 t2,C0_SR + nop + .set reorder + and t2,SR_CM + bne t2,zero,3f /* cache miss, must be no cache */ + bne v1,t1,3f /* data not equal -> no cache */ + /* + * Clear cache size boundries to known state. + */ + li v0,MINCACHE +1: + sw zero,K0BASE(v0) + sll v0,1 + ble v0,MAXCACHE,1b + + li v0,-1 + sw v0,K0BASE(zero) /* store marker in cache */ + li v0,MINCACHE /* MIN cache size */ + +2: lw v1,K0BASE(v0) /* Look for marker */ + bne v1,zero,3f /* found marker */ + sll v0,1 /* cache size * 2 */ + ble v0,MAXCACHE,2b /* keep looking */ + move v0,zero /* must be no cache */ + .set noreorder +3: mtc0 t0,C0_SR /* restore sr */ + j ra + nop +ENDFRAME(_size_cache) + .set reorder + + +#define FLUSHFRM (2*4) + +/*************************************************************************** +** +** flush_Dcache() - flush entire Data cache +** +****************************************************************************/ +FRAME(flush_Dcache,sp,FLUSHFRM,ra) + lw t2, dcache_size + .set noreorder + mfc0 t3,C0_SR /* save SR */ + nop + and t3,~SR_PE /* dont inadvertently clear PE */ + beq t2,zero,_Dflush_done /* no D cache, get out! */ + nop + li v0, SR_ISC /* isolate cache */ + mtc0 v0, C0_SR + nop + .set reorder + li t0,K0BASE /* set loop registers */ + or t1,t0,t2 + +2: sb zero,0(t0) + sb zero,4(t0) + sb zero,8(t0) + sb zero,12(t0) + sb zero,16(t0) + sb zero,20(t0) + sb zero,24(t0) + addu t0,32 + sb zero,-4(t0) + bne t0,t1,2b + + .set noreorder +_Dflush_done: + mtc0 t3,C0_SR /* restore Status Register */ + .set reorder + j ra +ENDFRAME(flush_Dcache) + + +/*************************************************************************** +** +** flush_Icache() - flush entire Instruction cache +** +** NOTE: Icache can only be flushed/cleared when uncached +** Code forces into uncached memory regardless of calling mode +** +****************************************************************************/ +FRAME(flush_Icache,sp,FLUSHFRM,ra) + lw t1,icache_size + .set noreorder + mfc0 t3,C0_SR /* save SR */ + nop + la v0,1f + li v1,K1BASE + or v0,v1 + j v0 /* force into non-cached space */ + nop +1: + and t3,~SR_PE /* dont inadvertently clear PE */ + beq t1,zero,_Iflush_done /* no i-cache get out */ + nop + li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */ + mtc0 v0,C0_SR + li t0,K0BASE + .set reorder + or t1,t0,t1 + +1: sb zero,0(t0) + sb zero,4(t0) + sb zero,8(t0) + sb zero,12(t0) + sb zero,16(t0) + sb zero,20(t0) + sb zero,24(t0) + addu t0,32 + sb zero,-4(t0) + bne t0,t1,1b + .set noreorder +_Iflush_done: + mtc0 t3,C0_SR /* un-isolate, enable interrupts */ + .set reorder + j ra +ENDFRAME(flush_Icache) + +/************************************************************************** +** +** clear_Dcache(base_addr, byte_count) - flush portion of Data cache +** +** a0 = base address of portion to be cleared +** a1 = byte count of length +** +***************************************************************************/ +FRAME(clear_Dcache,sp,0,ra) + + lw t2, dcache_size /* Data cache size */ + .set noreorder + mfc0 t3,C0_SR /* save SR */ + nop + and t3,~SR_PE /* dont inadvertently clear PE */ + nop + nop + .set reorder + /* + * flush data cache + */ + + .set noreorder + nop + li v0,SR_ISC /* isolate data cache */ + mtc0 v0,C0_SR + .set reorder + bltu t2,a1,1f /* cache is smaller than region */ + move t2,a1 +1: addu t2,a0 /* ending address + 1 */ + move t0,a0 + +1: sb zero,0(t0) + sb zero,4(t0) + sb zero,8(t0) + sb zero,12(t0) + sb zero,16(t0) + sb zero,20(t0) + sb zero,24(t0) + addu t0,32 + sb zero,-4(t0) + bltu t0,t2,1b + + .set noreorder + mtc0 t3,C0_SR /* un-isolate, enable interrupts */ + nop + .set reorder + j ra +ENDFRAME(clear_Dcache) + + +/************************************************************************** +** +** clear_Icache(base_addr, byte_count) - flush portion of Instruction cache +** +** a0 = base address of portion to be cleared +** a1 = byte count of length +** +** NOTE: Icache can only be flushed/cleared when uncached +** Code forces into uncached memory regardless of calling mode +** +***************************************************************************/ +FRAME(clear_Icache,sp,0,ra) + + lw t1, icache_size /* Instruction cache size */ + /* + * flush text cache + */ + .set noreorder + mfc0 t3,C0_SR /* save SR */ + nop + la v0,1f + li v1,K1BASE + or v0,v1 + j v0 /* force into non-cached space */ + nop +1: + and t3,~SR_PE /* dont inadvertently clear PE */ + nop + nop + li v0,SR_ISC|SR_SWC /* disable intr, isolate and swap */ + mtc0 v0,C0_SR + .set reorder + bltu t1,a1,1f /* cache is smaller than region */ + move t1,a1 +1: addu t1,a0 /* ending address + 1 */ + move t0,a0 + + sb zero,0(t0) + sb zero,4(t0) + sb zero,8(t0) + sb zero,12(t0) + sb zero,16(t0) + sb zero,20(t0) + sb zero,24(t0) + addu t0,32 + sb zero,-4(t0) + bltu t0,t1,1b + .set noreorder + mtc0 t3,C0_SR /* un-isolate, enable interrupts */ + nop + nop + nop /* allow time for caches to swap */ + .set reorder + j ra +ENDFRAME(clear_Icache) + + +/************************************************************************** +** +** get_mem_conf - get memory configuration +** +***************************************************************************/ + + +FRAME(get_mem_conf,sp,0,ra) + + lw t6, mem_size + sw t6, 0(a0) + lw t7, icache_size + sw t7, 4(a0) + lw t8, dcache_size + sw t8, 8(a0) + j ra + +ENDFRAME(get_mem_conf) +#endif /* defined CPU_R3000 */ + +#if defined(CPU_R4000) +#define LEAF(label) FRAME(label,sp,0,ra) +#define XLEAF(label) \ + .globl label ; \ +label: +#define END(label) ENDFRAME(label) + +/* + * cacheop macro to automate cache operations + * first some helpers... + */ +#define _mincache(size, maxsize) \ + bltu size,maxsize,8f ; \ + move size,maxsize ; \ +8: + +#define _align(tmp, minaddr, maxaddr, linesize) \ + subu tmp,linesize,1 ; \ + not tmp ; \ + and minaddr,tmp ; \ + addu maxaddr,-1 ; \ + and maxaddr,tmp + +/* This is a bit of a hack really because it relies on minaddr=a0 */ +#define _doop1(op1) \ + cache op1,0(a0) + +#define _doop2(op1, op2) \ + cache op1,0(a0) ; \ + cache op2,0(a0) + +/* specials for cache initialisation */ +#define _doop1lw1(op1) \ + cache op1,0(a0) ; \ + lw zero,0(a0) ; \ + cache op1,0(a0) + +#define _doop121(op1,op2) \ + cache op1,0(a0) ; \ + nop; \ + cache op2,0(a0) ; \ + nop; \ + cache op1,0(a0) + +#define _oploopn(minaddr, maxaddr, linesize, tag, ops) \ + .set noreorder ; \ +7: _doop##tag##ops ; \ + bne minaddr,maxaddr,7b ; \ + addu minaddr,linesize ; \ + .set reorder + +/* finally the cache operation macros */ +#define icacheopn(kva, n, cache_size, cache_linesize, tag, ops) \ + _mincache(n, cache_size); \ + blez n,9f ; \ + addu n,kva ; \ + _align(t1, kva, n, cache_linesize) ; \ + _oploopn(kva, n, cache_linesize, tag, ops) ; \ +9: + +#define vcacheopn(kva, n, cache_size, cache_linesize, tag, ops) \ + blez n,9f ; \ + addu n,kva ; \ + _align(t1, kva, n, cache_linesize) ; \ + _oploopn(kva, n, cache_linesize, tag, ops) ; \ +9: + +#define icacheop(kva, n, cache_size, cache_linesize, op) \ + icacheopn(kva, n, cache_size, cache_linesize, 1, (op)) + +#define vcacheop(kva, n, cache_size, cache_linesize, op) \ + vcacheopn(kva, n, cache_size, cache_linesize, 1, (op)) + + .text + +/* + * static void _size_cache() R4000 + * + * Internal routine to determine cache sizes by looking at R4000 config + * register. Sizes are returned in registers, as follows: + * t2 icache size + * t3 dcache size + * t6 scache size + * t4 icache line size + * t5 dcache line size + * t7 scache line size + */ +LEAF(_size_cache) + mfc0 t0,C0_CONFIG + + and t1,t0,CFG_ICMASK + srl t1,CFG_ICSHIFT + li t2,0x1000 + sll t2,t1 + + and t1,t0,CFG_DCMASK + srl t1,CFG_DCSHIFT + li t3,0x1000 + sll t3,t1 + + li t4,32 + and t1,t0,CFG_IB + bnez t1,1f + li t4,16 +1: + + li t5,32 + and t1,t0,CFG_DB + bnez t1,1f + li t5,16 +1: + + move t6,zero # default to no scache + move t7,zero # + + and t1,t0,CFG_C_UNCACHED # test config register + bnez t1,1f # no scache if uncached/non-coherent + + li t6,0x100000 # assume 1Mb scache <<-NOTE + and t1,t0,CFG_SBMASK + srl t1,CFG_SBSHIFT + li t7,16 + sll t7,t1 +1: j ra +END(_size_cache) + + +/* + * void config_cache() R4000 + * + * Work out size of I, D & S caches, assuming they are already initialised. + */ +LEAF(config_cache) + lw t0,icache_size + bgtz t0,8f # already known? + move v0,ra + bal _size_cache + move ra,v0 + + sw t2,icache_size + sw t3,dcache_size + sw t6,scache_size + sw t4,icache_linesize + sw t5,dcache_linesize + sw t7,scache_linesize +8: j ra +END(config_cache) + + +/* + * void _init_cache() R4000 + */ +LEAF(_init_cache) + /* + * First work out the sizes + */ + move v0,ra + bal _size_cache + move ra,v0 + + /* + * The caches may be in an indeterminate state, + * so we force good parity into them by doing an + * invalidate, load/fill, invalidate for each line. + */ + + /* disable all i/u and cache exceptions */ + mfc0 v0,C0_SR + and v1,v0,~SR_IE + or v1,SR_DE + mtc0 v1,C0_SR + + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + /* assume bottom of RAM will generate good parity for the cache */ + li a0,PHYS_TO_K0(0) + move a2,t2 # icache_size + move a3,t4 # icache_linesize + move a1,a2 + icacheopn(a0,a1,a2,a3,121,(Index_Store_Tag_I,Fill_I)) + + li a0,PHYS_TO_K0(0) + move a2,t3 # dcache_size + move a3,t5 # dcache_linesize + move a1,a2 + icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_D)) + + /* assume unified I & D in scache <<-NOTE */ + blez t6,1f + li a0,PHYS_TO_K0(0) + move a2,t6 + move a3,t7 + move a1,a2 + icacheopn(a0,a1,a2,a3,1lw1,(Index_Store_Tag_SD)) + +1: mtc0 v0,C0_SR + j ra +END(_init_cache) + + +/* + * void flush_cache (void) R4000 + * + * Flush and invalidate all caches + */ +LEAF(flush_cache) + /* secondary cacheops do all the work if present */ + lw a2,scache_size + blez a2,1f + lw a3,scache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD) + b 2f + +1: + lw a2,icache_size + blez a2,2f + lw a3,icache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Invalidate_I) + + lw a2,dcache_size + lw a3,dcache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D) + +2: j ra +END(flush_cache) + +/* + * void flush_cache_nowrite (void) R4000 + * + * Invalidate all caches + */ +LEAF(flush_cache_nowrite) + mfc0 v0,C0_SR + and v1,v0,~SR_IE + mtc0 v1,C0_SR + + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + lw a2,icache_size + blez a2,2f + lw a3,icache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Invalidate_I) + + lw a2,dcache_size + lw a3,dcache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + + lw a2,scache_size + blez a2,2f + lw a3,scache_linesize + li a0,PHYS_TO_K0(0) + move a1,a2 + icacheop(a0,a1,a2,a3,Index_Store_Tag_SD) + +2: mtc0 v0,C0_SR + j ra +END(flush_cache_nowrite) + +/* + * void clean_cache (unsigned kva, size_t n) R4000 + * + * Writeback and invalidate address range in all caches + */ +LEAF(clean_cache) +XLEAF(clear_cache) + + /* secondary cacheops do all the work (if fitted) */ + lw a2,scache_size + blez a2,1f + lw a3,scache_linesize + vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD) + b 2f + +1: lw a2,icache_size + blez a2,2f + lw a3,icache_linesize + /* save kva & n for subsequent loop */ + move t8,a0 + move t9,a1 + vcacheop(a0,a1,a2,a3,Hit_Invalidate_I) + + lw a2,dcache_size + lw a3,dcache_linesize + /* restore kva & n */ + move a0,t8 + move a1,t9 + vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D) + +2: j ra +END(clean_cache) + +/* + * void clean_dcache (unsigned kva, size_t n) R4000 + * + * Writeback and invalidate address range in primary data cache + */ +LEAF(clean_dcache) + lw a2,dcache_size + blez a2,2f + lw a3,dcache_linesize + + vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_D) + +2: j ra +END(clean_dcache) + +/* + * void clean_dcache_indexed (unsigned kva, size_t n) R4000 + * + * Writeback and invalidate indexed range in primary data cache + */ +LEAF(clean_dcache_indexed) + lw a2,dcache_size + blez a2,2f + lw a3,dcache_linesize + +#ifdef CPU_ORION + srl a2,1 # do one set (half cache) at a time + move t8,a0 # save kva & n + move t9,a1 + icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D) + + addu a0,t8,a2 # do next set + move a1,t9 # restore n +#endif + icacheop(a0,a1,a2,a3,Index_Writeback_Inv_D) + +2: j ra +END(clean_dcache_indexed) + +/* + * void clean_dcache_nowrite (unsigned kva, size_t n) R4000 + * + * Invalidate an address range in primary data cache + */ +LEAF(clean_dcache_nowrite) + lw a2,dcache_size + blez a2,2f + lw a3,dcache_linesize + + vcacheop(a0,a1,a2,a3,Hit_Invalidate_D) + +2: j ra +END(clean_dcache_nowrite) + +/* + * void clean_dcache_nowrite_indexed (unsigned kva, size_t n) R4000 + * + * Invalidate indexed range in primary data cache + */ +LEAF(clean_dcache_nowrite_indexed) + mfc0 v0,C0_SR + and v1,v0,~SR_IE + mtc0 v1,C0_SR + + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + lw a2,dcache_size + blez a2,2f + lw a3,dcache_linesize + +#ifdef CPU_ORION + srl a2,1 # do one set (half cache) at a time + move t8,a0 # save kva & n + move t9,a1 + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + + addu a0,t8,a2 # do next set + move a1,t9 # restore n +#endif + icacheop(a0,a1,a2,a3,Index_Store_Tag_D) + +2: mtc0 v0,C0_SR + j ra +END(clean_dcache_nowrite_indexed) + +/* + * void clean_icache (unsigned kva, size_t n) R4000 + * + * Invalidate address range in primary instruction cache + */ +LEAF(clean_icache) + lw a2,icache_size + blez a2,2f + lw a3,icache_linesize + + vcacheop(a0,a1,a2,a3,Hit_Invalidate_I) + +2: j ra +END(clean_icache) + +/* + * void clean_icache_indexed (unsigned kva, size_t n) R4000 + * + * Invalidate indexed range in primary instruction cache + */ +LEAF(clean_icache_indexed) + lw a2,icache_size + blez a2,2f + lw a3,icache_linesize + +#ifdef CPU_ORION + srl a2,1 # do one set (half cache) at a time + move t8,a0 # save kva & n + move t9,a1 + icacheop(a0,a1,a2,a3,Index_Invalidate_I) + + addu a0,t8,a2 # do next set + move a1,t9 # restore n +#endif + icacheop(a0,a1,a2,a3,Index_Invalidate_I) + +2: j ra +END(clean_icache_indexed) + + + +/* + * void clean_scache (unsigned kva, size_t n) R4000 + * + * Writeback and invalidate address range in secondary cache + */ +LEAF(clean_scache) + lw a2,scache_size + blez a2,2f + lw a3,scache_linesize + vcacheop(a0,a1,a2,a3,Hit_Writeback_Inv_SD) + +2: j ra +END(clean_scache) + +/* + * void clean_scache_indexed (unsigned kva, size_t n) R4000 + * + * Writeback and invalidate indexed range in secondary cache + */ +LEAF(clean_scache_indexed) + lw a2,scache_size + blez a2,2f + lw a3,scache_linesize + + icacheop(a0,a1,a2,a3,Index_Writeback_Inv_SD) + +2: j ra +END(clean_scache_indexed) + +/* + * void clean_scache_nowrite (unsigned kva, size_t n) R4000 + * + * Invalidate an address range in secondary cache + */ +LEAF(clean_scache_nowrite) + lw a2,scache_size + blez a2,2f + lw a3,scache_linesize + + vcacheop(a0,a1,a2,a3,Hit_Invalidate_SD) + +2: j ra +END(clean_scache_nowrite) + +/* + * void clean_scache_nowrite_indexed (unsigned kva, size_t n) R4000 + * + * Invalidate indexed range in secondary cache + */ +LEAF(clean_scache_nowrite_indexed) + mfc0 v0,C0_SR + and v1,v0,~SR_IE + mtc0 v1,C0_SR + + mtc0 zero,C0_TAGLO + mtc0 zero,C0_TAGHI + + lw a2,scache_size + blez a2,2f + lw a3,scache_linesize + + icacheop(a0,a1,a2,a3,Index_Store_Tag_SD) + +2: mtc0 v0,C0_SR + j ra +END(clean_scache_nowrite_indexed) + +/************************************************************************** +** +** get_mem_conf - get memory configuration R4000 +** +***************************************************************************/ + + +FRAME(get_mem_conf,sp,0,ra) + + lw t6, mem_size + sw t6, 0(a0) + lw t7, icache_size + sw t7, 4(a0) + lw t8, dcache_size + sw t8, 8(a0) + lw t7, scache_size + sw t7, 12(a0) + j ra + +ENDFRAME(get_mem_conf) + +#endif /* defined(CPU_R4000) */ + +/* + * void set_mem_size (mem_size) + * + * config_memory()'s memory size gets written into mem_size here. + * Now we don't need to call config_cache() with memory size - New to IDTC6.0 + */ +FRAME(set_memory_size,sp,0,ra) + sw a0, mem_size + j ra +ENDFRAME(set_memory_size) + + diff --git a/c/src/lib/libbsp/mips64orion/p4000/startup/linkcmds b/c/src/lib/libbsp/mips64orion/p4000/startup/linkcmds new file mode 100644 index 0000000000..e9d0566a12 --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/startup/linkcmds @@ -0,0 +1,69 @@ +/* @(#)linkcmds 04/08/96 1.2 */ +OUTPUT_FORMAT("elf32-bigmips") +OUTPUT_ARCH(mips) +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +_DYNAMIC_LINK = 0; +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + .text 0x80030000 : /* */ +/* .text 0xa0020000 : /* */ +/* .text 0x00020000 : /* */ + { + _ftext = . ; + *(.text) + CREATE_OBJECT_SYMBOLS + _etext = .; + } + .init ALIGN(8) : { *(.init) } =0 + .fini ALIGN(8) : { *(.fini) } =0 + .ctors ALIGN(8) : { *(.ctors) } + .dtors ALIGN(8) : { *(.dtors) } + .rodata ALIGN(8) : { *(.rodata) } + .rodata1 ALIGN(8) : + { + *(.rodata1) + . = ALIGN(8); + } + .reginfo . : { *(.reginfo) } + /* also: .hash .dynsym .dynstr .plt(if r/o) .rel.got */ + /* Read-write section, merged into data segment: */ + .data ALIGN(16) : + { + _fdata = . ; + *(.data) + CONSTRUCTORS + } + .data1 ALIGN(8) : { *(.data1) } + _gp = . + 0x8000; + .lit8 . : { *(.lit8) } + .lit4 . : { *(.lit4) } + /* also (before uninitialized portion): .dynamic .got .plt(if r/w) + (or does .dynamic go into its own segment?) */ + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata ALIGN(8) : { *(.sdata) } + _edata = .; + __bss_start = ALIGN(8); + _fbss = .; + .sbss ALIGN(8) : { *(.sbss) *(.scommon) } + .bss ALIGN(8) : + { + *(.bss) + *(COMMON) + _end = . ; + end = . ; + } + /* Debug sections. These should never be loadable, but they must have + zero addresses for the debuggers to work correctly. */ + .line 0 : { *(.line) } + .debug 0 : { *(.debug) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} + diff --git a/c/src/lib/libbsp/mips64orion/p4000/startup/setvec.c b/c/src/lib/libbsp/mips64orion/p4000/startup/setvec.c new file mode 100644 index 0000000000..1c6b581296 --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/startup/setvec.c @@ -0,0 +1,51 @@ +/* set_vector + * + * This routine installs an interrupt vector on the target Board/CPU. + * This routine is allowed to be as board dependent as necessary. + * + * INPUT: + * handler - interrupt handler entry point + * vector - vector number + * type - 0 indicates raw hardware connect + * 1 indicates RTEMS interrupt connect + * + * RETURNS: + * address of previous interrupt handler + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * setvec.c,v 1.2 1995/05/31 16:56:35 joel Exp + */ + +#ifndef lint +static char _sccsid[] = "@(#)setvec.c 04/25/96 1.2\n"; +#endif + +#include +#include + +#include + +mips_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +) +{ + mips_isr_entry previous_isr; + + if ( type ) + rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr ); + else { + /* XXX: install non-RTEMS ISR as "raw" interupt */ + rtems_interrupt_catch( handler, vector, (rtems_isr_entry *) &previous_isr ); + } + return previous_isr; +} + diff --git a/c/src/lib/libbsp/mips64orion/p4000/times b/c/src/lib/libbsp/mips64orion/p4000/times new file mode 100644 index 0000000000..6a3dbfe1fb --- /dev/null +++ b/c/src/lib/libbsp/mips64orion/p4000/times @@ -0,0 +1,200 @@ +# +# Timing Test Suite Results for the NO_BSP +# +# NOTE: This is just a template. The times are irrelevant since this BSP +# can only be compiled -- not executed. +# +# times,v 1.2 1995/12/07 15:44:23 joel Exp +# +# @(#)times 08/01/96 1.4 + +NOTE: To obtain the execution time in microseconds, divide the number of + cycles by the clock speed. For example, if rtems_semaphore create + is reported to be 1164 cycles, then at 66 Mhz it takes 17.64 + microseconds or 8.75 microseconds at 133 Mhz. + +Board: Algorithmics P4000i +CPU: IDT 4650 +Clock Speed: 100MHz +Memory Configuration: SRAM, DRAM, cache, etc +Wait States: + +Times Reported in: cycles +Timer Source: on-CPU cycle counter + +Column A:RTEMS compiled with 64 bit pointers and 64 bit unsigned32 types +Column B:RTEMS compiled with 32 bit pointers and 32 bit unsigned32 types + +# DESCRIPTION A B +== ================================================================= ==== ==== + 1 rtems_semaphore_create 788 759 + rtems_semaphore_delete 903 945 + rtems_semaphore_obtain: available 119 119 + rtems_semaphore_obtain: not available -- NO_WAIT 118 118 + rtems_semaphore_release: no waiting tasks 127 127 + + 2 rtems_semaphore_obtain: not available -- caller blocks 842 840 + + 3 rtems_semaphore_release: task readied -- preempts caller 777 751 + + 4 rtems_task_restart: blocked task -- preempts caller 1611 1595 + rtems_task_restart: ready task -- preempts caller 1253 1395 + rtems_semaphore_release: task readied -- returns to caller 365 345 + rtems_task_create 798 797 + rtems_task_start 464 460 + rtems_task_restart: suspended task -- returns to caller 517 517 + rtems_task_delete: suspended task 529 595 + rtems_task_restart: ready task -- returns to caller 527 525 + rtems_task_restart: blocked task -- returns to caller 707 684 + rtems_task_delete: blocked task 609 675 + + 5 rtems_task_suspend: calling task 549 549 + rtems_task_resume: task readied -- preempts caller 702 699 + + 6 rtems_task_restart: calling task 291 291 + rtems_task_suspend: returns to caller 195 194 + rtems_task_resume: task readied -- returns to caller 198 198 + rtems_task_delete: ready task 734 736 + + 7 rtems_task_restart: suspended task -- preempts caller 1049 990 + + 8 rtems_task_set_priority: obtain current priority 94 94 + rtems_task_set_priority: returns to caller 418 355 + rtems_task_mode: obtain current mode 44 43 + rtems_task_mode: no reschedule 0 49 + rtems_task_mode: reschedule -- returns to caller 0 232 + rtems_task_mode: reschedule -- preempts caller 0 687 + rtems_task_set_note 0 101 + rtems_task_get_note 0 103 + rtems_clock_set 0 237 + rtems_clock_get 0 16 + + 9 rtems_message_queue_create 3583 3432 + rtems_message_queue_send: no waiting tasks 252 252 + rtems_message_queue_urgent: no waiting tasks 252 252 + rtems_message_queue_receive: available 207 207 + rtems_message_queue_flush: no messages flushed 95 96 + rtems_message_queue_flush: messages flushed 110 110 + rtems_message_queue_delete 1044 1111 + +10 rtems_message_queue_receive: not available -- NO_WAIT 132 131 + rtems_message_queue_receive: not available -- caller blocks 884 892 + +11 rtems_message_queue_send: task readied -- preempts caller 397 817 + +12 rtems_message_queue_send: task readied -- returns to caller 397 397 + +13 rtems_message_queue_urgent: task readied -- preempts caller 816 817 + +14 rtems_message_queue_urgent: task readied -- returns to caller 397 398 + +15 rtems_event_receive: obtain current events 5 5 + rtems_event_receive: not available -- NO_WAIT 99 99 + rtems_event_receive: not available -- caller blocks 689 689 + rtems_event_send: no task readied 123 123 + rtems_event_receive: available 326 349 + rtems_event_send: task readied -- returns to caller 333 429 + +16 rtems_event_send: task readied -- preempts caller 843 838 + +17 rtems_task_set_priority: preempts caller 1002 991 + +18 rtems_task_delete: calling task 1171 1157 + +19 rtems_signal_catch 0 1306 + rtems_signal_send: returns to caller 0 1019 + rtems_signal_send: signal to self 0 496 + exit ASR overhead: returns to calling task 0 120 + exit ASR overhead: returns to preempting task 0 73 + +20 rtems_partition_create 1293 1306 + rtems_region_create 1010 1019 + rtems_partition_get_buffer: available 481 496 + rtems_partition_get_buffer: not available 120 120 + rtems_partition_return_buffer 587 460 + rtems_partition_delete 379 320 + rtems_region_get_segment: available 179 179 + rtems_region_get_segment: not available -- NO_WAIT 349 293 + rtems_region_return_segment: no waiting tasks 335 322 + rtems_region_get_segment: not available -- caller blocks 1603 1496 + rtems_region_return_segment: task readied -- preempts caller 1616 1533 + rtems_region_return_segment: task readied -- returns to caller 940 939 + rtems_region_delete 301 348 + rtems_io_initialize 9 10 + rtems_io_open 6 6 + rtems_io_close 6 6 + rtems_io_read 6 6 + rtems_io_write 6 5 + rtems_io_control 6 6 + +21 rtems_task_ident 1057 1058 + rtems_message_queue_ident 963 963 + rtems_semaphore_ident 1137 1136 + rtems_partition_ident 962 961 + rtems_region_ident 923 924 + rtems_port_ident 918 917 + rtems_timer_ident 942 941 + rtems_rate_monotonic_ident 924 925 + +22 rtems_message_queue_broadcast: task readied -- returns to caller 1084 1095 + rtems_message_queue_broadcast: no waiting tasks 147 148 + rtems_message_queue_broadcast: task readied -- preempts caller 1305 1268 + +23 rtems_timer_create 202 201 + rtems_timer_fire_after: inactive 261 261 + rtems_timer_fire_after: active 271 269 + rtems_timer_cancel: active 142 141 + rtems_timer_cancel: inactive 122 124 + rtems_timer_reset: inactive 222 222 + rtems_timer_reset: active 246 245 + rtems_timer_fire_when: inactive 312 311 + rtems_timer_fire_when: active 358 358 + rtems_timer_delete: active 263 263 + rtems_timer_delete: inactive 247 247 + rtems_task_wake_when 833 831 + +24 rtems_task_wake_after: yield -- returns to caller 99 98 + rtems_task_wake_after: yields -- preempts caller 479 478 + +25 rtems_clock_tick 313 318 + +26 _ISR_Disable 64 57 + _ISR_Flash 51 36 + _ISR_Enable 31 18 + _Thread_Disable_dispatch 53 37 + _Thread_Enable_dispatch 260 233 + _Thread_Set_state 446 463 + _Thread_Disptach (NO FP) 839 801 + context switch: no floating point contexts 673 653 + context switch: self 156 162 + context switch: to another task 84 70 + context switch: restore 1st FP task 1030 1013 + fp context switch: save idle, restore idle 969 948 + fp context switch: save idle, restore initialized 275 267 + fp context switch: save initialized, restore initialized 319 292 + _Thread_Resume 512 480 + _Thread_Unblock 121 139 + _Thread_Ready 199 203 + _Thread_Get 27 27 + _Semaphore_Get 20 21 + _Thread_Get: invalid id 5 5 + +27 interrupt entry overhead: returns to interrupted task 0 0 + interrupt exit overhead: returns to interrupted task 27 41 + interrupt entry overhead: returns to nested interrupt 0 0 + interrupt exit overhead: returns to nested interrupt 0 0 + interrupt entry overhead: returns to preempting task 0 0 + interrupt exit overhead: returns to preempting task 0 0 + +28 rtems_port_create 574 560 + rtems_port_external_to_internal 87 87 + rtems_port_internal_to_external 86 86 + rtems_port_delete 395 353 + +29 rtems_rate_monotonic_create 621 633 + rtems_rate_monotonic_period: initiate period -- returns to caller 773 694 + rtems_rate_monotonic_period: obtain status 295 284 + rtems_rate_monotonic_cancel 408 451 + rtems_rate_monotonic_delete: inactive 453 471 + rtems_rate_monotonic_delete: active 332 336 + rtems_rate_monotonic_period: conclude periods -- caller blocks 664 686 diff --git a/c/src/lib/libcpu/mips/clock/ckinit.c b/c/src/lib/libcpu/mips/clock/ckinit.c new file mode 100644 index 0000000000..9677a02b47 --- /dev/null +++ b/c/src/lib/libcpu/mips/clock/ckinit.c @@ -0,0 +1,245 @@ + +/* ckinit.c + * + * This file contains the clock driver initialization for the IDT 4650. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c: + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * ckinit.c,v 1.5 1995/10/30 21:53:23 joel Exp + */ + +#ifndef lint +static char _sccsid[] = "@(#)ckinit.c 08/20/96 1.3\n"; +#endif + +#include + +#include +#include +#include + +#include + +#include "clock.h" + +#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */ + +void Clock_exit( void ); +rtems_isr Clock_isr( rtems_vector_number vector ); + + +/* + * The interrupt vector number associated with the clock tick device + * driver. + */ + +#define CLOCK_VECTOR_MASK EXT_INT5 +#define CLOCK_VECTOR 0x7 + +/* + * Clock_driver_ticks is a monotonically increasing counter of the + * number of clock ticks since the driver was initialized. + */ + +volatile rtems_unsigned32 Clock_driver_ticks; + +/* + * Clock_isrs is the number of clock ISRs until the next invocation of + * the RTEMS clock tick routine. The clock tick device driver + * gets an interrupt once a millisecond and counts down until the + * length of time between the user configured microseconds per tick + * has passed. + */ + +rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ + +/* + * These are set by clock driver during its init + */ + +rtems_device_major_number rtems_clock_major = ~0; +rtems_device_minor_number rtems_clock_minor; + +/* + * The previous ISR on this clock tick interrupt vector. + */ + +rtems_isr_entry Old_ticker; + +void Clock_exit( void ); + +static unsigned32 mips_timer_rate = 0; + +/* + * Isr Handler + */ + +rtems_isr Clock_isr( + rtems_vector_number vector +) +{ +/* + * bump the number of clock driver ticks since initialization + * + * determine if it is time to announce the passing of tick as configured + * to RTEMS through the rtems_clock_tick directive + * + * perform any timer dependent tasks + */ + + /* refresh the internal CPU timer */ + mips_set_timer( mips_timer_rate ); + + Clock_driver_ticks += 1; + + rtems_clock_tick(); +} + +/* User callback shell (set from Clock_Control) */ +static void (*user_callback)(void); + +rtems_isr User_Clock_isr( + rtems_vector_number vector +) +{ + /* refresh the internal CPU timer */ + mips_set_timer( mips_timer_rate ); + + if (user_callback) + user_callback(); +} + +/* + * Install_clock + * + * Install a clock tick handleR and reprograms the chip. This + * is used to initially establish the clock tick. + */ + +void Install_clock( + rtems_isr_entry clock_isr +) +{ + /* + * Initialize the clock tick device driver variables + */ + + Clock_driver_ticks = 0; + Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; + + /* + * If ticks_per_timeslice is configured as non-zero, then the user + * wants a clock tick. + */ + + if ( BSP_Configuration.ticks_per_timeslice ) { + Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 ); + /* + * Hardware specific initialize goes here + */ + + mips_timer_rate = BSP_Configuration.microseconds_per_tick * CLOCKS_PER_MICROSECOND; + mips_set_timer( mips_timer_rate ); + enable_int(CLOCK_VECTOR_MASK); + } + + /* + * Schedule the clock cleanup routine to execute if the application exits. + */ + + atexit( Clock_exit ); +} + +/* + * Clean up before the application exits + */ + +void Clock_exit( void ) +{ + if ( BSP_Configuration.ticks_per_timeslice ) { + + /* mips: turn off the timer interrupts */ + disable_int(CLOCK_VECTOR_MASK); + + } +} + +/* + * Clock_initialize + * + * Device driver entry point for clock tick driver initialization. + */ + +rtems_device_driver Clock_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + Install_clock( Clock_isr ); + + /* + * make major/minor avail to others such as shared memory driver + */ + + rtems_clock_major = major; + rtems_clock_minor = minor; + + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver Clock_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + rtems_unsigned32 isrlevel; + rtems_libio_ioctl_args_t *args = pargp; + + if (args == 0) + goto done; + + /* + * This is hokey, but until we get a defined interface + * to do this, it will just be this simple... + */ + + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) + { + Clock_isr(CLOCK_VECTOR); + } + else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) + { + rtems_interrupt_disable( isrlevel ); + user_callback = (void (*)(void))args->buffer; + (void) set_vector( User_Clock_isr, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); + } + +done: + return RTEMS_SUCCESSFUL; +} diff --git a/c/src/lib/libcpu/mips/clock/clock.S b/c/src/lib/libcpu/mips/clock/clock.S new file mode 100644 index 0000000000..a41edf5ea5 --- /dev/null +++ b/c/src/lib/libcpu/mips/clock/clock.S @@ -0,0 +1,44 @@ +/* clock.s + * + * This file contains the assembly code for the IDT 4650 clock driver. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + */ +/* @(#)clock.S 08/20/96 1.2 */ + +#include +#include +#include + +FRAME(mips_set_timer,sp,0,ra) + .set noreorder + mfc0 t0,C0_COUNT + nop + addu t0,a0,t0 + mtc0 t0,C0_COMPARE + nop + j ra + .set reorder +ENDFRAME(mips_set_timer) + +FRAME(mips_get_timer,sp,0,ra) + .set noreorder + mfc0 v0,C0_COUNT + nop + j ra + .set reorder +ENDFRAME(mips_get_timer) diff --git a/c/src/lib/libcpu/mips/clock/clock.h b/c/src/lib/libcpu/mips/clock/clock.h new file mode 100644 index 0000000000..19bc7f6bfe --- /dev/null +++ b/c/src/lib/libcpu/mips/clock/clock.h @@ -0,0 +1,24 @@ +/* clock.s + * + * This file contains the assembly code for the IDT 4650 clock driver. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + */ + +/* @(#)clock.h 08/20/96 1.2 */ + +extern void mips_set_timer( unsigned32 timer_clock_interval ); diff --git a/c/src/lib/libcpu/mips/timer/gettime.S b/c/src/lib/libcpu/mips/timer/gettime.S new file mode 100644 index 0000000000..2c97c6e66e --- /dev/null +++ b/c/src/lib/libcpu/mips/timer/gettime.S @@ -0,0 +1,34 @@ +/* gettime.s + * + * This file contains the assembly code for the IDT 4650 timer driver. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + */ + +/* @(#)gettime.S 08/20/96 1.2 */ + +#include +#include +#include + +FRAME(mips_read_timer,sp,0,ra) + .set noreorder + mfc0 v0,C0_COUNT + nop + j ra + .set reorder +ENDFRAME(mips_read_timer) diff --git a/c/src/lib/libcpu/mips/timer/timer.c b/c/src/lib/libcpu/mips/timer/timer.c new file mode 100644 index 0000000000..a141232229 --- /dev/null +++ b/c/src/lib/libcpu/mips/timer/timer.c @@ -0,0 +1,136 @@ +/* timer.c + * + * This file contains the initialization code for the IDT 4650 timer driver. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * derived from src/lib/libbsp/no_cpu/no_bsp/timer/timer.c + * + * This file manages the benchmark timer used by the RTEMS Timing Test + * Suite. Each measured time period is demarcated by calls to + * Timer_initialize() and Read_timer(). Read_timer() usually returns + * the number of microseconds since Timer_initialize() exitted. + * + * NOTE: It is important that the timer start/stop overhead be + * determined when porting or modifying this code. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * timer.c,v 1.2 1995/05/31 16:56:39 joel Exp + */ + +#ifndef lint +static char _sccsid[] = "@(#)timer.c 08/20/96 1.5\n"; +#endif + +#include +#include + +#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) +#define TIMER_MAX_VALUE 0xffffffff + +extern unsigned32 mips_read_timer( void ); + +static rtems_boolean Timer_driver_Find_average_overhead; +static unsigned32 Timer_initial_value = 0; + +void Timer_initialize( void ) +{ + Timer_initial_value = mips_read_timer(); + /* + * Somehow start the timer + */ + + /* Timer on 4650 is always running */ +} + +/* + * The following controls the behavior of Read_timer(). + * + * AVG_OVEREHAD is the overhead for starting and stopping the timer. It + * is usually deducted from the number returned. + * + * LEAST_VALID is the lowest number this routine should trust. Numbers + * below this are "noise" and zero is returned. + */ + +#define AVG_OVERHEAD 8 /* It typically takes X.X microseconds */ + /* (Y countdowns) to start/stop the timer. */ + /* This value is in cycles. */ +#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */ + +int Read_timer( void ) +{ + unsigned64 clicks; + unsigned32 total; + + /* + * Read the timer and see how many clicks it has been since we started. + */ + + clicks = mips_read_timer(); /* XXX: read some HW here */ + if (clicks < Timer_initial_value) + { + clicks += TIMER_MAX_VALUE; + } + clicks -= Timer_initial_value; + + /* + * Total is calculated by taking into account the number of timer overflow + * interrupts since the timer was initialized and clicks since the last + * interrupts. + */ +#if 0 /* leave total in number of cycles */ + total = clicks / CLOCKS_PER_MICROSECOND; +#else + total = clicks; +#endif + + if ( Timer_driver_Find_average_overhead == 1 ) + return total; /* in # cycles units */ + else { + if ( total < LEAST_VALID ) + return 0; /* below timer resolution */ + /* + * leave total in cycles + */ + return (total - AVG_OVERHEAD); + } +} + +/* + * Empty function call used in loops to measure basic cost of looping + * in Timing Test Suite. + */ + +rtems_status_code Empty_function( void ) +{ + return RTEMS_SUCCESSFUL; +} + +void Set_find_average_overhead( + rtems_boolean find_flag +) +{ + Timer_driver_Find_average_overhead = find_flag; +} + diff --git a/c/src/lib/libcpu/mips64orion/clock/ckinit.c b/c/src/lib/libcpu/mips64orion/clock/ckinit.c new file mode 100644 index 0000000000..9677a02b47 --- /dev/null +++ b/c/src/lib/libcpu/mips64orion/clock/ckinit.c @@ -0,0 +1,245 @@ + +/* ckinit.c + * + * This file contains the clock driver initialization for the IDT 4650. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libbsp/no_cpu/no_bsp/clock/ckinit.c: + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * ckinit.c,v 1.5 1995/10/30 21:53:23 joel Exp + */ + +#ifndef lint +static char _sccsid[] = "@(#)ckinit.c 08/20/96 1.3\n"; +#endif + +#include + +#include +#include +#include + +#include + +#include "clock.h" + +#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) /* equivalent to CPU clock speed in MHz */ + +void Clock_exit( void ); +rtems_isr Clock_isr( rtems_vector_number vector ); + + +/* + * The interrupt vector number associated with the clock tick device + * driver. + */ + +#define CLOCK_VECTOR_MASK EXT_INT5 +#define CLOCK_VECTOR 0x7 + +/* + * Clock_driver_ticks is a monotonically increasing counter of the + * number of clock ticks since the driver was initialized. + */ + +volatile rtems_unsigned32 Clock_driver_ticks; + +/* + * Clock_isrs is the number of clock ISRs until the next invocation of + * the RTEMS clock tick routine. The clock tick device driver + * gets an interrupt once a millisecond and counts down until the + * length of time between the user configured microseconds per tick + * has passed. + */ + +rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ + +/* + * These are set by clock driver during its init + */ + +rtems_device_major_number rtems_clock_major = ~0; +rtems_device_minor_number rtems_clock_minor; + +/* + * The previous ISR on this clock tick interrupt vector. + */ + +rtems_isr_entry Old_ticker; + +void Clock_exit( void ); + +static unsigned32 mips_timer_rate = 0; + +/* + * Isr Handler + */ + +rtems_isr Clock_isr( + rtems_vector_number vector +) +{ +/* + * bump the number of clock driver ticks since initialization + * + * determine if it is time to announce the passing of tick as configured + * to RTEMS through the rtems_clock_tick directive + * + * perform any timer dependent tasks + */ + + /* refresh the internal CPU timer */ + mips_set_timer( mips_timer_rate ); + + Clock_driver_ticks += 1; + + rtems_clock_tick(); +} + +/* User callback shell (set from Clock_Control) */ +static void (*user_callback)(void); + +rtems_isr User_Clock_isr( + rtems_vector_number vector +) +{ + /* refresh the internal CPU timer */ + mips_set_timer( mips_timer_rate ); + + if (user_callback) + user_callback(); +} + +/* + * Install_clock + * + * Install a clock tick handleR and reprograms the chip. This + * is used to initially establish the clock tick. + */ + +void Install_clock( + rtems_isr_entry clock_isr +) +{ + /* + * Initialize the clock tick device driver variables + */ + + Clock_driver_ticks = 0; + Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; + + /* + * If ticks_per_timeslice is configured as non-zero, then the user + * wants a clock tick. + */ + + if ( BSP_Configuration.ticks_per_timeslice ) { + Old_ticker = (rtems_isr_entry) set_vector( clock_isr, CLOCK_VECTOR, 1 ); + /* + * Hardware specific initialize goes here + */ + + mips_timer_rate = BSP_Configuration.microseconds_per_tick * CLOCKS_PER_MICROSECOND; + mips_set_timer( mips_timer_rate ); + enable_int(CLOCK_VECTOR_MASK); + } + + /* + * Schedule the clock cleanup routine to execute if the application exits. + */ + + atexit( Clock_exit ); +} + +/* + * Clean up before the application exits + */ + +void Clock_exit( void ) +{ + if ( BSP_Configuration.ticks_per_timeslice ) { + + /* mips: turn off the timer interrupts */ + disable_int(CLOCK_VECTOR_MASK); + + } +} + +/* + * Clock_initialize + * + * Device driver entry point for clock tick driver initialization. + */ + +rtems_device_driver Clock_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + Install_clock( Clock_isr ); + + /* + * make major/minor avail to others such as shared memory driver + */ + + rtems_clock_major = major; + rtems_clock_minor = minor; + + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver Clock_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + rtems_unsigned32 isrlevel; + rtems_libio_ioctl_args_t *args = pargp; + + if (args == 0) + goto done; + + /* + * This is hokey, but until we get a defined interface + * to do this, it will just be this simple... + */ + + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) + { + Clock_isr(CLOCK_VECTOR); + } + else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) + { + rtems_interrupt_disable( isrlevel ); + user_callback = (void (*)(void))args->buffer; + (void) set_vector( User_Clock_isr, CLOCK_VECTOR, 1 ); + rtems_interrupt_enable( isrlevel ); + } + +done: + return RTEMS_SUCCESSFUL; +} diff --git a/c/src/lib/libcpu/mips64orion/clock/clock.S b/c/src/lib/libcpu/mips64orion/clock/clock.S new file mode 100644 index 0000000000..a41edf5ea5 --- /dev/null +++ b/c/src/lib/libcpu/mips64orion/clock/clock.S @@ -0,0 +1,44 @@ +/* clock.s + * + * This file contains the assembly code for the IDT 4650 clock driver. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + */ +/* @(#)clock.S 08/20/96 1.2 */ + +#include +#include +#include + +FRAME(mips_set_timer,sp,0,ra) + .set noreorder + mfc0 t0,C0_COUNT + nop + addu t0,a0,t0 + mtc0 t0,C0_COMPARE + nop + j ra + .set reorder +ENDFRAME(mips_set_timer) + +FRAME(mips_get_timer,sp,0,ra) + .set noreorder + mfc0 v0,C0_COUNT + nop + j ra + .set reorder +ENDFRAME(mips_get_timer) diff --git a/c/src/lib/libcpu/mips64orion/clock/clock.h b/c/src/lib/libcpu/mips64orion/clock/clock.h new file mode 100644 index 0000000000..19bc7f6bfe --- /dev/null +++ b/c/src/lib/libcpu/mips64orion/clock/clock.h @@ -0,0 +1,24 @@ +/* clock.s + * + * This file contains the assembly code for the IDT 4650 clock driver. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + */ + +/* @(#)clock.h 08/20/96 1.2 */ + +extern void mips_set_timer( unsigned32 timer_clock_interval ); diff --git a/c/src/lib/libcpu/mips64orion/timer/gettime.S b/c/src/lib/libcpu/mips64orion/timer/gettime.S new file mode 100644 index 0000000000..2c97c6e66e --- /dev/null +++ b/c/src/lib/libcpu/mips64orion/timer/gettime.S @@ -0,0 +1,34 @@ +/* gettime.s + * + * This file contains the assembly code for the IDT 4650 timer driver. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + */ + +/* @(#)gettime.S 08/20/96 1.2 */ + +#include +#include +#include + +FRAME(mips_read_timer,sp,0,ra) + .set noreorder + mfc0 v0,C0_COUNT + nop + j ra + .set reorder +ENDFRAME(mips_read_timer) diff --git a/c/src/lib/libcpu/mips64orion/timer/timer.c b/c/src/lib/libcpu/mips64orion/timer/timer.c new file mode 100644 index 0000000000..a141232229 --- /dev/null +++ b/c/src/lib/libcpu/mips64orion/timer/timer.c @@ -0,0 +1,136 @@ +/* timer.c + * + * This file contains the initialization code for the IDT 4650 timer driver. + * + * Author: Craig Lebakken + * + * COPYRIGHT (c) 1996 by Transition Networks Inc. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of Transition Networks not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * Transition Networks makes no representations about the suitability + * of this software for any purpose. + * + * derived from src/lib/libbsp/no_cpu/no_bsp/timer/timer.c + * + * This file manages the benchmark timer used by the RTEMS Timing Test + * Suite. Each measured time period is demarcated by calls to + * Timer_initialize() and Read_timer(). Read_timer() usually returns + * the number of microseconds since Timer_initialize() exitted. + * + * NOTE: It is important that the timer start/stop overhead be + * determined when porting or modifying this code. + * + * COPYRIGHT (c) 1989, 1990, 1991, 1992, 1993, 1994. + * On-Line Applications Research Corporation (OAR). + * All rights assigned to U.S. Government, 1994. + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + * timer.c,v 1.2 1995/05/31 16:56:39 joel Exp + */ + +#ifndef lint +static char _sccsid[] = "@(#)timer.c 08/20/96 1.5\n"; +#endif + +#include +#include + +#define CLOCKS_PER_MICROSECOND ( CPU_CLOCK_RATE_MHZ ) +#define TIMER_MAX_VALUE 0xffffffff + +extern unsigned32 mips_read_timer( void ); + +static rtems_boolean Timer_driver_Find_average_overhead; +static unsigned32 Timer_initial_value = 0; + +void Timer_initialize( void ) +{ + Timer_initial_value = mips_read_timer(); + /* + * Somehow start the timer + */ + + /* Timer on 4650 is always running */ +} + +/* + * The following controls the behavior of Read_timer(). + * + * AVG_OVEREHAD is the overhead for starting and stopping the timer. It + * is usually deducted from the number returned. + * + * LEAST_VALID is the lowest number this routine should trust. Numbers + * below this are "noise" and zero is returned. + */ + +#define AVG_OVERHEAD 8 /* It typically takes X.X microseconds */ + /* (Y countdowns) to start/stop the timer. */ + /* This value is in cycles. */ +#define LEAST_VALID 1 /* Don't trust a clicks value lower than this */ + +int Read_timer( void ) +{ + unsigned64 clicks; + unsigned32 total; + + /* + * Read the timer and see how many clicks it has been since we started. + */ + + clicks = mips_read_timer(); /* XXX: read some HW here */ + if (clicks < Timer_initial_value) + { + clicks += TIMER_MAX_VALUE; + } + clicks -= Timer_initial_value; + + /* + * Total is calculated by taking into account the number of timer overflow + * interrupts since the timer was initialized and clicks since the last + * interrupts. + */ +#if 0 /* leave total in number of cycles */ + total = clicks / CLOCKS_PER_MICROSECOND; +#else + total = clicks; +#endif + + if ( Timer_driver_Find_average_overhead == 1 ) + return total; /* in # cycles units */ + else { + if ( total < LEAST_VALID ) + return 0; /* below timer resolution */ + /* + * leave total in cycles + */ + return (total - AVG_OVERHEAD); + } +} + +/* + * Empty function call used in loops to measure basic cost of looping + * in Timing Test Suite. + */ + +rtems_status_code Empty_function( void ) +{ + return RTEMS_SUCCESSFUL; +} + +void Set_find_average_overhead( + rtems_boolean find_flag +) +{ + Timer_driver_Find_average_overhead = find_flag; +} + diff --git a/c/src/lib/start/mips64orion/idt_csu.S b/c/src/lib/start/mips64orion/idt_csu.S new file mode 100644 index 0000000000..bbedf0c5dd --- /dev/null +++ b/c/src/lib/start/mips64orion/idt_csu.S @@ -0,0 +1,298 @@ +/* + +Based upon IDT provided code with the following release: + +This source code has been made available to you by IDT on an AS-IS +basis. Anyone receiving this source is licensed under IDT copyrights +to use it in any way he or she deems fit, including copying it, +modifying it, compiling it, and redistributing it either with or +without modifications. No license under IDT patents or patent +applications is to be implied by the copyright license. + +Any user of this software should understand that IDT cannot provide +technical support for this software and will not be responsible for +any consequences resulting from the use of this software. + +Any person who transfers this source code or any derivative work must +include the IDT copyright notice, this paragraph, and the preceeding +two paragraphs in the transferred software. + +COPYRIGHT IDT CORPORATION 1996 +LICENSED MATERIAL - PROGRAM PROPERTY OF IDT + +*/ + +/************************************************************************* +** +** Copyright 1991-95 Integrated Device Technology, Inc. +** All Rights Reserved +** +** idt_csu.S -- IDT stand alone startup code +** +**************************************************************************/ +#include +#include +#include + + +.extern _fbss,4 /* this is defined by the linker */ +.extern end,4 /* this is defined by the linker */ + +.lcomm sim_mem_cfg_struct,12 + + .text + + +#define TMP_STKSIZE 1024 + +/************************************************************************** +** +** start - Typicl standalone start up code required for R3000/R4000 +** +** +** 1) Initialize the STATUS Register +** a) Clear parity error bit +** b) Set co_processor 1 usable bit ON +** c) Clear all IntMask Enables +** d) Set kernel/disabled mode +** 2) Initialize Cause Register +** a) clear software interrupt bits +** 3) Determine FPU installed or not +** if not, clear CoProcessor 1 usable bit +** 4) Clear bss area +** 5) MUST allocate temporary stack until memory size determined +** It MUST be uncached to prevent overwriting when caches are cleared +** 6) Install exception handlers +** 7) Determine memory and cache sizes +** 8) Establish permanent stack (cached or uncached as defined by bss) +** 9) Flush Instruction and Data caches +** 10) If there is a Translation Lookaside Buffer, Clear the TLB +** 11) Execute initialization code if the IDT/c library is to be used +** +** 12) Jump to user's "main()" +** 13) Jump to promexit +** +** IDT/C 5.x defines _R3000, IDT/C 6.x defines _R4000 internally. +** This is used to mark code specific to R3xxx or R4xxx processors. +** IDT/C 6.x defines __mips to be the ISA level for which we're +** generating code. This is used to make sure the stack etc. is +** double word aligned, when using -mips3 (default) or -mips2, +** when compiling with IDT/C6.x +** +***************************************************************************/ + +FRAME(start,sp,0,ra) + + .set noreorder +#ifdef _R3000 + li v0,SR_PE|SR_CU1 /* reset parity error and set */ + /* cp1 usable */ +#endif +#ifdef _R4000 +#if __mips==3 || defined(R4650) + li v0,SR_CU1|SR_DE|SR_FR /* initally clear ERL, enable FPA 64bit regs*/ + /* 4650: Need fr to be set anyway */ +#else + li v0,SR_CU1|SR_DE /* initally clear ERL, enable FPA 32bit regs*/ +#endif mips3 +#endif + + mtc0 v0,C0_SR /* clr IntMsks/ kernel/disabled mode */ + nop + mtc0 zero,C0_CAUSE /* clear software interrupts */ + nop + +#ifdef _R4000 + li v0,CFG_C_NONCOHERENT # initialise default cache mode + mtc0 v0,C0_CONFIG +#endif + +/* +** check to see if an fpu is really plugged in +*/ + li t3,0xaaaa5555 /* put a's and 5's in t3 */ + mtc1 t3,fp0 /* try to write them into fp0 */ + mtc1 zero,fp1 /* try to write zero in fp */ + mfc1 t0,fp0 + mfc1 t1,fp1 + nop + bne t0,t3,1f /* branch if no match */ + nop + bne t1,zero,1f /* double check for positive id */ + nop + /* We have a FPU. clear fcsr */ + ctc1 zero, fcr31 + j 2f /* status register already correct */ + nop +1: +#ifdef _R3000 + li v0, SR_PE /* reset parity error/NO cp1 usable */ +#endif + +#ifdef _R4000 + li v0,SR_DE /* clear ERL and disable FPA */ +#endif + + mtc0 v0, C0_SR /* reset status register */ +2: + la gp, _gp + + la v0,_fbss /* clear bss before using it */ + la v1,end /* end of bss */ +3: sw zero,0(v0) + bltu v0,v1,3b + add v0,4 + + +/************************************************************************ +** +** Temporary Stack - needed to handle stack saves until +** memory size is determined and permanent stack set +** +** MUST be uncached to avoid confusion at cache +** switching during memory sizing +** +*************************************************************************/ +#if __mips==3 + /* For MIPS 3, we need to be sure that the stack is aligned on a + * double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 11f /* Last three bits Zero, already aligned */ + nop + add v0, 4 +11: +#endif + + or v0, K1BASE /* switch to uncached */ + add v1, v0, TMP_STKSIZE /* end of bss + length of tmp stack */ + sub v1, v1, (4*4) /* overhead */ + move sp, v1 /* set sp to top of stack */ +4: sw zero, 0(v0) + bltu v0, v1, 4b /* clear out temp stack */ + add v0, 4 + + jal init_exc_vecs /* install exception handlers */ + nop /* MUST do before memory probes */ + + la v0, 5f + li v1, K1BASE /* force into uncached space */ + or v0, v1 /* during memory/cache probes */ + j v0 + nop +5: + la a0, sim_mem_cfg_struct + jal sim_mem_cfg /* Make SIM call to get mem size */ + nop + la a0, sim_mem_cfg_struct + lw a0, 0(a0) /* Get memory size from struct */ +#ifdef _R3000 + jal config_Icache + nop + jal config_Dcache /* determine size of D & I caches */ + nop +#endif +#ifdef _R4000 + jal config_cache /* determine size of D & I caches */ + nop +#endif + + move v0, a0 /* mem_size */ + +#if __mips==3 + /* For MIPS 3, we need to be sure that the stack (and hence v0 + * here) is aligned on a double word boundary. + */ + andi t0, v0, 0x7 + beqz t0, 12f /* Last three bits Zero, already aligned */ + nop + subu v0, 4 /* mem_size was not aligned on doubleword bdry????*/ +12: +#endif + + + +/************************************************************************** +** +** Permanent Stack - now know top of memory, put permanent stack there +** +***************************************************************************/ + + la t2, _fbss /* cache mode as linked */ + and t2, 0xF0000000 /* isolate segment */ + la t1, 6f + j t1 /* back to original cache mode */ + nop +6: + or v0, t2 /* stack back to original cache mode */ + addiu v0,v0,-16 /* overhead */ + move sp, v0 /* now replace count w top of memory */ + move v1, v0 + subu v1, P_STACKSIZE /* clear requested stack size */ + +7: sw zero, 0(v1) /* clear P_STACKSIZE stack */ + bltu v1,v0,7b + add v1, 4 + .set reorder + +#ifdef _R3000 + jal flush_Icache + jal flush_Dcache /* flush Data & Instruction caches */ +#endif +#ifdef _R4000 + jal flush_cache_nowrite /* flush Data & Instruction caches */ +#endif + + + +/************************************************************************** +** +** If this chip supports a Translation Lookaside Buffer, clear it +** +***************************************************************************/ + + .set noreorder + mfc0 t1, C0_SR /* look at Status Register */ + nop + .set reorder +#ifdef _R3000 + li t2, SR_TS /* TLB Shutdown bit */ + and t1,t2 /* TLB Shutdown if 1 */ + bnez t1, 8f /* skip clearing if no TLB */ +#endif + +#ifndef R4650 + jal init_tlb /* clear the tlb */ +#endif + + +/************************************************************************ +** +** Initialization required if using IDT/c or libc.a, standard C Lib +** +** can SKIP if not necessary for application +** +************************************************************************/ +8: + + jal idtsim_init_sbrk + jal idtsim_init_file +/*********************** END I/O initialization **********************/ + + + jal main + + jal idtsim_promexit + +ENDFRAME(start) + + + .globl sim_mem_cfg +sim_mem_cfg: + .set noat + .set noreorder + li AT, (0xbfc00000+((55)*8)) + jr AT + nop + .set at + .set reorder -- cgit v1.2.3