From 886b962e7b8c7c15f7d849925d7ca48482a05bca Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sun, 3 Jul 2016 09:30:20 +0200 Subject: bsp/arm: Report correct maximal cache line length for ARM Cortex-A + L2C-310. Updates #2782 Updates #2783 --- c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'c/src/lib') diff --git a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h index 35c80026d4..e83b55cfa6 100644 --- a/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h +++ b/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h @@ -72,6 +72,10 @@ extern "C" { /* These two defines also ensure that the rtems_cache_* functions have bodies */ #define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT #define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT +#if defined(__ARM_ARCH_7A__) +/* Some/many ARM Cortex-A cores have L1 data line lenght 64 bytes */ +#define CPU_MAXIMAL_CACHE_ALIGNMENT 64 +#endif #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \ ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS -- cgit v1.2.3