From 50cf94da7e57a9e83d7c0753dd55eae5fd55455a Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Fri, 20 Mar 1998 17:16:31 +0000 Subject: SH port submitted from Ralf Corsepius . --- c/src/lib/libbsp/sh/Makefile.in | 15 ++ c/src/lib/libbsp/sh/gensh1/Makefile.in | 22 ++ c/src/lib/libbsp/sh/gensh1/README | 50 ++++ c/src/lib/libbsp/sh/gensh1/bsp_specs | 22 ++ c/src/lib/libbsp/sh/gensh1/include/Makefile.in | 37 +++ c/src/lib/libbsp/sh/gensh1/include/bsp.h | 133 +++++++++++ c/src/lib/libbsp/sh/gensh1/include/coverhd.h | 130 +++++++++++ c/src/lib/libbsp/sh/gensh1/startup/Makefile.in | 59 +++++ c/src/lib/libbsp/sh/gensh1/startup/bspclean.c | 40 ++++ c/src/lib/libbsp/sh/gensh1/startup/bspstart.c | 278 ++++++++++++++++++++++ c/src/lib/libbsp/sh/gensh1/startup/linkcmds | 203 ++++++++++++++++ c/src/lib/libbsp/sh/gensh1/times | 195 ++++++++++++++++ c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in | 64 +++++ c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c | 311 +++++++++++++++++++++++++ c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c | 252 ++++++++++++++++++++ c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c | 311 +++++++++++++++++++++++++ 16 files changed, 2122 insertions(+) create mode 100644 c/src/lib/libbsp/sh/Makefile.in create mode 100644 c/src/lib/libbsp/sh/gensh1/Makefile.in create mode 100644 c/src/lib/libbsp/sh/gensh1/README create mode 100644 c/src/lib/libbsp/sh/gensh1/bsp_specs create mode 100644 c/src/lib/libbsp/sh/gensh1/include/Makefile.in create mode 100644 c/src/lib/libbsp/sh/gensh1/include/bsp.h create mode 100644 c/src/lib/libbsp/sh/gensh1/include/coverhd.h create mode 100644 c/src/lib/libbsp/sh/gensh1/startup/Makefile.in create mode 100644 c/src/lib/libbsp/sh/gensh1/startup/bspclean.c create mode 100644 c/src/lib/libbsp/sh/gensh1/startup/bspstart.c create mode 100644 c/src/lib/libbsp/sh/gensh1/startup/linkcmds create mode 100644 c/src/lib/libbsp/sh/gensh1/times create mode 100644 c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in create mode 100644 c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c create mode 100644 c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c create mode 100644 c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c (limited to 'c/src/lib') diff --git a/c/src/lib/libbsp/sh/Makefile.in b/c/src/lib/libbsp/sh/Makefile.in new file mode 100644 index 0000000000..3479cee62d --- /dev/null +++ b/c/src/lib/libbsp/sh/Makefile.in @@ -0,0 +1,15 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH=@srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/directory.cfg + +# Descend into the $(RTEMS_BSP_FAMILY) directory +SUB_DIRS=$(RTEMS_BSP_FAMILY) diff --git a/c/src/lib/libbsp/sh/gensh1/Makefile.in b/c/src/lib/libbsp/sh/gensh1/Makefile.in new file mode 100644 index 0000000000..968560eed7 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/Makefile.in @@ -0,0 +1,22 @@ +# +# $Id $ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH=@srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/directory.cfg + +# wrapup is the one that actually builds and installs the library +# from the individual .rel files built in other directories +# was: +# SUB_DIRS=include startup clock console shmsupp timer wrapup +# is +SUB_DIRS=include \ + startup \ + wrapup + diff --git a/c/src/lib/libbsp/sh/gensh1/README b/c/src/lib/libbsp/sh/gensh1/README new file mode 100644 index 0000000000..c75ad9927e --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/README @@ -0,0 +1,50 @@ +# +# $Id$ +# +# Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) +# + +BSP NAME: generic SH1 (gensh1) +BOARD: n/a +BUS: n/a +CPU FAMILY: Hitachi SH +CPU: SH 7032 +COPROCESSORS: none +MODE: n/a + +DEBUG MONITOR: gdb + +PERIPHERALS +=========== +TIMERS: on-chip + RESOLUTION: cf. Hitachi SH 703X Hardware Manual (Phi/4) +SERIAL PORTS: on-chip (with 2 ports) +REAL-TIME CLOCK: none +DMA: not used +VIDEO: none +SCSI: none +NETWORKING: none + +DRIVER INFORMATION +================== +CLOCK DRIVER: on-chip timer +IOSUPP DRIVER: default +SHMSUPP: default +TIMER DRIVER: on-chip timer +TTY DRIVER: /dev/null (stub) + +STDIO +===== +PORT: /dev/null (stub) +ELECTRICAL: n/a +BAUD: n/a +BITS PER CHARACTER: n/a +PARITY: n/a +STOP BITS: n/a + +NOTES +===== + +(1) Only stub console driver available at the moment. + Driver for the on-chip serial devices (sci) will be available soon. + diff --git a/c/src/lib/libbsp/sh/gensh1/bsp_specs b/c/src/lib/libbsp/sh/gensh1/bsp_specs new file mode 100644 index 0000000000..9436cdcd72 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/bsp_specs @@ -0,0 +1,22 @@ +%rename cpp old_cpp +%rename lib old_lib +%rename endfile old_endfile +%rename startfile old_startfile +%rename link old_link + +*cpp: +%(old_cpp) %{qrtems: -D__embedded__} -Asystem(embedded) + +*lib: +%{!qrtems: %(old_lib)} \ +%{qrtems: --start-group %{!qrtems_debug: -lrtemsall } %{qrtems_debug: -lrtemsall_g} \ + -lc -lgcc --end-group \ + %{!qnolinkcmds: -T linkcmds%s}} + +*startfile: +%{!qrtems: %(old_startfile)} \ +%{qrtems: %{qrtems_debug: start_g.o%s} %{!qrtems_debug: start.o%s}} + +*link: +%{!qrtems: %(old_link)} %{qrtems: -dc -dp -N -e _start} + diff --git a/c/src/lib/libbsp/sh/gensh1/include/Makefile.in b/c/src/lib/libbsp/sh/gensh1/include/Makefile.in new file mode 100644 index 0000000000..2a2cd51b24 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/include/Makefile.in @@ -0,0 +1,37 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH=@srcdir@ +RTEMS_ROOT=@top_srcdir@ +PROJECT_ROOT=@PROJECT_ROOT@ + +H_FILES = \ + $(srcdir)/bsp.h \ + $(srcdir)/coverhd.h + +# +# Equate files are for including from assembly preprocessed by +# gm4 or gasp. No examples are provided except for those for +# other CPUs. The best way to generate them would be to +# provide a program which generates the constants used based +# on the C equivalents. +# + +EQ_FILES = + +SRCS=$(H_FILES) $(EQ_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +all: $(SRCS) + $(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE) + $(INSTALL) -m 444 $(EQ_FILES) $(PROJECT_INCLUDE) + +install: all diff --git a/c/src/lib/libbsp/sh/gensh1/include/bsp.h b/c/src/lib/libbsp/sh/gensh1/include/bsp.h new file mode 100644 index 0000000000..3bca4d7da1 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/include/bsp.h @@ -0,0 +1,133 @@ +/* + * This include file contains all board IO definitions. + * + * generic sh1 + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __gensh1_h +#define __gensh1_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CPU_CONSOLE_DEVNAME "/dev/null" + + +#include +#include +#include +#include + +/* + * Define the time limits for RTEMS Test Suite test durations. + * Long test and short test duration limits are provided. These + * values are in seconds and need to be converted to ticks for the + * application. + * + */ + +#define MAX_LONG_TEST_DURATION 300 /* 5 minutes = 300 seconds */ +#define MAX_SHORT_TEST_DURATION 3 /* 3 seconds */ + +/* + * Stuff for Time Test 27 + */ + +#define MUST_WAIT_FOR_INTERRUPT 0 + +#define Install_tm27_vector( handler ) set_vector( (handler), 0, 1 ) + +#define Cause_tm27_intr() + +#define Clear_tm27_intr() + +#define Lower_tm27_intr() + +/* Constants */ + +#define MHZ 20 + +/* + * Defined in the linker script 'linkcmds' + */ + +extern unsigned32 HeapStart ; +extern unsigned32 HeapEnd ; +extern unsigned32 WorkSpaceStart ; +extern unsigned32 WorkSpaceEnd ; + +extern void *CPU_Interrupt_stack_low ; +extern void *CPU_Interrupt_stack_high ; + + +/* miscellaneous stuff assumed to exist */ + +extern rtems_configuration_table BSP_Configuration; + +extern int bsp_start( int argc, char **argv, char **env ); + +extern void bsp_cleanup( void ); + +/* + * Device Driver Table Entries + */ + +/* + * We redefine CONSOLE_DRIVER_TABLE_ENTRY to redirect /dev/console + */ +#if defined(CONSOLE_DRIVER_TABLE_ENTRY) +#warning Overwriting CONSOLE_DRIVER_TABLE_ENTRY +#undef CONSOLE_DRIVER_TABLE_ENTRY +#endif + +#define CONSOLE_DRIVER_TABLE_ENTRY \ + DEVNULL_DRIVER_TABLE_ENTRY, \ + { console_initialize, console_open, console_close, \ + console_read, console_write, console_control } + +/* + * NOTE: Use the standard Clock driver entry + */ + +/* + * How many libio files we want + */ + +#define BSP_LIBIO_MAX_FDS 20 + +/* + * FIXME: Should this go to libcpu/sh/sh7032 ? + */ +/* functions */ +sh_isr_entry set_vector( /* returns old vector */ + rtems_isr_entry handler, /* isr routine */ + rtems_vector_number vector, /* vector number */ + int type /* RTEMS or RAW intr */ +); + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/sh/gensh1/include/coverhd.h b/c/src/lib/libbsp/sh/gensh1/include/coverhd.h new file mode 100644 index 0000000000..570d21d0cb --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/include/coverhd.h @@ -0,0 +1,130 @@ +/* coverhd.h + * + * This include file has defines to represent the overhead associated + * with calling a particular directive from C. These are used in the + * Timing Test Suite to ignore the overhead required to pass arguments + * to directives. On some CPUs and/or target boards, this overhead + * is significant and makes it difficult to distinguish internal + * RTEMS execution time from that used to call the directive. + * This file should be updated after running the C overhead timing + * test. Once this update has been performed, the RTEMS Time Test + * Suite should be rebuilt to account for these overhead times in the + * timing results. + * + * NOTE: If these are all zero, then the times reported include all + * all calling overhead including passing of arguments. + * + * + * These are the figures tmoverhd.exe reported with egcs-980205 -O3 + * on a Diesner OktagonSH/Amos-2.1 board with SH7032/20MHz + * + * These results are assumed to be applicable to most SH7032/20MHz boards + * + * Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#ifndef __COVERHD_h +#define __COVERHD_h + +#ifdef __cplusplus +extern "C" { +#endif + +#define CALLING_OVERHEAD_INITIALIZE_EXECUTIVE 4 +#define CALLING_OVERHEAD_SHUTDOWN_EXECUTIVE 4 +#define CALLING_OVERHEAD_TASK_CREATE 9 +#define CALLING_OVERHEAD_TASK_IDENT 6 +#define CALLING_OVERHEAD_TASK_START 5 +#define CALLING_OVERHEAD_TASK_RESTART 5 +#define CALLING_OVERHEAD_TASK_DELETE 4 +#define CALLING_OVERHEAD_TASK_SUSPEND 4 +#define CALLING_OVERHEAD_TASK_RESUME 4 +#define CALLING_OVERHEAD_TASK_SET_PRIORITY 5 +#define CALLING_OVERHEAD_TASK_MODE 5 +#define CALLING_OVERHEAD_TASK_GET_NOTE 5 +#define CALLING_OVERHEAD_TASK_SET_NOTE 5 +#define CALLING_OVERHEAD_TASK_WAKE_WHEN 14 +#define CALLING_OVERHEAD_TASK_WAKE_AFTER 4 +#define CALLING_OVERHEAD_INTERRUPT_CATCH 5 +#define CALLING_OVERHEAD_CLOCK_GET 16 +#define CALLING_OVERHEAD_CLOCK_SET 14 +#define CALLING_OVERHEAD_CLOCK_TICK 3 + +#define CALLING_OVERHEAD_TIMER_CREATE 4 +#define CALLING_OVERHEAD_TIMER_IDENT 4 +#define CALLING_OVERHEAD_TIMER_DELETE 4 +#define CALLING_OVERHEAD_TIMER_FIRE_AFTER 6 +#define CALLING_OVERHEAD_TIMER_FIRE_WHEN 20 +#define CALLING_OVERHEAD_TIMER_RESET 4 +#define CALLING_OVERHEAD_TIMER_CANCEL 4 +#define CALLING_OVERHEAD_SEMAPHORE_CREATE 7 +#define CALLING_OVERHEAD_SEMAPHORE_IDENT 5 +#define CALLING_OVERHEAD_SEMAPHORE_DELETE 4 +#define CALLING_OVERHEAD_SEMAPHORE_OBTAIN 5 +#define CALLING_OVERHEAD_SEMAPHORE_RELEASE 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_CREATE 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_IDENT 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_DELETE 4 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_SEND 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_URGENT 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_BROADCAST 5 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_RECEIVE 6 +#define CALLING_OVERHEAD_MESSAGE_QUEUE_FLUSH 5 + +#define CALLING_OVERHEAD_EVENT_SEND 6 +#define CALLING_OVERHEAD_EVENT_RECEIVE 5 +#define CALLING_OVERHEAD_SIGNAL_CATCH 4 +#define CALLING_OVERHEAD_SIGNAL_SEND 4 +#define CALLING_OVERHEAD_PARTITION_CREATE 9 +#define CALLING_OVERHEAD_PARTITION_IDENT 5 +#define CALLING_OVERHEAD_PARTITION_DELETE 4 +#define CALLING_OVERHEAD_PARTITION_GET_BUFFER 6 +#define CALLING_OVERHEAD_PARTITION_RETURN_BUFFER 6 +#define CALLING_OVERHEAD_REGION_CREATE 9 +#define CALLING_OVERHEAD_REGION_IDENT 5 +#define CALLING_OVERHEAD_REGION_DELETE 4 +#define CALLING_OVERHEAD_REGION_GET_SEGMENT 9 +#define CALLING_OVERHEAD_REGION_RETURN_SEGMENT 5 +#define CALLING_OVERHEAD_PORT_CREATE 9 +#define CALLING_OVERHEAD_PORT_IDENT 4 +#define CALLING_OVERHEAD_PORT_DELETE 4 +#define CALLING_OVERHEAD_PORT_EXTERNAL_TO_INTERNAL 7 +#define CALLING_OVERHEAD_PORT_INTERNAL_TO_EXTERNAL 8 + +#define CALLING_OVERHEAD_IO_INITIALIZE 5 +#define CALLING_OVERHEAD_IO_OPEN 5 +#define CALLING_OVERHEAD_IO_CLOSE 5 +#define CALLING_OVERHEAD_IO_READ 5 +#define CALLING_OVERHEAD_IO_WRITE 5 +#define CALLING_OVERHEAD_IO_CONTROL 5 +#define CALLING_OVERHEAD_FATAL_ERROR_OCCURRED 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CREATE 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_IDENT 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_DELETE 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_CANCEL 4 +#define CALLING_OVERHEAD_RATE_MONOTONIC_PERIOD 4 +#define CALLING_OVERHEAD_MULTIPROCESSING_ANNOUNCE 3 + +#ifdef __cplusplus +} +#endif + +#endif +/* end of include file */ diff --git a/c/src/lib/libbsp/sh/gensh1/startup/Makefile.in b/c/src/lib/libbsp/sh/gensh1/startup/Makefile.in new file mode 100644 index 0000000000..d162cbdc92 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/startup/Makefile.in @@ -0,0 +1,59 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH=@srcdir@:@srcdir@/../../shared:@srcdir@/../../../shared +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/startup.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=bspstart bspclean sbrk setvec main +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES= +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +SRCS=linkcmds $(C_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + $(INSTALL) $(srcdir)/linkcmds ${PROJECT_RELEASE}/lib + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile diff --git a/c/src/lib/libbsp/sh/gensh1/startup/bspclean.c b/c/src/lib/libbsp/sh/gensh1/startup/bspclean.c new file mode 100644 index 0000000000..27b767f373 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/startup/bspclean.c @@ -0,0 +1,40 @@ +/* bsp_cleanup() + * + * This routine normally is part of start.s and usually returns + * control to a monitor. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * You should have received a copy of the GNU General Public License + * along with this program; If not, write to the Free Software Foundation, + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +void bsp_cleanup( void ) +{ +} diff --git a/c/src/lib/libbsp/sh/gensh1/startup/bspstart.c b/c/src/lib/libbsp/sh/gensh1/startup/bspstart.c new file mode 100644 index 0000000000..1a3cc2737f --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/startup/bspstart.c @@ -0,0 +1,278 @@ +/* bsp_start() + * + * This routine starts the application. It includes application, + * board, and monitor specific initialization and configuration. + * The generic CPU dependent initialization has been performed + * before this routine is invoked. + * + * INPUT: NONE + * + * OUTPUT: NONE + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include + +#include + +#include +#include + +#ifdef STACK_CHECKER_ON +#include +#endif + +/* + * The original table from the application and our copy of it with + * some changes. + */ + +extern rtems_configuration_table Configuration; + +rtems_configuration_table BSP_Configuration; + +rtems_cpu_table Cpu_table; + +char *rtems_progname; + +/* Initialize whatever libc we are using + * called from postdriver hook + */ + + +void bsp_libc_init() +{ + /* + * The last parameter to RTEMS_Malloc_Initialize is the "chunk" + * size which a multiple of will be requested on each sbrk() + * call by malloc(). A value of 0 indicates that sbrk() should + * not be called to extend the heap. + */ + + RTEMS_Malloc_Initialize(&HeapStart, sizeof(unsigned32) * (&HeapEnd - &HeapStart), 0); + + /* + * Init the RTEMS libio facility to provide UNIX-like system + * calls for use by newlib (ie: provide __rtems_open, __rtems_close, etc) + * Uses malloc() to get area for the iops, so must be after malloc init + */ + + rtems_libio_init(); + + /* + * Set up for the libc handling. + */ + + if (BSP_Configuration.ticks_per_timeslice > 0) + libc_init(1); /* reentrant if possible */ + else + libc_init(0); /* non-reentrant */ +} + +/* + * Function: bsp_pretasking_hook + * + * Description: + * BSP pretasking hook. Called just before drivers are initialized. + * Used to setup libc and install any BSP extensions. + * + * NOTES: + * Must not use libc (to do io) from here, since drivers are + * not yet initialized. + * + */ + +void +bsp_pretasking_hook(void) +{ + bsp_libc_init(); + +#ifdef STACK_CHECKER_ON + /* + * Initialize the stack bounds checker + * We can either turn it on here or from the app. + */ + + Stack_check_Initialize(); +#endif + +#ifdef RTEMS_DEBUG + rtems_debug_enable( RTEMS_DEBUG_ALL_MASK ); +#endif +} + + +/* + * After drivers are setup, register some "filenames" + * and open stdin, stdout, stderr files + * + * Newlib will automatically associate the files with these + * (it hardcodes the numbers) + */ + +void +bsp_postdriver_hook(void) +{ + int stdin_fd, stdout_fd, stderr_fd; + int error_code; + + error_code = 'S' << 24 | 'T' << 16; + + if ((stdin_fd = __rtems_open("/dev/console", O_RDONLY, 0)) == -1) + rtems_fatal_error_occurred( error_code | 'D' << 8 | '0' ); + + if ((stdout_fd = __rtems_open("/dev/console", O_WRONLY, 0)) == -1) + rtems_fatal_error_occurred( error_code | 'D' << 8 | '1' ); + + if ((stderr_fd = __rtems_open("/dev/console", O_WRONLY, 0)) == -1) + rtems_fatal_error_occurred( error_code | 'D' << 8 | '2' ); + + if ((stdin_fd != 0) || (stdout_fd != 1) || (stderr_fd != 2)) + rtems_fatal_error_occurred( error_code | 'I' << 8 | 'O' ); +} + +int bsp_start( + int argc, + char **argv, + char **environp +) +{ + /* + For real boards you need to setup the hardware + and need to copy the vector table from rom to ram. + + Depending on the board this can ether be done from inside the rom + startup code, rtems startup code or here. + */ + + if ((argc > 0) && argv && argv[0]) + rtems_progname = argv[0]; + else + rtems_progname = "RTEMS"; + + /* + * Allocate the memory for the RTEMS Work Space. This can come from + * a variety of places: hard coded address, malloc'ed from outside + * RTEMS world (e.g. simulator or primitive memory manager), or (as + * typically done by stock BSPs) by subtracting the required amount + * of work space from the last physical address on the CPU board. + */ + + /* + * Copy the Configuration Table .. so we can change it + */ + + BSP_Configuration = Configuration; + + /* + * Add 1 region for the RTEMS Malloc + */ + + BSP_Configuration.RTEMS_api_configuration->maximum_regions++; + + /* + * Add 1 extension for newlib libc + */ + +#ifdef RTEMS_NEWLIB + BSP_Configuration.maximum_extensions++; +#endif + + /* + * Add 1 extension for newlib libc + */ + +#ifdef RTEMS_NEWLIB + BSP_Configuration.maximum_extensions++; +#endif + +#ifdef STACK_CHECKER_ON + /* + * Add 1 extension for stack checker + */ + + BSP_Configuration.maximum_extensions++; +#endif + + /* + * Need to "allocate" the memory for the RTEMS Workspace and + * tell the RTEMS configuration where it is. This memory is + * not malloc'ed. It is just "pulled from the air". + */ + + BSP_Configuration.work_space_start = (void *) &WorkSpaceStart ; + BSP_Configuration.work_space_size = + (unsigned32) &WorkSpaceEnd - + (unsigned32) &WorkSpaceStart ; + + /* + * initialize the CPU table for this BSP + */ + +#if ( CPU_ALLOCATE_INTERRUPT_STACK == FALSE ) + _CPU_Interrupt_stack_low = &CPU_Interrupt_stack_low ; + _CPU_Interrupt_stack_high = &CPU_Interrupt_stack_high ; + + /* This isn't used anywhere */ + Cpu_table.interrupt_stack_size = + (unsigned32) (&CPU_Interrupt_stack_high) - + (unsigned32) (&CPU_Interrupt_stack_low) ; +#endif + + + Cpu_table.pretasking_hook = bsp_pretasking_hook; /* init libc, etc. */ + + Cpu_table.predriver_hook = NULL; + + Cpu_table.postdriver_hook = bsp_postdriver_hook; + + Cpu_table.idle_task = NULL; /* do not override system IDLE task */ + + Cpu_table.do_zero_of_workspace = TRUE; + +#if ( CPU_ALLOCATE_INTERRUPT_STACK == TRUE ) + Cpu_table.interrupt_stack_size = 4096; +#endif + + Cpu_table.extra_mpci_receive_server_stack = 0; + + /* + * Don't forget the other CPU Table entries. + */ + + /* + * Tell libio how many fd's we want and allow it to tweak config + */ + + rtems_libio_config(&BSP_Configuration, BSP_LIBIO_MAX_FDS); + + /* + * Start RTEMS + */ + + rtems_initialize_executive( &BSP_Configuration, &Cpu_table ); + + bsp_cleanup(); + + return 0; +} diff --git a/c/src/lib/libbsp/sh/gensh1/startup/linkcmds b/c/src/lib/libbsp/sh/gensh1/startup/linkcmds new file mode 100644 index 0000000000..e20551efe7 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/startup/linkcmds @@ -0,0 +1,203 @@ +/* + * This is an adapted linker script from egcs-1.0.1 + * + * Memory layout for an SH 7032 with main memory in area 2 + * This memory layout it very similar to that used for Hitachi's + * EVB with CMON in rom + * + * NOTE: The ram start address may vary, all other start addresses are fixed + * Not suiteable for gdb's simulator + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +OUTPUT_FORMAT("coff-sh") +OUTPUT_ARCH(sh) +ENTRY(_start) + +MEMORY +{ + rom : o = 0x00000000, l = 128k + onchip_peri : o = 0x05000000, l = 512 + ram : o = 0x0A040000, l = 256k + + onchip_ram : o = 0x0f000000, l = 8k +} + +SECTIONS +{ + /* boot vector table */ + .monvects 0x00000000 (NOLOAD): { + _monvects = . ; + } > rom + + /* monitor play area */ + .monram 0x0A040000 (NOLOAD) : + { + _ramstart = .; + } > ram + + /* monitor vector table */ + .vects 0x0A042000 (NOLOAD) : { + _vectab = . ; + *(.vects); + } + + /* Read-only sections, merged into text segment: */ + + . = 0x0a044000 ; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .gnu.version : { *(.gnu.version) } + .gnu.version_d : { *(.gnu.version_d) } + .gnu.version_r : { *(.gnu.version_r) } + .rel.text : + { *(.rel.text) *(.rel.gnu.linkonce.t*) } + .rela.text : + { *(.rela.text) *(.rela.gnu.linkonce.t*) } + .rel.data : + { *(.rel.data) *(.rel.gnu.linkonce.d*) } + .rela.data : + { *(.rela.data) *(.rela.gnu.linkonce.d*) } + .rel.rodata : + { *(.rel.rodata) *(.rel.gnu.linkonce.r*) } + .rela.rodata : + { *(.rela.rodata) *(.rela.gnu.linkonce.r*) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.init : { *(.rel.init) } + .rela.init : { *(.rela.init) } + .rel.fini : { *(.rel.fini) } + .rela.fini : { *(.rela.fini) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } =0 + .plt : { *(.plt) } + .text . : + { + *(.text) + *(.stub) + /* .gnu.warning sections are handled specially by elf32.em. */ + *(.gnu.warning) + *(.gnu.linkonce.t*) + } > ram + _etext = .; + PROVIDE (etext = .); + .fini . : { *(.fini) } =0 + .rodata . : { *(.rodata) *(.gnu.linkonce.r*) } + .rodata1 . : { *(.rodata1) } + /* Adjust the address for the data segment. We want to adjust up to + the same address within the page on the next page up. */ + . = ALIGN(128) + (. & (128 - 1)); + .data . : + { + *(.data) + *(.gnu.linkonce.d*) + CONSTRUCTORS + } > ram + .data1 . : { *(.data1) } + .ctors . : + { + ___ctors = .; + *(.ctors) + ___ctors_end = .; + } + .dtors . : + { + ___dtors = .; + *(.dtors) + ___dtors_end = .; + } + .got . : { *(.got.plt) *(.got) } + .dynamic . : { *(.dynamic) } + /* We want the small data sections together, so single-instruction offsets + can access them all, and initialized data all before uninitialized, so + we can shorten the on-disk segment size. */ + .sdata . : { *(.sdata) } + _edata = .; + PROVIDE (edata = .); + __bss_start = .; + .sbss . : { *(.sbss) *(.scommon) } + .bss . : + { + *(.dynbss) + *(.bss) + *(COMMON) + } > ram + _end = . ; + PROVIDE (end = .); + + _HeapStart = . ; + . = . + 1024 * 20 ; + PROVIDE( _HeapEnd = . ); + + _WorkSpaceStart = . ; + . = 0x0a080000 ; + PROVIDE(_WorkSpaceEnd = .); + + _CPU_Interrupt_stack_low = 0x0f000000 ; + _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ; + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + Symbols in the DWARF debugging sections are relative to the beginning + of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } + + .stack 0x0f001ff0 : { _stack = .; *(.stack) } > onchip_ram + /* These must appear regardless of . */ +} diff --git a/c/src/lib/libbsp/sh/gensh1/times b/c/src/lib/libbsp/sh/gensh1/times new file mode 100644 index 0000000000..8820913932 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/times @@ -0,0 +1,195 @@ +# +# Timing Test Suite Results for the generic sh1 +# +# NOTE: Due to memory shortage the timing test suite could not yet be run. +# +# Author: Ralf Corsepius (corsepiu@faw.uni-ulm.de) +# +# $Id$ +# + +Board: Diesner OktagonSH/AMOS-2.1 +CPU: Hitachi SH 7032 +Clock Speed: 20MHz +Memory Configuration: 8k on-chip ram, 256k external RAM in Area 4 +Wait States: + +Times Reported in: cycles, microseconds, etc +Timer Source: Count Down Timer, on-CPU cycle counter, etc + +Column A: +Column B: + +# DESCRIPTION A B +== ================================================================= ==== ==== + 1 rtems_semaphore_create X + rtems_semaphore_delete X + rtems_semaphore_obtain: available X + rtems_semaphore_obtain: not available -- NO_WAIT X + rtems_semaphore_release: no waiting tasks X + + 2 rtems_semaphore_obtain: not available -- caller blocks X + + 3 rtems_semaphore_release: task readied -- preempts caller X + + 4 rtems_task_restart: blocked task -- preempts caller X + rtems_task_restart: ready task -- preempts caller X + rtems_semaphore_release: task readied -- returns to caller X + rtems_task_create X + rtems_task_start X + rtems_task_restart: suspended task -- returns to caller X + rtems_task_delete: suspended task X + rtems_task_restart: ready task -- returns to caller X + rtems_task_restart: blocked task -- returns to caller X + rtems_task_delete: blocked task X + + 5 rtems_task_suspend: calling task X + rtems_task_resume: task readied -- preempts caller X + + 6 rtems_task_restart: calling task X + rtems_task_suspend: returns to caller X + rtems_task_resume: task readied -- returns to caller X + rtems_task_delete: ready task X + + 7 rtems_task_restart: suspended task -- preempts caller X + + 8 rtems_task_set_priority: obtain current priority X + rtems_task_set_priority: returns to caller X + rtems_task_mode: obtain current mode X + rtems_task_mode: no reschedule X + rtems_task_mode: reschedule -- returns to caller X + rtems_task_mode: reschedule -- preempts caller X + rtems_task_set_note X + rtems_task_get_note X + rtems_clock_set X + rtems_clock_get X + + 9 rtems_message_queue_create X + rtems_message_queue_send: no waiting tasks X + rtems_message_queue_urgent: no waiting tasks X + rtems_message_queue_receive: available X + rtems_message_queue_flush: no messages flushed X + rtems_message_queue_flush: messages flushed X + rtems_message_queue_delete X + +10 rtems_message_queue_receive: not available -- NO_WAIT X + rtems_message_queue_receive: not available -- caller blocks X + +11 rtems_message_queue_send: task readied -- preempts caller X + +12 rtems_message_queue_send: task readied -- returns to caller X + +13 rtems_message_queue_urgent: task readied -- preempts caller X + +14 rtems_message_queue_urgent: task readied -- returns to caller X + +15 rtems_event_receive: obtain current events X + rtems_event_receive: not available -- NO_WAIT X + rtems_event_receive: not available -- caller blocks X + rtems_event_send: no task readied X + rtems_event_receive: available X + rtems_event_send: task readied -- returns to caller X + +16 rtems_event_send: task readied -- preempts caller X + +17 rtems_task_set_priority: preempts caller X + +18 rtems_task_delete: calling task X + +19 rtems_signal_catch X + rtems_signal_send: returns to caller X + rtems_signal_send: signal to self X + exit ASR overhead: returns to calling task X + exit ASR overhead: returns to preempting task X + +20 rtems_partition_create X + rtems_region_create X + rtems_partition_get_buffer: available X + rtems_partition_get_buffer: not available X + rtems_partition_return_buffer X + rtems_partition_delete X + rtems_region_get_segment: available X + rtems_region_get_segment: not available -- NO_WAIT X + rtems_region_return_segment: no waiting tasks X + rtems_region_get_segment: not available -- caller blocks X + rtems_region_return_segment: task readied -- preempts caller X + rtems_region_return_segment: task readied -- returns to caller X + rtems_region_delete X + rtems_io_initialize X + rtems_io_open X + rtems_io_close X + rtems_io_read X + rtems_io_write X + rtems_io_control X + +21 rtems_task_ident X + rtems_message_queue_ident X + rtems_semaphore_ident X + rtems_partition_ident X + rtems_region_ident X + rtems_port_ident X + rtems_timer_ident X + rtems_rate_monotonic_ident X + +22 rtems_message_queue_broadcast: task readied -- returns to caller X + rtems_message_queue_broadcast: no waiting tasks X + rtems_message_queue_broadcast: task readied -- preempts caller X + +23 rtems_timer_create X + rtems_timer_fire_after: inactive X + rtems_timer_fire_after: active X + rtems_timer_cancel: active X + rtems_timer_cancel: inactive X + rtems_timer_reset: inactive X + rtems_timer_reset: active X + rtems_timer_fire_when: inactive X + rtems_timer_fire_when: active X + rtems_timer_delete: active X + rtems_timer_delete: inactive X + rtems_task_wake_when X + +24 rtems_task_wake_after: yield -- returns to caller X + rtems_task_wake_after: yields -- preempts caller X + +25 rtems_clock_tick X + +26 _ISR_Disable X + _ISR_Flash X + _ISR_Enable X + _Thread_Disable_dispatch X + _Thread_Enable_dispatch X + _Thread_Set_state X + _Thread_Disptach (NO FP) X + context switch: no floating point contexts X + context switch: self X + context switch: to another task X + context switch: restore 1st FP task X + fp context switch: save idle, restore idle X + fp context switch: save idle, restore initialized X + fp context switch: save initialized, restore initialized X + _Thread_Resume X + _Thread_Unblock X + _Thread_Ready X + _Thread_Get X + _Semaphore_Get X + _Thread_Get: invalid id X + +27 interrupt entry overhead: returns to interrupted task X + interrupt exit overhead: returns to interrupted task X + interrupt entry overhead: returns to nested interrupt X + interrupt exit overhead: returns to nested interrupt X + interrupt entry overhead: returns to preempting task X + interrupt exit overhead: returns to preempting task X + +28 rtems_port_create X + rtems_port_external_to_internal X + rtems_port_internal_to_external X + rtems_port_delete X + +29 rtems_rate_monotonic_create X + rtems_rate_monotonic_period: initiate period -- returns to caller X + rtems_rate_monotonic_period: obtain status X + rtems_rate_monotonic_cancel X + rtems_rate_monotonic_delete: inactive X + rtems_rate_monotonic_delete: active X + rtems_rate_monotonic_period: conclude periods -- caller blocks X diff --git a/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in b/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in new file mode 100644 index 0000000000..ef0fa74558 --- /dev/null +++ b/c/src/lib/libbsp/sh/gensh1/wrapup/Makefile.in @@ -0,0 +1,64 @@ +# +# $Id $ +# +# $Id$ +# +# build and install libbsp +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH=@srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +BSP_PIECES=startup +GENERIC_PIECES= + +# pieces to pick up out of libcpu/sh +CPU_PIECES=\ + sh7032/null \ + sh7032/clock \ + sh7032/console \ + sh7032/timer + +# bummer; have to use $foreach since % pattern subst rules only replace 1x +OBJS=$(foreach piece, $(BSP_PIECES), ../$(piece)/$(ARCH)/$(piece).rel) \ + $(foreach piece, $(CPU_PIECES), \ + ../../../../libcpu/$(RTEMS_CPU)/$(piece)/$(ARCH)/$(notdir $(piece)).rel) \ + $(foreach piece, $(GENERIC_PIECES), ../../../../$(piece)/$(ARCH)/$(piece).rel) + +LIB=$(ARCH)/libbsp.a + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/lib.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +$(LIB): ${OBJS} + $(make-library) + +all: ${ARCH} $(SRCS) $(LIB) + $(INSTALL_VARIANT) -m 644 $(LIB) ${PROJECT_RELEASE}/lib + +install: all diff --git a/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c new file mode 100644 index 0000000000..42764f6eb1 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7032/score/cpu_asm.c @@ -0,0 +1,311 @@ +/* + * This file contains the basic algorithms for all assembly code used + * in an specific CPU port of RTEMS. These algorithms must be implemented + * in assembly language + * + * NOTE: This port uses a C file with inline assembler instructions + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + */ + +/* + * This is supposed to be an assembly file. This means that system.h + * and cpu.h should not be included in a "real" cpu_asm file. An + * implementation in assembly should include "cpu_asm.h" + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* from cpu_isps.c */ +extern proc_ptr _Hardware_isr_Table[]; + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + unsigned long *_old_stack_ptr; +#endif + +register unsigned long *stack_ptr asm("r15"); + +/* + * sh_set_irq_priority + * + * this function sets the interrupt level of the specified interrupt + * + * parameters: + * - irq : interrupt number + * - prio: priority to set for this interrupt number + * + * returns: 0 if ok + * -1 on error + */ + +unsigned int sh_set_irq_priority( + unsigned int irq, + unsigned int prio ) +{ + unsigned32 shiftcount; + unsigned32 prioreg; + unsigned16 temp16; + unsigned32 level; + + /* + * first check for valid interrupt + */ + if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp)) + return -1; + /* + * check for valid irq priority + */ + if( prio > 15 ) + return -1; + + /* + * look up appropriate interrupt priority register + */ + if( irq > 71) + { + irq = irq - 72; + shiftcount = 12 - ((irq & ~0x03) % 16); + + switch( irq / 16) + { + case 0: { prioreg = INTC_IPRC; break;} + case 1: { prioreg = INTC_IPRD; break;} + case 2: { prioreg = INTC_IPRE; break;} + default: return -1; + } + } + else + { + shiftcount = 12 - 4 * ( irq % 4); + if( irq > 67) + prioreg = INTC_IPRB; + else + prioreg = INTC_IPRA; + } + + /* + * Set the interrupt priority register + */ + _CPU_ISR_Disable( level ); + + temp16 = read16( prioreg); + temp16 &= ~( 15 << shiftcount); + temp16 |= prio << shiftcount; + write16( temp16, prioreg); + + _CPU_ISR_Enable( level ); + + return 0; +} + +/* + * _CPU_Context_save_fp_context + * + * This routine is responsible for saving the FP context + * at *fp_context_ptr. If the point to load the FP context + * from is changed then the pointer is modified by this routine. + * + * Sometimes a macro implementation of this is in cpu.h which dereferences + * the ** and a similarly named routine in this file is passed something + * like a (Context_Control_fp *). The general rule on making this decision + * is to avoid writing assembly language. + */ + +void _CPU_Context_save_fp( + void **fp_context_ptr +) +{ +} + +/* + * _CPU_Context_restore_fp_context + * + * This routine is responsible for restoring the FP context + * at *fp_context_ptr. If the point to load the FP context + * from is changed then the pointer is modified by this routine. + * + * Sometimes a macro implementation of this is in cpu.h which dereferences + * the ** and a similarly named routine in this file is passed something + * like a (Context_Control_fp *). The general rule on making this decision + * is to avoid writing assembly language. + */ + +void _CPU_Context_restore_fp( + void **fp_context_ptr +) +{ +} + +/* _CPU_Context_switch + * + * This routine performs a normal non-FP context switch. + */ + +/* within __CPU_Context_switch: + * _CPU_Context_switch + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: It should be safe not to store r4, r5 + * + * NOTE: It is doubtful if r0 is really needed to be stored + * + * NOTE: gbr is added, but should not be necessary, as it is + * only used globally in this port. + */ + +/* + * FIXME: This is an ugly hack, but we wanted to avoid recalculating + * the offset each time Context_Control is changed + */ +void __CPU_Context_switch( + Context_Control *run, /* r4 */ + Context_Control *heir /* r5 */ +) +{ + +asm volatile(" + .global __CPU_Context_switch +__CPU_Context_switch: + + add %0,r4 + + stc.l sr,@-r4 + stc.l gbr,@-r4 + mov.l r0,@-r4 + mov.l r1,@-r4 + mov.l r2,@-r4 + mov.l r3,@-r4 + + mov.l r6,@-r4 + mov.l r7,@-r4 + mov.l r8,@-r4 + mov.l r9,@-r4 + mov.l r10,@-r4 + mov.l r11,@-r4 + mov.l r12,@-r4 + mov.l r13,@-r4 + mov.l r14,@-r4 + sts.l pr,@-r4 + sts.l mach,@-r4 + sts.l macl,@-r4 + mov.l r15,@-r4 + + mov r5, r4" + :: "I" (sizeof(Context_Control)) + ); + + asm volatile(" + .global __CPU_Context_restore +__CPU_Context_restore: + mov.l @r4+,r15 + lds.l @r4+,macl + lds.l @r4+,mach + lds.l @r4+,pr + mov.l @r4+,r14 + mov.l @r4+,r13 + mov.l @r4+,r12 + mov.l @r4+,r11 + mov.l @r4+,r10 + mov.l @r4+,r9 + mov.l @r4+,r8 + mov.l @r4+,r7 + mov.l @r4+,r6 + + mov.l @r4+,r3 + mov.l @r4+,r2 + mov.l @r4+,r1 + mov.l @r4+,r0 + ldc.l @r4+,gbr + ldc.l @r4+,sr + + rts + nop" ); +} + +/* + * This routine provides the RTEMS interrupt management. + */ + +void __ISR_Handler( unsigned32 vector) +{ + register unsigned32 level; + + _CPU_ISR_Disable( level ); + + _Thread_Dispatch_disable_level++; + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + if( _ISR_Nest_level == 0 ) + { + /* Install irq stack */ + _old_stack_ptr = stack_ptr; + stack_ptr = _CPU_Interrupt_stack_high; + } + +#endif + + _ISR_Nest_level++; + + _CPU_ISR_Enable( level ); + + /* call isp */ + if( _ISR_Vector_table[ vector]) + (*_ISR_Vector_table[ vector ])( vector ); + + _CPU_ISR_Disable( level ); + + _ISR_Nest_level--; + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + + if( _ISR_Nest_level == 0 ) + /* restore old stack pointer */ + stack_ptr = _old_stack_ptr; +#endif + + _Thread_Dispatch_disable_level--; + + _CPU_ISR_Enable( level ); + + if ( _Thread_Dispatch_disable_level == 0 ) + { + if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing)) + { + _ISR_Signals_to_thread_executing = FALSE; + _Thread_Dispatch(); + } + } +} diff --git a/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c b/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c new file mode 100644 index 0000000000..1643785810 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7032/score/ispsh7032.c @@ -0,0 +1,252 @@ +/* + * This file contains the isp frames for the user interrupts. + * From these procedures __ISR_Handler is called with the vector number + * as argument. + * + * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in + * some releases of gcc doesn't properly handle #pragma interrupt, if a + * file contains both isrs and normal functions. + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include +#include + +/* + * This is a exception vector table + * + * It has the same structure like the actual vector table (vectab) + */ +proc_ptr _Hardware_isr_Table[256]={ +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, +_nmi_isp, _usb_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, +/* trapa 0 -31 */ +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, +/* irq 64 ... */ +_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp, +_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp, +_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp, +_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp, +_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp, +_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp, +_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp, +_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp, +_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp, +_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, +_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp, +_prt_isp, _adu_isp, _dummy_isp, _dummy_isp, +_wdt_isp, +/* 113 */ _dref_isp +}; + +#define Str(a)#a + +/* + * Some versions of gcc and all version of egcs at least until egcs-1.0.2 + * are not able to handle #praga interrupt correctly if more than 1 isr is + * contained in a file and when optimizing. + * We try to work around this problem by using the macro below. + */ +#define isp( name, number, func)\ +asm (".global _"Str(name)"\n\t" \ + "_"Str(name)": \n\t" \ + " mov.l r0,@-r15 \n\t" \ + " mov.l r1,@-r15 \n\t" \ + " mov.l r2,@-r15 \n\t" \ + " mov.l r3,@-r15 \n\t" \ + " mov.l r4,@-r15 \n\t" \ + " mov.l r5,@-r15 \n\t" \ + " mov.l r6,@-r15 \n\t" \ + " mov.l r7,@-r15 \n\t" \ + " mov.l r14,@-r15 \n\t" \ + " sts.l pr,@-r15 \n\t" \ + " sts.l mach,@-r15 \n\t" \ + " sts.l macl,@-r15 \n\t" \ + " mov r15,r14 \n\t" \ + " mov.l "Str(name)"_k, r1\n\t" \ + " jsr @r1 \n\t" \ + " mov #"Str(number)", r4\n\t" \ + " mov r14,r15 \n\t" \ + " lds.l @r15+,macl \n\t" \ + " lds.l @r15+,mach \n\t" \ + " lds.l @r15+,pr \n\t" \ + " mov.l @r15+,r14 \n\t" \ + " mov.l @r15+,r7 \n\t" \ + " mov.l @r15+,r6 \n\t" \ + " mov.l @r15+,r5 \n\t" \ + " mov.l @r15+,r4 \n\t" \ + " mov.l @r15+,r3 \n\t" \ + " mov.l @r15+,r2 \n\t" \ + " mov.l @r15+,r1 \n\t" \ + " mov.l @r15+,r0 \n\t" \ + " rte \n\t" \ + " nop \n\t" \ + " .align 2 \n\t" \ + #name"_k: \n\t" \ + ".long "Str(func)); + +/************************************************ + * Dummy interrupt service procedure for + * interrupts being not allowed --> Trap 34 + ************************************************/ +asm(" .section .text +.global __dummy_isp +__dummy_isp: + mov.l r14,@-r15 + mov r15, r14 + trapa #34 + mov.l @r15+,r14 + rte + nop"); + +/***************************** + * Non maskable interrupt + *****************************/ +isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler); + +/***************************** + * User break controller + *****************************/ +isp( _usb_isp, USB_ISP_V, ___ISR_Handler); + +/***************************** + * External interrupts 0-7 + *****************************/ +isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler); +isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler); +isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler); +isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler); +isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler); +isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler); +isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler); +isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler); + +/***************************** + * DMA - controller + *****************************/ +isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler); +isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler); +isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler); +isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler); + + +/***************************** + * Interrupt timer unit + *****************************/ + +/***************************** + * Timer 0 + *****************************/ +isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler); +isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler); +isp( _ovi0_isp, OVI0_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 1 + *****************************/ +isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler); +isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler); +isp( _ovi1_isp, OVI1_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 2 + *****************************/ +isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler); +isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler); +isp( _ovi2_isp, OVI2_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 3 + *****************************/ +isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler); +isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler); +isp( _ovi3_isp, OVI3_ISP_V, ___ISR_Handler); + +/***************************** + * Timer 4 + *****************************/ +isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler); +isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler); +isp( _ovi4_isp, OVI4_ISP_V, ___ISR_Handler); + + +/***************************** + * Serial interfaces + *****************************/ + +/***************************** + * Serial interface 0 + *****************************/ +isp( _eri0_isp, ERI0_ISP_V, ___ISR_Handler); +isp( _rxi0_isp, RXI0_ISP_V, ___ISR_Handler); +isp( _txi0_isp, TXI0_ISP_V, ___ISR_Handler); +isp( _tei0_isp, TEI0_ISP_V, ___ISR_Handler); + +/***************************** + * Serial interface 1 + *****************************/ +isp( _eri1_isp, ERI1_ISP_V, ___ISR_Handler); +isp( _rxi1_isp, RXI1_ISP_V, ___ISR_Handler); +isp( _txi1_isp, TXI1_ISP_V, ___ISR_Handler); +isp( _tei1_isp, TEI1_ISP_V, ___ISR_Handler); + + +/***************************** + * Parity control unit of + * the bus state controller + *****************************/ +isp( _prt_isp, PRT_ISP_V, ___ISR_Handler); + + +/****************************** + * Analog digital converter + * ADC + ******************************/ +isp( _adu_isp, ADU_ISP_V, ___ISR_Handler); + + +/****************************** + * Watchdog timer + ******************************/ +isp( _wdt_isp, WDT_ISP_V, ___ISR_Handler); + + +/****************************** + * DRAM refresh control unit + * of bus state controller + ******************************/ +isp( _dref_isp, DREF_ISP_V, ___ISR_Handler); diff --git a/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c new file mode 100644 index 0000000000..42764f6eb1 --- /dev/null +++ b/c/src/lib/libcpu/sh/sh7045/score/cpu_asm.c @@ -0,0 +1,311 @@ +/* + * This file contains the basic algorithms for all assembly code used + * in an specific CPU port of RTEMS. These algorithms must be implemented + * in assembly language + * + * NOTE: This port uses a C file with inline assembler instructions + * + * Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and + * Bernd Becker (becker@faw.uni-ulm.de) + * + * COPYRIGHT (c) 1997-1998, FAW Ulm, Germany + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + * + * COPYRIGHT (c) 1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + * + * This material may be reproduced by or for the U.S. Government pursuant + * to the copyright license under the clause at DFARS 252.227-7013. This + * notice must appear in all copies of this file and its derivatives. + * + */ + +/* + * This is supposed to be an assembly file. This means that system.h + * and cpu.h should not be included in a "real" cpu_asm file. An + * implementation in assembly should include "cpu_asm.h" + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* from cpu_isps.c */ +extern proc_ptr _Hardware_isr_Table[]; + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + unsigned long *_old_stack_ptr; +#endif + +register unsigned long *stack_ptr asm("r15"); + +/* + * sh_set_irq_priority + * + * this function sets the interrupt level of the specified interrupt + * + * parameters: + * - irq : interrupt number + * - prio: priority to set for this interrupt number + * + * returns: 0 if ok + * -1 on error + */ + +unsigned int sh_set_irq_priority( + unsigned int irq, + unsigned int prio ) +{ + unsigned32 shiftcount; + unsigned32 prioreg; + unsigned16 temp16; + unsigned32 level; + + /* + * first check for valid interrupt + */ + if(( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp)) + return -1; + /* + * check for valid irq priority + */ + if( prio > 15 ) + return -1; + + /* + * look up appropriate interrupt priority register + */ + if( irq > 71) + { + irq = irq - 72; + shiftcount = 12 - ((irq & ~0x03) % 16); + + switch( irq / 16) + { + case 0: { prioreg = INTC_IPRC; break;} + case 1: { prioreg = INTC_IPRD; break;} + case 2: { prioreg = INTC_IPRE; break;} + default: return -1; + } + } + else + { + shiftcount = 12 - 4 * ( irq % 4); + if( irq > 67) + prioreg = INTC_IPRB; + else + prioreg = INTC_IPRA; + } + + /* + * Set the interrupt priority register + */ + _CPU_ISR_Disable( level ); + + temp16 = read16( prioreg); + temp16 &= ~( 15 << shiftcount); + temp16 |= prio << shiftcount; + write16( temp16, prioreg); + + _CPU_ISR_Enable( level ); + + return 0; +} + +/* + * _CPU_Context_save_fp_context + * + * This routine is responsible for saving the FP context + * at *fp_context_ptr. If the point to load the FP context + * from is changed then the pointer is modified by this routine. + * + * Sometimes a macro implementation of this is in cpu.h which dereferences + * the ** and a similarly named routine in this file is passed something + * like a (Context_Control_fp *). The general rule on making this decision + * is to avoid writing assembly language. + */ + +void _CPU_Context_save_fp( + void **fp_context_ptr +) +{ +} + +/* + * _CPU_Context_restore_fp_context + * + * This routine is responsible for restoring the FP context + * at *fp_context_ptr. If the point to load the FP context + * from is changed then the pointer is modified by this routine. + * + * Sometimes a macro implementation of this is in cpu.h which dereferences + * the ** and a similarly named routine in this file is passed something + * like a (Context_Control_fp *). The general rule on making this decision + * is to avoid writing assembly language. + */ + +void _CPU_Context_restore_fp( + void **fp_context_ptr +) +{ +} + +/* _CPU_Context_switch + * + * This routine performs a normal non-FP context switch. + */ + +/* within __CPU_Context_switch: + * _CPU_Context_switch + * _CPU_Context_restore + * + * This routine is generally used only to restart self in an + * efficient manner. It may simply be a label in _CPU_Context_switch. + * + * NOTE: It should be safe not to store r4, r5 + * + * NOTE: It is doubtful if r0 is really needed to be stored + * + * NOTE: gbr is added, but should not be necessary, as it is + * only used globally in this port. + */ + +/* + * FIXME: This is an ugly hack, but we wanted to avoid recalculating + * the offset each time Context_Control is changed + */ +void __CPU_Context_switch( + Context_Control *run, /* r4 */ + Context_Control *heir /* r5 */ +) +{ + +asm volatile(" + .global __CPU_Context_switch +__CPU_Context_switch: + + add %0,r4 + + stc.l sr,@-r4 + stc.l gbr,@-r4 + mov.l r0,@-r4 + mov.l r1,@-r4 + mov.l r2,@-r4 + mov.l r3,@-r4 + + mov.l r6,@-r4 + mov.l r7,@-r4 + mov.l r8,@-r4 + mov.l r9,@-r4 + mov.l r10,@-r4 + mov.l r11,@-r4 + mov.l r12,@-r4 + mov.l r13,@-r4 + mov.l r14,@-r4 + sts.l pr,@-r4 + sts.l mach,@-r4 + sts.l macl,@-r4 + mov.l r15,@-r4 + + mov r5, r4" + :: "I" (sizeof(Context_Control)) + ); + + asm volatile(" + .global __CPU_Context_restore +__CPU_Context_restore: + mov.l @r4+,r15 + lds.l @r4+,macl + lds.l @r4+,mach + lds.l @r4+,pr + mov.l @r4+,r14 + mov.l @r4+,r13 + mov.l @r4+,r12 + mov.l @r4+,r11 + mov.l @r4+,r10 + mov.l @r4+,r9 + mov.l @r4+,r8 + mov.l @r4+,r7 + mov.l @r4+,r6 + + mov.l @r4+,r3 + mov.l @r4+,r2 + mov.l @r4+,r1 + mov.l @r4+,r0 + ldc.l @r4+,gbr + ldc.l @r4+,sr + + rts + nop" ); +} + +/* + * This routine provides the RTEMS interrupt management. + */ + +void __ISR_Handler( unsigned32 vector) +{ + register unsigned32 level; + + _CPU_ISR_Disable( level ); + + _Thread_Dispatch_disable_level++; + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + if( _ISR_Nest_level == 0 ) + { + /* Install irq stack */ + _old_stack_ptr = stack_ptr; + stack_ptr = _CPU_Interrupt_stack_high; + } + +#endif + + _ISR_Nest_level++; + + _CPU_ISR_Enable( level ); + + /* call isp */ + if( _ISR_Vector_table[ vector]) + (*_ISR_Vector_table[ vector ])( vector ); + + _CPU_ISR_Disable( level ); + + _ISR_Nest_level--; + +#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE) + + if( _ISR_Nest_level == 0 ) + /* restore old stack pointer */ + stack_ptr = _old_stack_ptr; +#endif + + _Thread_Dispatch_disable_level--; + + _CPU_ISR_Enable( level ); + + if ( _Thread_Dispatch_disable_level == 0 ) + { + if(( _Context_Switch_necessary) || (! _ISR_Signals_to_thread_executing)) + { + _ISR_Signals_to_thread_executing = FALSE; + _Thread_Dispatch(); + } + } +} -- cgit v1.2.3