From 479c86ddbd7324fb0b85aa8a94f7658c85fb8dbe Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 23 Sep 1998 13:22:43 +0000 Subject: Patch from Erik Ivanenko : Please find attached the two files that have been changed relative to 980921 . The changes here are in the handling of the counter-timer used as the basis for the rtems executive clock. For the most part, these are housekeeping changes. The PSCLK frequency change in start.s... was a part of several bug-fixes. The fix improves executive clock and timer accuracy. changes : start.s -- All timers are disabled by the initialization routine -- PSCLK ( used by clock and timers ) frequency changed to 1MHz The clock_initialize routine now assumes that the PSCLK frequency is exactly 1 MHz. ckinit.c Clock_isr -- removed division by 1000. Now use 'static' variable -- clock_intial_isr_value -- to reset Clock_isrs variable. clock_initialize -- moved counter timer initialization here. Values used to configure the timer are totally dependent on BSP_configuration.microseconds_per_tick ( and the PSCLK assumption). Initializes clock_initial_isr_value used by th Clock_isr to reset Clock_isrs. clock_on -- no longer configures the timer, just enables it. Since altering the number of sections in the BSP, I decided to give it a good "once over" . The clock handling is now cleaner. --- c/src/lib/libbsp/i386/i386ex/clock/ckinit.c | 40 +++++++++++++++++++++-------- c/src/lib/libbsp/i386/i386ex/start/start.s | 23 ++++++++--------- 2 files changed, 40 insertions(+), 23 deletions(-) (limited to 'c/src/lib') diff --git a/c/src/lib/libbsp/i386/i386ex/clock/ckinit.c b/c/src/lib/libbsp/i386/i386ex/clock/ckinit.c index 10086f618d..a44477b3b4 100644 --- a/c/src/lib/libbsp/i386/i386ex/clock/ckinit.c +++ b/c/src/lib/libbsp/i386/i386ex/clock/ckinit.c @@ -33,6 +33,7 @@ #include rtems_unsigned32 Clock_isrs; /* ISRs until next tick */ +static rtems_unsigned32 Clock_initial_isr_value; volatile rtems_unsigned32 Clock_driver_ticks; @@ -55,7 +56,7 @@ void Clock_isr() Clock_driver_ticks += 1; if ( Clock_isrs == 1 ) { rtems_clock_tick(); - Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; + Clock_isrs = Clock_initial_isr_value; /* BSP_Configuration.microseconds_per_tick / 1000;*/ } else Clock_isrs -= 1; @@ -63,19 +64,12 @@ void Clock_isr() void ClockOff(const rtems_irq_connect_data* unused) { - /* should do something here */; - outport_byte ( TMRCFG , 0x80 ); + outport_byte ( TMRCFG , 0x80 ); /* disable the counter timer */ } void ClockOn(const rtems_irq_connect_data* unused) { - outport_byte ( TMRCFG , 0x80 ); - - outport_byte ( TMRCON , 0x34 ); - outport_byte ( TMR0 , 0xA8 ); - outport_byte ( TMR0 , 0x04 ); - - outport_byte ( TMRCFG , 0x00 ); + outport_byte ( TMRCFG , 0x00 ); /* enable the counter timer */ } int ClockIsOn(const rtems_irq_connect_data* unused) @@ -95,12 +89,36 @@ rtems_device_driver Clock_initialize( void *pargp ) { + unsigned timer_counter_init_value; + unsigned char clock_lsb, clock_msb; + Clock_driver_ticks = 0; - Clock_isrs = BSP_Configuration.microseconds_per_tick / 1000; + + Clock_isrs = Clock_initial_isr_value = BSP_Configuration.microseconds_per_tick / 1000; /* ticks per clock_isr */ + + /* + * configure the counter timer ( should be based on microsecs/tick ) + * NB. The divisor(Clock_isrs) resolves the is the same number that appears in confdefs.h + * when setting the microseconds_per_tick value. + */ + ClockOff ( &clockIrqData ); + + timer_counter_init_value = BSP_Configuration.microseconds_per_tick / Clock_isrs; + clock_lsb = (unsigned char)timer_counter_init_value; + clock_msb = timer_counter_init_value >> 8; + + printk("timer_counter_init_value = 0x%x, lsb = 0x%x, msb = 0x%x, Clock_isrs = %d\n",timer_counter_init_value, + clock_lsb, clock_msb, Clock_isrs); + + outport_byte ( TMRCON , 0x34 ); + outport_byte ( TMR0 , clock_lsb ); /* load LSB first */ + outport_byte ( TMR0 , clock_msb ); /* then MSB */ + if (!pc386_install_rtems_irq_handler (&clockIrqData)) { printk("Unable to initialize system clock\n"); rtems_fatal_error_occurred(1); } + /* * make major/minor avail to others such as shared memory driver */ diff --git a/c/src/lib/libbsp/i386/i386ex/start/start.s b/c/src/lib/libbsp/i386/i386ex/start/start.s index f24f45abd6..e8cbc71b9c 100644 --- a/c/src/lib/libbsp/i386/i386ex/start/start.s +++ b/c/src/lib/libbsp/i386/i386ex/start/start.s @@ -44,6 +44,8 @@ changes: * #define NEXT_GAS */ +#define NEXT_GAS + EXTERN (boot_card) /* exits to bspstart */ EXTERN (stack_start) /* defined in startup/linkcmds */ EXTERN (Clock_exit) @@ -149,14 +151,13 @@ SYM(InitRCU): /* * Initialize clock and power mgmt unit for: * Clock Frequency = 50 Mhz - * Prescaled clock output = 1.19318 Mhz - * ( matches standard PC ) + * Prescaled clock output = 1 Mhz * Normal halt instructions */ SYM(InitClk): SetExRegByte( PWRCON, 0x0 ) - SetExRegWord( CLKPRS, 0x13) + SetExRegWord( CLKPRS, 0x17) # 0x13 for 1.19318 MHz. 0x17 for 1MHz. /************************************************************** * Initialize the Pin Configurations @@ -274,21 +275,19 @@ SYM(InitTimer): # and 2 are set to Vcc SetExRegByte(TMRCON , 0x34 ) # prepare to write counter 0 LSB,MSB - SetExRegByte(TMR0 , 0xA8 ) # LSB = 0B count, followed by MSB - SetExRegByte(TMR0 , 0x04 ) # for INT every 50 msec. MSB = 0xE900 - # for INT every 5 msec. 0x174c - # for INT every 1 msec. 0x04A8 - # was 0xe900 - + SetExRegByte(TMR0 , 0x00 ) # sfa + SetExRegByte(TMR0 , 0x00 ) # sfa + + SetExRegByte(TMRCON , 0x70 ) # mode 0 disables on Gate= Vcc SetExRegByte(TMR1 , 0x00 ) # sfa SetExRegByte(TMR1 , 0x00 ) # sfa SetExRegByte(TMRCON , 0xB0 ) # mode 0 disables on gate =Vcc SetExRegByte(TMR2 , 0x00 ) # - SetExRegByte(TMR2 , 0x00 ) # - SetExRegByte(TMRCFG , 0x80 ) # Enable timers = 0x00 - + SetExRegByte(TMR2 , 0x00 ) # + + SetExRegByte(TMRCFG , 0x80 ) # Enable = 0x00 /* * Initialize the DMACFG register for: -- cgit v1.2.3