From 7f93f772d805569652938c15d8c7caa30e3da89f Mon Sep 17 00:00:00 2001
From: Joel Sherrill <joel.sherrill@OARcorp.com>
Date: Tue, 16 Nov 1999 13:37:49 +0000
Subject: Committed modifications from ITRON Task and Task Dependendent
 Synchronization Working Group.  Included are tests.

---
 c/src/lib/start/a29k/amd.ah | 517 --------------------------------------------
 1 file changed, 517 deletions(-)
 delete mode 100644 c/src/lib/start/a29k/amd.ah

(limited to 'c/src/lib/start/a29k/amd.ah')

diff --git a/c/src/lib/start/a29k/amd.ah b/c/src/lib/start/a29k/amd.ah
deleted file mode 100644
index 69f34f173e..0000000000
--- a/c/src/lib/start/a29k/amd.ah
+++ /dev/null
@@ -1,517 +0,0 @@
-; /* @(#)amd.ah	1.1 96/05/23 08:56:58, TEI */
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;		 Initialization values for registers after RESET
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;  /* $Id$ */
-;
-;* File information and includes.
-
-        .file   "amd.ah"
-        .ident  "@(#)amd.ah	1.1 96/05/23 08:56:58, TEI"
-
-
-
-;
-;* AMD PROCESSOR SPECIFIC VALUES...
-;
-
-;
-;* Processor revision levels...
-;
-
-; PRL values: 31-28   27-24
-; Am29000	0	x
-; Am29005	1	x
-; Am29050	2	x
-; Am29035	3	x
-; Am29030	4	x
-; Am29200	5	x
-; Am29205	5	1x
-; Am29240	6	0
-; Manx		7	0
-; Cougar	8	0
-
-
-	.equ	AM29000_PRL, 	0x00
-
-	.equ	AM29005_PRL, 	0x10
-
-	.equ	AM29050_PRL, 	0x20
-
-	.equ	AM29035_PRL, 	0x30
-
-	.equ	AM29030_PRL, 	0x40
-
-	.equ	AM29200_PRL, 	0x50
-
-	.equ	AM29205_PRL, 	0x58
-
-	.equ	AM29240_PRL, 	0x60
-
-	.equ	AM29040_PRL, 	0x70
-
-	.equ	MANX_PRL,  	0x70
-
-	.equ	COUGAR_PRL, 	0x80
-
-;
-;* data structures sizes.
-;
-	.equ	CFGINFO_SIZE,	16*4
-
-	.equ	PGMINFO_SIZE,	16*4
-
-	.equ	VARARGS_SPACE,	16*4
-
-	.equ	WINDOWSIZE,	0x80
-;
-;* Am29027 Mode registers
-;
-
-	.equ	Am29027Mode1, 0x0fc00820
-
-	.equ	Am29027Mode2, 0x00001375
-	
-
-
-;* Processor Based Equates and Defines
-
-	.equ	SIG_SYNC,	-1	
-
-	.equ	ENABLE,		(SM)
-
-	.equ	DISABLE,	(ENABLE | DI | DA)
-
-	.equ	DISABLE_FZ,	(FZ | ENABLE | DI | DA)
-
-	.equ	CLR_TRAP,	(FZ | DA)	
-
-	.equ	InitOPS,	(TD | SM | (3<<IMShift) | DI | DA) 
-	
-	.equ	InitCPS,	(TD | SM | (0<<IMShift) | DI | DA) 
-
-	.equ	InitCPS1,	(TD | SM | (0<<IMShift) | DI ) 
-
-	.equ	CPS_TMR,	(SM | (0<<IMShift) | DI)
-
-	.equ	CPS_INT0,	(TD | SM | (0<<IMShift))
-
-	.equ	CPS_TMRINT0,	(SM | (0<<IMShift))
-
-	.equ	InitCFG,	0x0 
-
-	.equ	InitRBP,	(B0|B1|B2|B3|B4|B5)
-
-	.equ	TMC_VALUE,	0xFFFFFF
-
-	.equ	TMR_VALUE,	(IE | TMC_VALUE)
-
-
-
-
-
-
-;* 29205 specific (internal) peripheral initialization constants.
-
-; Current Processor Status (CPS) Register.
-; Old Processor Status Register (OPS).
-
-	.equ	DA,	0x00001
-	.equ	DI,	0x00002
-	.equ	IMShift,0x2
-	.equ	SM,	0x00010
-	.equ	PI,	0x00020
-	.equ	PD,	0x00040
-	.equ	WM,	0x00080
-	.equ	RE, 	0x00100
-	.equ	LK,	0x00200
-	.equ	FZ, 	0x00400
-	.equ	TU,	0x00800
-	.equ	TP,	0x01000
-	.equ	TE,	0x02000
-	.equ	IP,	0x04000
-	.equ	CA,	0x08000
-	.equ	MM,	0x10000
-	.equ	TD,	0x20000
-
-; Configuration Register (CFG)
-
-	.equ	CD,	0x01
-	.equ	CP,	0x02
-	.equ	BO,	0x04
-	.equ	RV, 	0x08
-	.equ	VF,	0x10
-	.equ	DW,	0x20
-	.equ	CO,	0x40
-	.equ	EE,	0x80
-	.equ	IDShift,	8
-	.equ	CFG_ID,	0x100
-	.equ	ILShift,	9
-	.equ	CFG_ILMask,	0x600
-	.equ	DDShift,	11
-	.equ	CFG_DD,	0x800
-	.equ	DLShift,	12
-	.equ	CFG_DLMask,	0x3000
-	.equ	PCEShift, 	14
-	.equ	CFG_PCE,	0x4000
-	.equ	PMBShift, 	16
-	.equ	D16,	0x8000
-	.equ	TBOShift,	23
-	.equ	PRLShift, 24
-
-; Channel Control Register (CHC)
-
-	.equ	CV, 0x1
-	.equ	NN, 0x2
-	.equ	TRShift, 2
-	.equ	TF, 0x400
-	.equ	PER, 0x800
-	.equ	LA, 0x1000
-	.equ	ST, 0x2000
-	.equ	ML, 0x4000
-	.equ	LS, 0x8000
-	.equ 	CRShift, 16
-	.equ	CNTLShift, 24
-	.equ	CEShift, 31
-	.equ	WBERShift, 31
-
-; Register Bank Protect (RBP)
-	.equ	B0, 0x1
-	.equ	B1, 0x2
-	.equ	B2, 0x4
-	.equ	B3, 0x8
-	.equ	B4, 0x10
-	.equ	B5, 0x20
-	.equ	B6, 0x40
-	.equ	B7, 0x80
-	.equ	B8, 0x100
-	.equ	B9, 0x200
-	.equ	B10, 0x400
-	.equ	B11, 0x800
-	.equ	B12, 0x1000
-	.equ	B13, 0x2000
-	.equ	B14, 0x4000
-	.equ	B15, 0x8000
-
-; Timer Counter
-
-	.equ	TCVMask, 0xffffff
-
-; Timer Reload Register
-
-	.equ	IE, 0x1000000
-	.equ	IN, 0x2000000
-	.equ	OV, 0x4000000
-	.equ	TRVMAsk, 0xffffff
-
-; MMU Configuration
-
-	.equ	PSShift, 8
-	.equ	PS0Shift, 8
-	.equ	PS1Shift, 12
-
-; LRU Recommendation (LRU)
-	.equ	LRUMask, 0xff
-
-; Reason Vector (RSN)
-	.equ 	RSNMask, 0xff
-
-; Region Mapping Address (RMA0 | RMA1)
-	.equ	PBAMask,0xffff
-	.equ	VBAShift, 16
-
-; Region Mapping Control (RMC0 | RMC1)
-	.equ	TIDMask, 0xff
-	.equ	RMC_UE, 0x100
-	.equ	RMC_UW, 0x200
-	.equ	RMC_UR, 0x400
-	.equ	RMC_SE, 0x800
-	.equ	RMC_SW, 0x1000
-	.equ	RMC_SR, 0x2000
-	.equ	RMC_VE, 0x4000
-	.equ	RMC_IO, 0x10000
-	.equ	RGSShift, 17
-	.equ	RMC_PGMShift, 22
-
-; Instruction breakpoint Control (IBC0 | IBC1)
-	.equ	BPIDMask, 0xff
-	.equ	BTE, 0x100
-	.equ	BRM, 0x200
-	.equ	IBC_BSY, 0x400
-	.equ	BEN, 0x800
-	.equ	BHO, 0x1000
-
-; Cache Data Register (CDR)
-	.equ	CDR_US, 0x1
-	.equ	P, 0x2
-	.equ	CDR_V, 0x4
-	.equ	IATAGShift, 20
-
-; Cache Interface Register (CIR)
-	.equ	CPTRShift, 2
-	.equ	CIR_RW, 0x1000000
-	.equ	FSELShift, 28
-
-; Indirect Pointer A, B, C (IPA, IPB, IPC)
-	.equ	IPShift, 2
-
-; ALU Status (ALU)
-	.equ	FCMask, 0x1F
-	.equ	BPShift, 5
-	.equ	C, 0x80
-	.equ	Z, 0x100
-	.equ	N, 0x200
-	.equ	ALU_V, 0x400
-	.equ	DF, 0x800
-
-; Byte Pointer
-	.equ	BPMask, 0x3
-
-; Load/Store Count Remaining (CR)
-	.equ	CRMask, 0xff
-
-; Floating Point Environment (FPE)
-	.equ	NM, 0x1
-	.equ	RM, 0x2
-	.equ	VM, 0x4
-	.equ	UM, 0x8
-	.equ	XM, 0x10
-	.equ	DM, 0x20
-	.equ 	FRMShift, 6
-	.equ	FF, 0x100
-	.equ	ACFShift, 9
-
-; Integer Environment (INTE)
-	.equ	MO, 0x1
-	.equ	DO, 0x2
-
-; Floating Point Status (FPS)
-	.equ	NS, 0x1
-	.equ	RS, 0x2
-	.equ	VS, 0x4
-	.equ	FPS_US, 0x8
-	.equ	XS, 0x10
-	.equ	DS, 0x20
-	.equ	NT, 0x100
-	.equ	RT, 0x200
-	.equ	VT, 0x400
-	.equ	UT, 0x800
-	.equ	XT, 0x1000
-	.equ	DT, 0x2000
-
-; Exception Opcode (EXOP)
-	.equ	IOPMask, 0xff
-
-; TLB Entry Word 0
-;	.equ	TIDMask, 0xff	already defined above
-	.equ	TLB_UE, 0x100
-	.equ	TLB_UW, 0x200
-	.equ	TLB_UR, 0x400
-	.equ	TLB_SE, 0x800
-	.equ	TLB_SW, 0x1000
-	.equ	TLB_SR, 0x2000
-	.equ	TLB_VE, 0x4000
-	.equ	VTAGShift, 15
-
-; TLB Entry Word 1
-	.equ	TLB_IO, 0x1
-	.equ	U, 0x2
-	.equ	TLB_PGMShift, 6
-	.equ	RPNShift, 10
-
-; Am29200 ROM Control bits.
-	.equ	RMCT_DW0Shift, 29
-	.equ	RMCT_DW1Shift, 21
-	.equ	RMCT_DW2Shift, 13
-	.equ	RMCT_DW3Shift, 5
-
-; Am29200 DRAM Control bits.
-	.equ	DW3, (1<<18)
-	.equ	DW2, (1<<22)
-	.equ	DW1, (1<<26)
-	.equ	DW0, (1<<30)
-
-	; Internal peripheral address assignments.
-	.equ	RMCT, 0x80000000
-	.equ	RMCF, 0x80000004
-	.equ	DRCT, 0x80000008
-	.equ	DRCF, 0x8000000C
-	.equ	DRM0, 0x80000010
-	.equ	DRM1, 0x80000014
-	.equ	DRM2, 0x80000018
-	.equ	DRM3, 0x8000001C
-	.equ	PIACT0, 0x80000020
-	.equ	PIACT1, 0x80000020
-	.equ	ICT, 0x80000028
-	.equ	DMCT0, 0x80000030
-	.equ	DMAD0, 0x80000034
-	.ifdef	revA
-	.equ	TAD0, 0x80000036
-	.equ	TCN0, 0x8000003A
-	.else
-	.equ	TAD0, 0x80000070	; default
-	.equ	TCN0, 0x8000003C	; default
-	.endif
-	.equ	DMCN0, 0x80000038
-	.equ	DMCT1, 0x80000040
-	.equ	DMAD1, 0x80000044
-	.equ	DMCN1, 0x80000048
-	.equ	SPCT, 0x80000080
-	.equ	SPST, 0x80000084
-	.equ	SPTH, 0x80000088
-	.equ	SPRB, 0x8000008C
-	.equ	BAUD, 0x80000090
-	.equ	PPCT, 0x800000C0
-	.equ	PPST, 0x800000C1
-	.equ	PPDT, 0x800000C4
-	.equ	POCT, 0x800000D0
-	.equ	PIN, 0x800000D4
-	.equ	POUT, 0x800000D8
-	.equ	POEN, 0x800000DC
-	.equ	VCT, 0x800000E0
-	.equ	TOP, 0x800000E4
-	.equ	SIDE, 0x800000E8
-	.equ	VDT, 0x800000EC
-
-	; Interrupt Controller Register bits.
-	.equ	TXDI,	(1<<5)
-	.equ	RXDI,	(1<<6)
-	.equ	RXSI,	(1<<7)
-	.equ	PPI,	(1<<11)
-	.equ	DMA1I,	(1<<13)
-	.equ	DMA0I,	(1<<14)
-	.equ	IOPIMask,	(0xFF<<16)
-	.equ	VDI,	(1<<27)
-	.equ	ICT200_I,  (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI)
-	.equ	ICT205_I,  (TXDI|RXDI|RXSI|PPI|DMA1I|DMA0I|IOPIMask|VDI)
-
-	; Serial port Initialization bits
-	.equ	NO_PARITY,	0
-	
-
-	; SPST bits
-	.equ	THREShift, 22
-
-;* REGISTER Addresses
-
-	.equ	ROMCntlRegAddr,		0x80000000
-
-	.equ	ROMCfgRegAddr, 		0x80000004
-
-	.equ	DRAMCntlRegAddr,	0x80000008
-
-	.equ	DRAMCfgRegAddr,		0x8000000C
-
-	.equ	DRAMMap0RegAddr,	0x80000010
-
-	.equ	DRAMMap1RegAddr,	0x80000014
-
-	.equ	DRAMMap2RegAddr,	0x80000018
-
-	.equ	DRAMMap3RegAddr,	0x8000001C
-
-	.equ	PIACntl0RegAddr,	0x80000020
-
-	.equ	PIACntl1RegAddr,	0x80000024
-
-	.equ	INTRCntlRegAddr,	0x80000028
-
-	.equ	DMACntl0RegAddr,	0x80000030
-
-	.equ	DMACntl1RegAddr,	0x80000040
-
-	.equ	SERPortCntlRegAddr,	0x80000080
-
-	.equ	SERPortStatRegAddr,	0x80000084
-
-	.equ	SERPortTHLDRegAddr,	0x80000088
-
-	.equ	SERPortRbufRegAddr,	0x8000008C
-
-	.equ	SERPortBaudRegAddr,	0x80000090
-
-	.equ	PARPortCntlRegAddr,	0x800000C0
-
-	.equ	PIOCntlRegAddr,		0x800000D0
-
-	.equ	PIOInpRegAddr,		0x800000D4
-
-	.equ	PIOOutRegAddr,		0x800000D8
-
-	.equ	PIOOutEnaRegAddr,	0x800000DC
-
-	.equ	VCTCntlRegAddr,		0x800000E0
-
-;
-;* Control constants
-;
-
-;* AM29030 Timer related constants.
-
-	.equ	TMR_IE,			0x01000000
-
-	.equ	TMR_IN,			0x02000000
-
-	.equ	TMR_OV,			0x04000000
-
-	.equ	TMC_INITCNT, 		1613
-
-;
-;* System initialization values.
-;
-
-	.equ	__os_version,		0x0001		;
-
-	.equ	STACKSize,		0x8000		;
-
-	.equ	PGMExecMode,		0x0000		;
-
-	.equ	TSTCK_OFST,		28 * 4
-
-	.equ	CSTCK_OFST,		29 * 4
-
-	.equ	TMSTCK_OFST,		30 * 4
-
-	.equ	CMSTCK_OFST,		31 * 4
-
-	.equ	CTXSW_OK, 		0xA55A		; ctx switch ok
-
-	.set	NV_STARTOFST,		0x20		; 32 bytes
-
-	.set	NV_BAUDOFST,		0x00		; 00 bytes
-
-	.set	reg_cir, 		29
-
-	.set	reg_cdr, 		30
-
-	.equ	MSG_BUFSIZE,		0x1000		; serial buffer size 
-
-        .equ    ILLOPTRAP,      	0
-
-        .equ    UATRAP,         	1
-
-        .equ    PVTRAP,         	5
-
-        .equ    UITLBMISSTRAP,  	8
-
-        .equ    UDTLBMISSTRAP,  	9
-
-        .equ    TIMERTRAP,      	14
-
-        .equ    TRACETRAP,      	15
-
-        .equ    XLINXTRAP,      	16
-
-        .equ    SERIALTRAP,     	17
-
-        .equ    SLOWTMRTRAP,    	18
-
-        .equ    PORTTRAP,       	19
-
-        .equ    SVSCTRAP,       	80
-
-        .equ    SVSCTRAP1,       	81
-
-        .equ    V_CACHETRAP,      	66		;
-
-        .equ    V_SETSERVICE,      	67		;
-- 
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