From 8b9128277d4992c413a86b8ed1b519e83aab4b3b Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Tue, 21 Dec 1999 14:27:52 +0000 Subject: Patch rtems-rc-19991203-5.diff from Ralf Corsepius which cleans up and merges some Hitachi SH-2 modifications from John Mills . --- c/src/lib/libcpu/sh/sh7045/include/io_types.h | 30 ++-- c/src/lib/libcpu/sh/sh7045/include/iosh7045.h | 2 +- c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h | 233 ++++++++++++++++++-------- c/src/lib/libcpu/sh/sh7045/sci/sci.c | 110 ++++++------ 4 files changed, 237 insertions(+), 138 deletions(-) (limited to 'c/src/lib/libcpu') diff --git a/c/src/lib/libcpu/sh/sh7045/include/io_types.h b/c/src/lib/libcpu/sh/sh7045/include/io_types.h index 18ba181143..8d817e9aee 100644 --- a/c/src/lib/libcpu/sh/sh7045/include/io_types.h +++ b/c/src/lib/libcpu/sh/sh7045/include/io_types.h @@ -16,15 +16,15 @@ * found in the file LICENSE in this distribution or at * http://www.OARcorp.com/rtems/license.html. * - * John M. Mills (jmills@tga.com) - * TGA Technologies, Inc. - * 100 Pinnacle Way, Suite 140 - * Norcross, GA 30071 U.S.A. + * John M. Mills (jmills@tga.com) + * TGA Technologies, Inc. + * 100 Pinnacle Way, Suite 140 + * Norcross, GA 30071 U.S.A. * - * This modified file may be copied and distributed in accordance - * the above-referenced license. It is provided for critique and - * developmental purposes without any warranty nor representation - * by the authors or by TGA Technologies. + * This modified file may be copied and distributed in accordance + * the above-referenced license. It is provided for critique and + * developmental purposes without any warranty nor representation + * by the authors or by TGA Technologies. * * $Id$ * @@ -43,13 +43,13 @@ typedef enum {one, two} stopBits; typedef enum {even, odd} parity; typedef struct { - portNo line; - int speed_ix; - dataBits dBits; - int parEn; - parity par; - int mulPro; - stopBits sBits; + portNo line; + int speed_ix; + dataBits dBits; + int parEn; + parity par; + int mulPro; + stopBits sBits; } sci_setup_t; typedef union{ diff --git a/c/src/lib/libcpu/sh/sh7045/include/iosh7045.h b/c/src/lib/libcpu/sh/sh7045/include/iosh7045.h index 327cd34f86..62918dd958 100644 --- a/c/src/lib/libcpu/sh/sh7045/include/iosh7045.h +++ b/c/src/lib/libcpu/sh/sh7045/include/iosh7045.h @@ -307,7 +307,7 @@ #define PFC_PEIOR (REG_BASE + 0x03B4) /* Port E I/O Register */ #define PFC_PECR1 (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */ #define PFC_PECR2 (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */ -#define PFC_IFCR (REG_BASE + 0x03C8) /* short */ +#define PFC_IFCR (REG_BASE + 0x03C8) /* short */ /*Compare/Match Timer*/ #define CMT_CMSTR (REG_BASE + 0x3D0) /* Start Reg. char, short, word */ diff --git a/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h b/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h index 5be9ca8a5d..5640e0f630 100644 --- a/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h +++ b/c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h @@ -29,90 +29,177 @@ #include +/* + * Port A IO Registers (PAIORH, PAIORL) + * 1 => OUTPUT + * 0 => INPUT + */ +#define PAIORH PFC_PAIORH +#define PAIORL PFC_PAIORL + +/* PAIORH */ +#define PA23IOR 0x0080 +#define PA22IOR 0x0040 +#define PA21IOR 0x0020 +#define PA20IOR 0x0010 +#define PA19IOR 0x0008 +#define PA18IOR 0x0004 +#define PA17IOR 0x0002 +#define PA16IOR 0x0001 + +/* PAIORL */ +#define PA15IOR 0x8000 +#define PA14IOR 0x4000 +#define PA13IOR 0x2000 +#define PA12IOR 0x1000 +#define PA11IOR 0x0800 +#define PA10IOR 0x0400 +#define PA9IOR 0x0200 +#define PA8IOR 0x0100 +#define PA7IOR 0x0080 +#define PA6IOR 0x0040 +#define PA5IOR 0x0020 +#define PA4IOR 0x0010 +#define PA3IOR 0x0008 +#define PA2IOR 0x0004 +#define PA1IOR 0x0002 +#define PA0IOR 0x0001 + +/* + * Port A Control Registers (PACRH, PACRL1, PACRL2) + * and mode bits + */ +#define PACRH PFC_PACRH +#define PACRL1 PFC_PACRL1 +#define PACRL2 PFC_PACRL2 + +/* PACRH */ +#define PA23MD0 0x4000 +#define PA22MD0 0x1000 +#define PA21MD0 0x0400 +#define PA20MD0 0x0100 +#define PA19MD1 0x0080 +#define PA19MD0 0x0040 +#define PA18MD1 0x0020 +#define PA18MD0 0x0010 +#define PA17MD0 0x0004 +#define PA16MD0 0x0001 + +/* PACRL1 */ +#define PA15MD0 0x4000 +#define PA14MD0 0x1000 +#define PA13MD0 0x0400 +#define PA12MD0 0x0100 +#define PA11MD0 0x0040 +#define PA10MD0 0x0010 +#define PA9MD1 0x0008 +#define PA9MD0 0x0004 +#define PA8MD1 0x0002 +#define PA8MD0 0x0001 + +/* PACRL2 */ +#define PA7MD1 0x8000 +#define PA7MD0 0x4000 +#define PA6MD1 0x2000 +#define PA6MD0 0x1000 +#define PA5MD1 0x0800 +#define PA5MD0 0x0400 +#define PA4MD0 0x0100 +#define PA3MD0 0x0040 +#define PA2MD1 0x0020 +#define PA2MD0 0x0010 +#define PA1MD0 0x0004 +#define PA0MD0 0x0001 + +#define PA_TXD1 PA4MD0 +#define PA_RXD1 PA3MD0 +#define PA_TXD0 PA1MD0 +#define PA_RXD0 PA0MD0 + /* * Port B IO Register (PBIOR) */ -#define PBIOR PFC_PBIOR -#define PB15IOR 0x8000 -#define PB14IOR 0x4000 -#define PB13IOR 0x2000 -#define PB12IOR 0x1000 -#define PB11IOR 0x0800 -#define PB10IOR 0x0400 -#define PB9IOR 0x0200 -#define PB8IOR 0x0100 -#define PB7IOR 0x0080 -#define PB6IOR 0x0040 -#define PB5IOR 0x0020 -#define PB4IOR 0x0010 -#define PB3IOR 0x0008 -#define PB2IOR 0x0004 -#define PB1IOR 0x0002 -#define PB0IOR 0x0001 +#define PBIOR PFC_PBIOR +#define PB15IOR 0x8000 +#define PB14IOR 0x4000 +#define PB13IOR 0x2000 +#define PB12IOR 0x1000 +#define PB11IOR 0x0800 +#define PB10IOR 0x0400 +#define PB9IOR 0x0200 +#define PB8IOR 0x0100 +#define PB7IOR 0x0080 +#define PB6IOR 0x0040 +#define PB5IOR 0x0020 +#define PB4IOR 0x0010 +#define PB3IOR 0x0008 +#define PB2IOR 0x0004 +#define PB1IOR 0x0002 +#define PB0IOR 0x0001 /* * Port B Control Register (PBCR1) */ -#define PBCR1 PFC_PBCR1 -#define PB15MD1 0x8000 -#define PB15MD0 0x4000 -#define PB14MD1 0x2000 -#define PB14MD0 0x1000 -#define PB13MD1 0x0800 -#define PB13MD0 0x0400 -#define PB12MD1 0x0200 -#define PB12MD0 0x0100 -#define PB11MD1 0x0080 -#define PB11MD0 0x0040 -#define PB10MD1 0x0020 -#define PB10MD0 0x0010 -#define PB9MD1 0x0008 -#define PB9MD0 0x0004 -#define PB8MD1 0x0002 -#define PB8MD0 0x0001 - -#define PB15MD PB15MD1|PB14MD0 -#define PB14MD PB14MD1|PB14MD0 -#define PB13MD PB13MD1|PB13MD0 -#define PB12MD PB12MD1|PB12MD0 -#define PB11MD PB11MD1|PB11MD0 -#define PB10MD PB10MD1|PB10MD0 -#define PB9MD PB9MD1|PB9MD0 -#define PB8MD PB8MD1|PB8MD0 - -#define PB_TXD1 PB11MD1 -#define PB_RXD1 PB10MD1 -#define PB_TXD0 PB9MD1 -#define PB_RXD0 PB8MD1 +#define PBCR1 PFC_PBCR1 +#define PB15MD1 0x8000 +#define PB15MD0 0x4000 +#define PB14MD1 0x2000 +#define PB14MD0 0x1000 +#define PB13MD1 0x0800 +#define PB13MD0 0x0400 +#define PB12MD1 0x0200 +#define PB12MD0 0x0100 +#define PB11MD1 0x0080 +#define PB11MD0 0x0040 +#define PB10MD1 0x0020 +#define PB10MD0 0x0010 +#define PB9MD1 0x0008 +#define PB9MD0 0x0004 +#define PB8MD1 0x0002 +#define PB8MD0 0x0001 + +#define PB15MD PB15MD1|PB14MD0 +#define PB14MD PB14MD1|PB14MD0 +#define PB13MD PB13MD1|PB13MD0 +#define PB12MD PB12MD1|PB12MD0 +#define PB11MD PB11MD1|PB11MD0 +#define PB10MD PB10MD1|PB10MD0 +#define PB9MD PB9MD1|PB9MD0 +#define PB8MD PB8MD1|PB8MD0 + +#define PB_TXD1 PB11MD1 +#define PB_RXD1 PB10MD1 +#define PB_TXD0 PB9MD1 +#define PB_RXD0 PB8MD1 /* * Port B Control Register (PBCR2) */ -#define PBCR2 PFC_PBCR2 -#define PB7MD1 0x8000 -#define PB7MD0 0x4000 -#define PB6MD1 0x2000 -#define PB6MD0 0x1000 -#define PB5MD1 0x0800 -#define PB5MD0 0x0400 -#define PB4MD1 0x0200 -#define PB4MD0 0x0100 -#define PB3MD1 0x0080 -#define PB3MD0 0x0040 -#define PB2MD1 0x0020 -#define PB2MD0 0x0010 -#define PB1MD1 0x0008 -#define PB1MD0 0x0004 -#define PB0MD1 0x0002 -#define PB0MD0 0x0001 +#define PBCR2 PFC_PBCR2 +#define PB7MD1 0x8000 +#define PB7MD0 0x4000 +#define PB6MD1 0x2000 +#define PB6MD0 0x1000 +#define PB5MD1 0x0800 +#define PB5MD0 0x0400 +#define PB4MD1 0x0200 +#define PB4MD0 0x0100 +#define PB3MD1 0x0080 +#define PB3MD0 0x0040 +#define PB2MD1 0x0020 +#define PB2MD0 0x0010 +#define PB1MD1 0x0008 +#define PB1MD0 0x0004 +#define PB0MD1 0x0002 +#define PB0MD0 0x0001 -#define PB7MD PB7MD1|PB7MD0 -#define PB6MD PB6MD1|PB6MD0 -#define PB5MD PB5MD1|PB5MD0 -#define PB4MD PB4MD1|PB4MD0 -#define PB3MD PB3MD1|PB3MD0 -#define PB2MD PB2MD1|PB2MD0 -#define PB1MD PB1MD1|PB1MD0 -#define PB0MD PB0MD1|PB0MD0 +#define PB7MD PB7MD1|PB7MD0 +#define PB6MD PB6MD1|PB6MD0 +#define PB5MD PB5MD1|PB5MD0 +#define PB4MD PB4MD1|PB4MD0 +#define PB3MD PB3MD1|PB3MD0 +#define PB2MD PB2MD1|PB2MD0 +#define PB1MD PB1MD1|PB1MD0 +#define PB0MD PB0MD1|PB0MD0 #endif /* _sh7_pfc_h */ diff --git a/c/src/lib/libcpu/sh/sh7045/sci/sci.c b/c/src/lib/libcpu/sh/sh7045/sci/sci.c index 8f7739275e..3a443e64ee 100644 --- a/c/src/lib/libcpu/sh/sh7045/sci/sci.c +++ b/c/src/lib/libcpu/sh/sh7045/sci/sci.c @@ -119,7 +119,9 @@ void sh_sci_outbyte_polled( while (wrtSCI1(ch) != TRUE); /* SCI1*/ } /* sh_sci_outbyte_polled */ -/* Initial version calls polled output driver and blocks */ +/* + * Initial version calls polled output driver and blocks + */ void outbyte( rtems_device_minor_number minor, char ch) @@ -186,13 +188,16 @@ char inbyte( /* sh_sci_initialize * - * This routine initializes the sh_sci IO driver. + * This routine initializes (registers) the sh_sci IO drivers. * - * Input parameters: NONE + * Input parameters: ignored * * Output parameters: NONE * - * Return values: + * Return values: RTEMS_SUCCESSFUL + * if all sci[...] register, else calls + * rtems_fatal_error_occurred(status) + * */ rtems_device_driver sh_sci_initialize( @@ -200,39 +205,34 @@ rtems_device_driver sh_sci_initialize( rtems_device_minor_number minor, void *arg ) { - int a; - unsigned16 temp16; rtems_device_driver status ; + rtems_device_minor_number i; + + /* + * register all possible devices. + * the initialization of the hardware is done by sci_open + */ - /* register devices */ - for ( a = 0 ; a < 2 ; a++ ) + for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ ) { status = rtems_io_register_name( - sci_device[a].name, + sci_device[i].name, major, - sci_device[a].minor ); + sci_device[i].minor ); if (status != RTEMS_SUCCESSFUL) rtems_fatal_error_occurred(status); } - /* default hardware setup */ + /* non-default hardware setup occurs in sh_sci_open() */ - /* general setup */ - temp16 = read16(PFC_PECR1) | 0x0800; /* General I/O except pin 13 (reset) */ - write16(temp16, PFC_PECR1); - write16(0x00, PFC_PECR2); /* All I/O lines bits 7-0 */ - temp16 = read16(PFC_PEIOR) | 0x0020; /* P5 to out, all other pins in */ - write16(temp16, PFC_PEIOR); - - temp16 = read16(PFC_PACRL2) | 0x0145; /* PFC - pins for Tx0-1, Rx0-1 */ - write16(temp16, PFC_PACRL2); - return RTEMS_SUCCESSFUL; } /* * Open entry point + * Sets up port and pins for selected sci. + * SCI0 setup is conditional on STANDALONE_EVB == 1 */ rtems_device_driver sh_sci_open( @@ -241,46 +241,58 @@ rtems_device_driver sh_sci_open( void * arg ) { unsigned8 temp8; + unsigned16 temp16; unsigned char smr ; unsigned char brr ; unsigned a ; + /* check for valid minor number */ + if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 )) + { + return RTEMS_INVALID_NUMBER; + } + /* device already opened */ if ( sci_device[minor].opened > 0 ) { sci_device[minor].opened++ ; - return RTEMS_SUCCESSFUL ; } - /* retrieve brr and smr values */ - _sci_get_brparms( sci_device[minor].cflags, &smr, &brr ); - - if (minor == 0) { - write8(0x00, SCI_SCR0); /* Clear SCR */ - write8(smr, SCI_SMR0); /* Clear SMR */ - write8(brr, SCI_BRR0); /* Default 9600 baud rate */ -#if 0 - write8(0x1F, SCI_BRR0); /* 28800 baud */ -#endif -/* FIXME: Will get optimized away */ - for(a=0;a<10000L;a++); /* One bit delay */ - write8(0x30, SCI_SCR0); /* Enable clock output */ - temp8 = read8(SCI_RDR0); /* Clear out old input */ - - } else { - write8(0x00, SCI_SCR1); /* Clear SCR */ - write8(smr, SCI_SMR1); /* Clear SMR */ - write8(brr, SCI_BRR1); /* Default 9600 baud rate */ -#if 0 - write8(0x1F, SCI_BRR1); /* 28800 baud */ -#endif -/* FIXME: Will get optimized away */ - for(a=0;a<10000L;a++); /* One bit delay */ - write8(0x30, SCI_SCR1); /* Enable clock output */ - temp8 = read8(SCI_RDR1); /* Clear out old input */ - } + /* enable I/O pins */ + + if ((minor == 0) && (STANDALONE_EVB == 1)) { + temp16 = read16(PFC_PACRL2) & /* disable SCK0, Tx0, Rx0 */ + ~(PA2MD1 | PA2MD0 | PA1MD0 | PA0MD0); + temp16 |= (PA_TXD0 | PA_RXD0); /* assign pins for Tx0, Rx0 */ + write16(temp16, PFC_PACRL2); + + } else if (minor == 1) { + temp16 = read16(PFC_PACRL2) & /* disable SCK1, Tx1, Rx1 */ + ~(PA5MD1 | PA5MD0 | PA4MD0 | PA3MD0); + temp16 |= (PA_TXD1 | PA_RXD1); /* assign pins for Tx1, Rx1 */ + write16(temp16, PFC_PACRL2); + + } /* add other devices and pins as req'd. */ + + /* set up SCI registers */ + if ((minor != 0) || (STANDALONE_EVB == 1)) { + write8(0x00, sci_device[minor].addr + SCI_SCR); /* Clear SCR */ + /* set SCR and BRR */ + _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags ); + + for(a=0; a < 10000L; a++) { /* One-bit delay */ + asm volatile ("nop"); + } + + write8((SCI_RE | SCI_TE), /* enable async. Tx and Rx */ + sci_device[minor].addr + SCI_SCR); + temp8 = read8(sci_device[minor].addr + SCI_RDR); /* flush input */ + + /* add interrupt setup if required */ + + } sci_device[minor].opened++ ; -- cgit v1.2.3