From 5175ac6a87e40c22a4aaf4a70e9ced375a76fe98 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 19 Dec 2014 12:12:08 +0100 Subject: bsps/powerpc: Support a cache alignment of 64 Give the BSP the ability to define PPC_CACHE_ALIGNMENT. --- c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) (limited to 'c/src/lib/libcpu') diff --git a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h index 9b9f738c6c..2a895e1201 100644 --- a/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h +++ b/c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h @@ -61,6 +61,12 @@ extern "C" { #include +/* + * Unfortunately it is very inefficient to use run-time detection for the cache + * line size, so give the BSP the opportunity to define it here. + */ +#include + /* * This file contains the information required to build * RTEMS for a particular member of the PowerPC family. It does @@ -271,7 +277,6 @@ extern "C" { #define PPC_USE_MULTIPLE 1 #elif defined(__ppc_generic) -#define PPC_CACHE_ALIGNMENT 32 #else @@ -302,6 +307,8 @@ extern "C" { #define PPC_CACHE_ALIGN_POWER 4 #elif (PPC_CACHE_ALIGNMENT == 32) #define PPC_CACHE_ALIGN_POWER 5 +#elif (PPC_CACHE_ALIGNMENT == 64) +#define PPC_CACHE_ALIGN_POWER 6 #elif (PPC_CACHE_ALIGNMENT == PPC_NO_CACHE_ALIGNMENT) #define PPC_CACHE_ALIGN_POWER PPC_NO_CACHE_ALIGNMENT_POWER #else -- cgit v1.2.3