From ee733965291f61dd959c0f75659b0482df7a64ca Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 17 Feb 1999 20:24:53 +0000 Subject: Jay Monkman submitted the eth_comm BSP for a PPC860 based board. --- c/src/lib/libcpu/powerpc/mpc860/Makefile.in | 14 + c/src/lib/libcpu/powerpc/mpc860/README | 22 + c/src/lib/libcpu/powerpc/mpc860/clock/Makefile.in | 60 ++ c/src/lib/libcpu/powerpc/mpc860/clock/clock.c | 186 ++++ .../powerpc/mpc860/console-generic/Makefile.in | 59 ++ .../mpc860/console-generic/console-generic.c | 938 ++++++++++++++++++++ .../lib/libcpu/powerpc/mpc860/include/Makefile.in | 29 + c/src/lib/libcpu/powerpc/mpc860/include/console.h | 44 + c/src/lib/libcpu/powerpc/mpc860/timer/Makefile.in | 60 ++ c/src/lib/libcpu/powerpc/mpc860/timer/timer.c | 104 +++ .../lib/libcpu/powerpc/mpc860/vectors/Makefile.in | 59 ++ c/src/lib/libcpu/powerpc/mpc860/vectors/README | 25 + c/src/lib/libcpu/powerpc/mpc860/vectors/align_h.S | 435 ++++++++++ c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S | 952 +++++++++++++++++++++ 14 files changed, 2987 insertions(+) create mode 100644 c/src/lib/libcpu/powerpc/mpc860/Makefile.in create mode 100644 c/src/lib/libcpu/powerpc/mpc860/README create mode 100644 c/src/lib/libcpu/powerpc/mpc860/clock/Makefile.in create mode 100644 c/src/lib/libcpu/powerpc/mpc860/clock/clock.c create mode 100644 c/src/lib/libcpu/powerpc/mpc860/console-generic/Makefile.in create mode 100644 c/src/lib/libcpu/powerpc/mpc860/console-generic/console-generic.c create mode 100644 c/src/lib/libcpu/powerpc/mpc860/include/Makefile.in create mode 100644 c/src/lib/libcpu/powerpc/mpc860/include/console.h create mode 100644 c/src/lib/libcpu/powerpc/mpc860/timer/Makefile.in create mode 100644 c/src/lib/libcpu/powerpc/mpc860/timer/timer.c create mode 100644 c/src/lib/libcpu/powerpc/mpc860/vectors/Makefile.in create mode 100644 c/src/lib/libcpu/powerpc/mpc860/vectors/README create mode 100644 c/src/lib/libcpu/powerpc/mpc860/vectors/align_h.S create mode 100644 c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S (limited to 'c/src/lib/libcpu/powerpc') diff --git a/c/src/lib/libcpu/powerpc/mpc860/Makefile.in b/c/src/lib/libcpu/powerpc/mpc860/Makefile.in new file mode 100644 index 0000000000..2439fbdc40 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/Makefile.in @@ -0,0 +1,14 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/directory.cfg + +SUB_DIRS=include console-generic clock timer vectors diff --git a/c/src/lib/libcpu/powerpc/mpc860/README b/c/src/lib/libcpu/powerpc/mpc860/README new file mode 100644 index 0000000000..528506d3dd --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/README @@ -0,0 +1,22 @@ +# +# $Id$ +# + +Various non BSP dependant support routines. + +clock - Uses the 403 PIT (Programmable interval timer) to + generate RTEMS clock ticks. + +console - Uses the 403 Internal serial port to do RTEMS + console I/O. Not ALL members of the 403 family + have this. + +include - Currently empty + +timer - Uses the 403 timebase register for timing + tests. Other PowerPCs have slightly different + timebase register definitions. + +vectors - PowerPC 403 specific vector entry points. + Includes CPU dependant, application independant + handlers: alignment. diff --git a/c/src/lib/libcpu/powerpc/mpc860/clock/Makefile.in b/c/src/lib/libcpu/powerpc/mpc860/clock/Makefile.in new file mode 100644 index 0000000000..7b299d4ef0 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/clock/Makefile.in @@ -0,0 +1,60 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/clock.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=clock +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES= +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += $(CFLAGS_OS_V) + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by +# libbsp/hppa/BSP/wrapup/Makefile +install: all diff --git a/c/src/lib/libcpu/powerpc/mpc860/clock/clock.c b/c/src/lib/libcpu/powerpc/mpc860/clock/clock.c new file mode 100644 index 0000000000..928c9e5a96 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/clock/clock.c @@ -0,0 +1,186 @@ +/* clock.c + * + * This routine initializes the PIT on the MPC860. + * The tick frequency is specified by the bsp. + * + * Author: Jay Monkman (jmonkman@frasca.com) + * Copyright (C) 1998 by Frasca International, Inc. + * + * Derived from c/src/lib/libcpu/ppc/ppc403/clock/clock.c: + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libcpu/hppa1_1/clock/clock.c: + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include +#include + +#include /* for atexit() */ +#include + +extern rtems_cpu_table Cpu_table; /* owned by BSP */ + +volatile rtems_unsigned32 Clock_driver_ticks; +extern volatile m860_t m860; + +void Clock_exit( void ); + +/* + * These are set by clock driver during its init + */ + +rtems_device_major_number rtems_clock_major = ~0; +rtems_device_minor_number rtems_clock_minor; + +/* + * ISR Handler + */ +rtems_isr Clock_isr(rtems_vector_number vector) +{ + m860.piscr |= M860_PISCR_PS; + Clock_driver_ticks++; + rtems_clock_tick(); +} + +void Install_clock(rtems_isr_entry clock_isr) +{ + rtems_isr_entry previous_isr; + rtems_unsigned32 pit_value; + + Clock_driver_ticks = 0; + + pit_value = BSP_Configuration.microseconds_per_tick * + Cpu_table.clicks_per_usec; + if (pit_value == 0) { + pit_value = 0xffff; + } else { + pit_value--; + } + + if (pit_value > 0xffff) { /* pit is only 16 bits long */ + rtems_fatal_error_occurred(-1); + } + if (BSP_Configuration.ticks_per_timeslice) { + + /* + * initialize the interval here + * First tick is set to right amount of time in the future + * Future ticks will be incremented over last value set + * in order to provide consistent clicks in the face of + * interrupt overhead + */ + + rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr); + + m860.sccr &= ~(1<<24); + m860.pitc = pit_value; + + /* set PIT irq level, enable PIT, PIT interrupts */ + /* and clear int. status */ + m860.piscr = M860_PISCR_PIRQ(0) | + M860_PISCR_PTE | M860_PISCR_PS | M860_PISCR_PIE; + + m860.simask |= M860_SIMASK_LVM0; + } + atexit(Clock_exit); +} + +void +ReInstall_clock(rtems_isr_entry new_clock_isr) +{ + rtems_isr_entry previous_isr; + rtems_unsigned32 isrlevel = 0; + + rtems_interrupt_disable(isrlevel); + + rtems_interrupt_catch(new_clock_isr, PPC_IRQ_LVL0, &previous_isr); + + rtems_interrupt_enable(isrlevel); +} + + +/* + * Called via atexit() + * Remove the clock interrupt handler by setting handler to NULL + */ +void +Clock_exit(void) +{ + if ( BSP_Configuration.ticks_per_timeslice ) { + /* disable PIT and PIT interrupts */ + m860.piscr &= ~(M860_PISCR_PTE | M860_PISCR_PIE); + + (void) set_vector(0, PPC_IRQ_LVL0, 1); + } +} + +rtems_device_driver Clock_initialize( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + Install_clock( Clock_isr ); + + /* + * make major/minor avail to others such as shared memory driver + */ + + rtems_clock_major = major; + rtems_clock_minor = minor; + + return RTEMS_SUCCESSFUL; +} + +rtems_device_driver Clock_control( + rtems_device_major_number major, + rtems_device_minor_number minor, + void *pargp +) +{ + rtems_libio_ioctl_args_t *args = pargp; + + if (args == 0) + goto done; + + /* + * This is hokey, but until we get a defined interface + * to do this, it will just be this simple... + */ + + if (args->command == rtems_build_name('I', 'S', 'R', ' ')) { + Clock_isr(PPC_IRQ_LVL0); + } + else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) { + ReInstall_clock(args->buffer); + } + + done: + return RTEMS_SUCCESSFUL; +} + diff --git a/c/src/lib/libcpu/powerpc/mpc860/console-generic/Makefile.in b/c/src/lib/libcpu/powerpc/mpc860/console-generic/Makefile.in new file mode 100644 index 0000000000..b538d198f7 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/console-generic/Makefile.in @@ -0,0 +1,59 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/console-generic.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=console-generic +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES= +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libcpu/powerpc/mpc860/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc860/console-generic/console-generic.c new file mode 100644 index 0000000000..bbf9748c12 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/console-generic/console-generic.c @@ -0,0 +1,938 @@ +/* + * General Serial I/O functions. + * + * This file contains the functions for performing serial I/O. + * The actual system calls (console_*) should be in the BSP part + * of the source tree. That way different BSPs can use whichever + * SMCs and SCCs they want. Originally, all the stuff was in + * this file, and it caused problems with one BSP using SCC2 + * as /dev/console, others using SMC1 for /dev/console, etc. + * + * On-chip resources used: + * resource minor note + * SMC1 0 + * SMC2 1 + * SCC1 2 (shared with ethernet driver) + * SCC2 3 + * SCC3 4 + * SCC4 5 + * BRG1 + * BRG2 + * BRG3 + * BRG4 + * Author: Jay Monkman (jmonkman@frasca.com) + * Copyright (C) 1998 by Frasca International, Inc. + * + * Derived from c/src/lib/libbsp/m68k/gen360/console/console.c: + * + * Author: + * W. Eric Norum + * Saskatchewan Accelerator Laboratory + * University of Saskatchewan + * Saskatoon, Saskatchewan, CANADA + * eric@skatter.usask.ca + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include +#include +#include +#include +#include +#include + +#define NIFACES 6 /* number of console devices (serial ports) */ + +extern rtems_cpu_table Cpu_table; /* owned by BSP */ + +static Buf_t *rxBufList[NIFACES]; +static Buf_t *rxBufListTail[NIFACES]; + +/* + * Interrupt-driven input buffer + */ +#define RXBUFSIZE 16 + + +/* + * I/O buffers and pointers to buffer descriptors + */ +static volatile char txBuf[NIFACES]; + +static volatile m860BufferDescriptor_t *RxBd[NIFACES], *TxBd[NIFACES]; + +/* + * Device-specific routines + */ +static int m860_get_brg_cd(int); +unsigned char m860_get_brg_clk(int); +void m860_console_reserve_resources(rtems_configuration_table *); +unsigned char m860_get_brg_clk(int); + + +/* + * Compute baud-rate-generator configuration register value + */ +static int +m860_get_brg_cd (int baud) +{ + int divisor; + int div16 = 0; + + divisor = ((Cpu_table.clock_speed / 16) + (baud / 2)) / baud; + if (divisor > 4096) { + div16 = 1; + divisor = (divisor + 8) / 16; + } + return M860_BRG_EN | M860_BRG_EXTC_BRGCLK | + ((divisor - 1) << 1) | div16; +} + + +/* this function will fail if more that 4 baud rates have been selected */ +/* at any time since the OS started. It needs to be fixed. FIXME */ +unsigned char m860_get_brg_clk(int baud) +{ + static short brg_spd[4]; + static char brg_used[4]; + int i; + + /* first try to find a BRG that is already at the right speed */ + for (i=0; i<4; i++) { + if (brg_spd[i] == baud) { + break; + } + } + + if (i==4) { /* I guess we didn't find one */ + for (i=0; i<4; i++) { + if (brg_used[i] == 0) { + break; + } + } + } + if (i != 4) { + brg_used[i]++; + brg_spd[i]=baud; + switch (i) { + case 0: + m860.brgc1 = M860_BRG_RST; + m860.brgc1 = m860_get_brg_cd(baud); + break; + case 1: + m860.brgc2 = M860_BRG_RST; + m860.brgc2 = m860_get_brg_cd(baud); + break; + case 2: + m860.brgc3 = M860_BRG_RST; + m860.brgc3 = m860_get_brg_cd(baud); + break; + case 3: + m860.brgc4 = M860_BRG_RST; + m860.brgc4 = m860_get_brg_cd(baud); + break; + } + return i; + } + + else + return 0xff; +} + +/* + * Hardware-dependent portion of tcsetattr(). + */ +int +m860_smc_set_attributes (int minor, const struct termios *t) +{ + /* + * minor must be 0 or 1 + */ + int baud; + int brg; + switch (t->c_cflag & CBAUD) { + default: baud = -1; break; + case B50: baud = 50; break; + case B75: baud = 75; break; + case B110: baud = 110; break; + case B134: baud = 134; break; + case B150: baud = 150; break; + case B200: baud = 200; break; + case B300: baud = 300; break; + case B600: baud = 600; break; + case B1200: baud = 1200; break; + case B1800: baud = 1800; break; + case B2400: baud = 2400; break; + case B4800: baud = 4800; break; + case B9600: baud = 9600; break; + case B19200: baud = 19200; break; + case B38400: baud = 38400; break; + case B57600: baud = 57600; break; + case B115200: baud = 115200; break; + case B230400: baud = 230400; break; + case B460800: baud = 460800; break; + } + if (baud > 0) { + brg = m860_get_brg_clk(baud); /* 4 BRGs, 6 serial ports - hopefully */ + /* at least 2 ports will be the same */ + m860.simode |= brg << (12 + ((minor) * 16)); + } + return 0; +} + +int +m860_scc_set_attributes (int minor, const struct termios *t) +{ + /* + * minor must be 2, 3, 4 or 5 + */ + int baud; + int brg; + switch (t->c_cflag & CBAUD) { + default: baud = -1; break; + case B50: baud = 50; break; + case B75: baud = 75; break; + case B110: baud = 110; break; + case B134: baud = 134; break; + case B150: baud = 150; break; + case B200: baud = 200; break; + case B300: baud = 300; break; + case B600: baud = 600; break; + case B1200: baud = 1200; break; + case B1800: baud = 1800; break; + case B2400: baud = 2400; break; + case B4800: baud = 4800; break; + case B9600: baud = 9600; break; + case B19200: baud = 19200; break; + case B38400: baud = 38400; break; + case B57600: baud = 57600; break; + case B115200: baud = 115200; break; + case B230400: baud = 230400; break; + case B460800: baud = 460800; break; + } + if (baud > 0) { + brg = m860_get_brg_clk(baud); /* 4 BRGs, 5 serial ports - hopefully */ + /* at least 2 ports will be the same */ + m860.sicr |= (brg << (3 + ((minor-2) * 8))) | + (brg << ((minor-2) * 8)); + } + return 0; +} + +void +m860_scc_initialize (int port) /* port is the SCC # (i.e. 1, 2, 3 or 4) */ +{ + unsigned char brg; + volatile m860SCCparms_t *sccparms; + volatile m860SCCRegisters_t *sccregs; + + /* + * Allocate buffer descriptors + */ + RxBd[port+1] = M860AllocateBufferDescriptors(1); + TxBd[port+1] = M860AllocateBufferDescriptors(1); + + /* + * Configure ports A and B to enable TXDx and RXDx pins + */ + m860.papar |= (0xC << ((port-2) * 2)); + m860.padir &= ~(0xC << ((port-2) * 2)); + m860.pbdir |= (0x04 << (port-2)); + m860.paodr &= ~(0x8 << ((port-2) * 2)); + m860.pbdat &= ~(0x04 << (port-2)); + + /* SCC2 is the only one with handshaking lines */ + /* + if (port == 2) { + m860.pcpar |= (0x02); + m860.pcpar &= ~(0xc0); + m860.pcdir &= ~(0xc2); + m860.pcso |= (0xc0); + } + */ + + brg = m860_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ + /* at least 2 ports will be the same */ + + /* + * Set up SDMA + */ + m860.sdcr = 0x01; /* as recommended p 16-80, sec 16.10.2.1 MPC860UM/AD */ + + + m860.sicr &= ~(0xff << ((port-1) * 8)); + m860.sicr |= (brg << (3 + ((port-1) * 8))) | (brg << ((port-1) * 8)); + + /* + * Set up SMC1 parameter RAM common to all protocols + */ + if (port == 1) { + sccparms = (m860SCCparms_t*)&m860.scc1p; + sccregs = &m860.scc1; + } + else if (port == 2) { + sccparms = &m860.scc2p; + sccregs = &m860.scc2; + } + else if (port == 3) { + sccparms = &m860.scc3p; + sccregs = &m860.scc3; + } + else { + sccparms = &m860.scc4p; + sccregs = &m860.scc4; + } + + sccparms->rbase = (char *)RxBd[port+1] - (char *)&m860; + sccparms->tbase = (char *)TxBd[port+1] - (char *)&m860; + + if (port == 1) + M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC1); + else if (port == 2) + M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC2); + else if (port == 3) + M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC3); + else if (port == 4) + M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC4); + + sccparms->rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); + sccparms->tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); + sccparms->mrblr = RXBUFSIZE; + + sccparms->un.uart.max_idl = 10; + sccparms->un.uart.brklen = 0; + sccparms->un.uart.brkec = 0; + sccparms->un.uart.brkcr = 1; + + sccparms->un.uart.parec = 0; + sccparms->un.uart.frmec = 0; + sccparms->un.uart.nosec = 0; + + sccparms->un.uart.uaddr[0] = 0; + sccparms->un.uart.uaddr[1] = 0; + sccparms->un.uart.toseq = 0; + + sccparms->un.uart.character[0] = 0x8000; + sccparms->un.uart.character[1] = 0x8000; + sccparms->un.uart.character[2] = 0x8000; + sccparms->un.uart.character[3] = 0x8000; + sccparms->un.uart.character[4] = 0x8000; + sccparms->un.uart.character[5] = 0x8000; + sccparms->un.uart.character[6] = 0x8000; + sccparms->un.uart.character[7] = 0x8000; + + sccparms->un.uart.rccm = 0xc0ff; + + /* + * Set up the Receive Buffer Descriptor + */ + RxBd[port+1]->status = M860_BD_EMPTY | M860_BD_WRAP | + M860_BD_INTERRUPT; + RxBd[port+1]->length = 0; + RxBd[port+1]->buffer = malloc(RXBUFSIZE); + + /* + * Setup the Transmit Buffer Descriptor + */ + TxBd[port+1]->status = M860_BD_WRAP; + + /* + * Set up SCCx general and protocol-specific mode registers + */ + sccregs->scce = 0xffff; + sccregs->sccm = 0x0000; + sccregs->gsmr_h = 0x00000020; + sccregs->gsmr_l = 0x00028004; + sccregs->psmr = 0x3000; + sccregs->gsmr_l = 0x00028034; +} + +void +m860_smc_initialize (int port) /* port is the SMC number (i.e. 1 or 2) */ +{ + unsigned char brg; + + /* + * Allocate buffer descriptors + */ + RxBd[port-1] = M860AllocateBufferDescriptors (1); + TxBd[port-1] = M860AllocateBufferDescriptors (1); + + /* + * Configure port B pins to enable SMTXDx and SMRXDx pins + */ + m860.pbpar |= (0xC0 << ((port-1) * 4)); + m860.pbdir &= ~(0xC0 << ((port-1) * 4)); + m860.pbdir |= (0x01 << (port-1)); + m860.pbodr &= ~(0xC0 << ((port-1) * 4)); + m860.pbdat &= ~(0x01 << (port-1)); + + /* + * Set up BRG1 (9,600 baud) + */ + brg = m860_get_brg_clk(9600); /* 4 BRGs, 5 serial ports - hopefully */ + /* at least 2 ports will be the same */ + + /* + * Put SMC in NMSI mode, connect SMC to BRG + */ + m860.simode &= ~0x7000 << ((port-1) * 8); + m860.simode |= brg << (12 + ((port-1) * 8)); + + /* + * Set up SMC1 parameter RAM common to all protocols + */ + if (port == 1) { + m860.smc1p.rbase = (char *)RxBd[port-1] - (char *)&m860; + m860.smc1p.tbase = (char *)TxBd[port-1] - (char *)&m860; + m860.smc1p.rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); + m860.smc1p.tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); + m860.smc1p.mrblr = RXBUFSIZE; + + /* + * Set up SMC1 parameter RAM UART-specific parameters + */ + m860.smc1p.un.uart.max_idl = 10; + m860.smc1p.un.uart.brklen = 0; + m860.smc1p.un.uart.brkec = 0; + m860.smc1p.un.uart.brkcr = 0; + + } + else { + m860.smc2p.rbase = (char *)RxBd[port-1] - (char *)&m860; + m860.smc2p.tbase = (char *)TxBd[port-1] - (char *)&m860; + m860.smc2p.rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0); + m860.smc2p.tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0); + m860.smc2p.mrblr = RXBUFSIZE; + + /* + * Set up SMC2 parameter RAM UART-specific parameters + */ + m860.smc2p.un.uart.max_idl = 10; + m860.smc2p.un.uart.brklen = 0; + m860.smc2p.un.uart.brkec = 0; + m860.smc2p.un.uart.brkcr = 0; + } + + /* + * Set up the Receive Buffer Descriptor + */ + RxBd[port-1]->status = M860_BD_EMPTY | M860_BD_WRAP | + M860_BD_INTERRUPT; + RxBd[port-1]->length = 0; + RxBd[port+3]->buffer = malloc(RXBUFSIZE); + + /* + * Setup the Transmit Buffer Descriptor + */ + TxBd[port-1]->status = M860_BD_WRAP; + + /* + * Set up SMCx general and protocol-specific mode registers + */ + if (port == 1) { + m860.smc1.smce = ~0; /* Clear any pending events */ + m860.smc1.smcm = 0; /* Mask all interrupt/event sources */ + m860.smc1.smcmr = M860_SMCMR_CLEN(9) | M860_SMCMR_SM_UART; + + /* + * Send "Init parameters" command + */ + M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SMC1); + + /* + * Enable receiver and transmitter + */ + m860.smc1.smcmr |= M860_SMCMR_TEN | M860_SMCMR_REN; + } + else { + m860.smc2.smce = ~0; /* Clear any pending events */ + m860.smc2.smcm = 0; /* Mask all interrupt/event sources */ + m860.smc2.smcmr = M860_SMCMR_CLEN(9) | M860_SMCMR_SM_UART; + + /* + * Send "Init parameters" command + */ + M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SMC2); + + /* + * Enable receiver and transmitter + */ + m860.smc2.smcmr |= M860_SMCMR_TEN | M860_SMCMR_REN; + } +} + +int +m860_char_poll_read (int minor) +{ + unsigned char c; + rtems_unsigned32 level; + + _CPU_ISR_Disable(level); + if (RxBd[minor]->status & M860_BD_EMPTY) { + _CPU_ISR_Enable(level); + return -1; + } + c = ((char *)RxBd[minor]->buffer)[0]; + RxBd[minor]->status = M860_BD_EMPTY | M860_BD_WRAP; + _CPU_ISR_Enable(level); + return c; +} + +int +m860_char_poll_write (int minor, const char *buf, int len) +{ + while (len--) { + while (TxBd[minor]->status & M860_BD_READY) + continue; + txBuf[minor] = *buf++; + TxBd[minor]->buffer = &txBuf[minor]; + TxBd[minor]->length = 1; + TxBd[minor]->status = M860_BD_READY | M860_BD_WRAP; + } + return 0; +} + +/* + * Interrupt handler + */ +rtems_isr +m860_scc1_console_interrupt_handler (rtems_vector_number v) +{ + /* + * Buffer received? + */ + if ((m860.scc1.sccm & 0x1) && (m860.scc1.scce & 0x1)) { + m860.scc1.scce = 0x1; + /* m860.scc1.sccm &= ~0x1;*/ + + while ((RxBd[SCC1_MINOR]->status & M860_BD_EMPTY) == 0) { + rxBufListTail[SCC1_MINOR]->next = malloc(sizeof(Buf_t)); + if (rxBufListTail[SCC1_MINOR]->next) { + rxBufListTail[SCC1_MINOR] = rxBufListTail[SCC1_MINOR]->next; + rxBufListTail[SCC1_MINOR]->buf = RxBd[SCC1_MINOR]->buffer; + rxBufListTail[SCC1_MINOR]->len = RxBd[SCC1_MINOR]->length; + rxBufListTail[SCC1_MINOR]->pos = 0; + rxBufListTail[SCC1_MINOR]->next = 0; + + RxBd[SCC1_MINOR]->buffer = malloc(RXBUFSIZE); + } + RxBd[SCC1_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | + M860_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ +#if 0 + if (m860.smc1.smce & 0x2) { + m860.smc1.smce = 0x2; + if ((smcTxBd->status & M360_BD_READY) == 0) + rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); + } +#endif + m860.cisr = 1UL << 30; /* Clear SCC1 interrupt-in-service bit */ +} + +rtems_isr +m860_scc2_console_interrupt_handler (rtems_vector_number v) +{ + /* + * Buffer received? + */ + if ((m860.scc2.sccm & 0x1) && (m860.scc2.scce & 0x1)) { + m860.scc2.scce = 0x1; + /* m860.scc2.sccm &= ~0x1;*/ + + while ((RxBd[SCC2_MINOR]->status & M860_BD_EMPTY) == 0) { + rxBufListTail[SCC2_MINOR]->next = malloc(sizeof(Buf_t)); + if (rxBufListTail[SCC2_MINOR]->next) { + rxBufListTail[SCC2_MINOR] = rxBufListTail[SCC2_MINOR]->next; + rxBufListTail[SCC2_MINOR]->buf = RxBd[SCC2_MINOR]->buffer; + rxBufListTail[SCC2_MINOR]->len = RxBd[SCC2_MINOR]->length; + rxBufListTail[SCC2_MINOR]->pos = 0; + rxBufListTail[SCC2_MINOR]->next = 0; + + RxBd[SCC2_MINOR]->buffer = malloc(RXBUFSIZE); + } + RxBd[SCC2_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | + M860_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ +#if 0 + if (m860.smc1.smce & 0x2) { + m860.smc1.smce = 0x2; + if ((smcTxBd->status & M360_BD_READY) == 0) + rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); + } +#endif + m860.cisr = 1UL << 29; /* Clear SCC2 interrupt-in-service bit */ +} + +rtems_isr +m860_scc3_console_interrupt_handler (rtems_vector_number v) +{ + /* + * Buffer received? + */ + if ((m860.scc3.sccm & 0x1) && (m860.scc3.scce & 0x1)) { + m860.scc3.scce = 0x1; + /* m860.scc3.sccm &= ~0x1;*/ + + while ((RxBd[SCC3_MINOR]->status & M860_BD_EMPTY) == 0) { + rxBufListTail[SCC3_MINOR]->next = malloc(sizeof(Buf_t)); + if (rxBufListTail[SCC3_MINOR]->next) { + rxBufListTail[SCC3_MINOR] = rxBufListTail[SCC3_MINOR]->next; + rxBufListTail[SCC3_MINOR]->buf = RxBd[SCC3_MINOR]->buffer; + rxBufListTail[SCC3_MINOR]->len = RxBd[SCC3_MINOR]->length; + rxBufListTail[SCC3_MINOR]->pos = 0; + rxBufListTail[SCC3_MINOR]->next = 0; + + RxBd[SCC3_MINOR]->buffer = malloc(RXBUFSIZE); + } + RxBd[SCC3_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | + M860_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ +#if 0 + if (m860.smc1.smce & 0x2) { + m860.smc1.smce = 0x2; + if ((smcTxBd->status & M360_BD_READY) == 0) + rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); + } +#endif + m860.cisr = 1UL << 28; /* Clear SCC3 interrupt-in-service bit */ +} + +rtems_isr +m860_scc4_console_interrupt_handler (rtems_vector_number v) +{ + /* + * Buffer received? + */ + if ((m860.scc4.sccm & 0x1) && (m860.scc4.scce & 0x1)) { + m860.scc4.scce = 0x1; + /* m860.scc4.sccm &= ~0x1;*/ + + while ((RxBd[SCC4_MINOR]->status & M860_BD_EMPTY) == 0) { + rxBufListTail[SCC4_MINOR]->next = malloc(sizeof(Buf_t)); + if (rxBufListTail[SCC4_MINOR]->next) { + rxBufListTail[SCC4_MINOR] = rxBufListTail[SCC4_MINOR]->next; + rxBufListTail[SCC4_MINOR]->buf = RxBd[SCC4_MINOR]->buffer; + rxBufListTail[SCC4_MINOR]->len = RxBd[SCC4_MINOR]->length; + rxBufListTail[SCC4_MINOR]->pos = 0; + rxBufListTail[SCC4_MINOR]->next = 0; + + RxBd[SCC4_MINOR]->buffer = malloc(RXBUFSIZE); + } + RxBd[SCC4_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | + M860_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ +#if 0 + if (m860.smc1.smce & 0x2) { + m860.smc1.smce = 0x2; + if ((smcTxBd->status & M360_BD_READY) == 0) + rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); + } +#endif + m860.cisr = 1UL << 27; /* Clear SCC4 interrupt-in-service bit */ +} + +rtems_isr +m860_smc1_console_interrupt_handler (rtems_vector_number v) +{ + /* + * Buffer received? + */ + if (m860.smc1.smce & 0x1) { + m860.smc1.smce = 0x1; + /* m860.scc2.sccm &= ~0x1;*/ + + while ((RxBd[SMC1_MINOR]->status & M860_BD_EMPTY) == 0) { + rxBufListTail[SMC1_MINOR]->next = malloc(sizeof(Buf_t)); + if (rxBufListTail[SMC1_MINOR]->next) { + rxBufListTail[SMC1_MINOR] = rxBufListTail[SMC1_MINOR]->next; + rxBufListTail[SMC1_MINOR]->buf = RxBd[SMC1_MINOR]->buffer; + rxBufListTail[SMC1_MINOR]->len = RxBd[SMC1_MINOR]->length; + rxBufListTail[SMC1_MINOR]->pos = 0; + rxBufListTail[SMC1_MINOR]->next = 0; + + RxBd[SMC1_MINOR]->buffer = malloc(RXBUFSIZE); + } + RxBd[SMC1_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | + M860_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ +#if 0 + if (m860.smc1.smce & 0x2) { + m860.smc1.smce = 0x2; + if ((smcTxBd->status & M360_BD_READY) == 0) + rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); + } +#endif + m860.cisr = 1UL << 4; /* Clear SMC1 interrupt-in-service bit */ +} + +rtems_isr +m860_smc2_console_interrupt_handler (rtems_vector_number v) +{ + /* + * Buffer received? + */ + if (m860.smc2.smce & 0x1) { + m860.smc2.smce = 0x1; + + while ((RxBd[SMC2_MINOR]->status & M860_BD_EMPTY) == 0) { + rxBufListTail[SMC2_MINOR]->next = malloc(sizeof(Buf_t)); + if (rxBufListTail[SMC2_MINOR]->next) { + rxBufListTail[SMC2_MINOR] = rxBufListTail[SMC2_MINOR]->next; + rxBufListTail[SMC2_MINOR]->buf = RxBd[SMC2_MINOR]->buffer; + rxBufListTail[SMC2_MINOR]->len = RxBd[SMC2_MINOR]->length; + rxBufListTail[SMC2_MINOR]->pos = 0; + rxBufListTail[SMC2_MINOR]->next = 0; + + RxBd[SMC2_MINOR]->buffer = malloc(RXBUFSIZE); + } + RxBd[SMC2_MINOR]->status = M860_BD_EMPTY | M860_BD_WRAP | + M860_BD_INTERRUPT; + } + } + + /* + * Buffer transmitted? + */ +#if 0 + if (m860.smc1.smce & 0x2) { + m860.smc1.smce = 0x2; + if ((smcTxBd->status & M360_BD_READY) == 0) + rtems_termios_dequeue_characters (smc1ttyp, smcTxBd->length); + } +#endif + m860.cisr = 1UL << 3; /* Clear SMC2 interrupt-in-service bit */ +} + + +int +m860_buf_poll_read (int minor, char **buf) +{ + int len; + + if (RxBd[minor]->status & M860_BD_EMPTY) + return -1; + + RxBd[minor]->buffer = malloc(RXBUFSIZE); /* I hope this succeeds ... */ + len = RxBd[minor]->length; + RxBd[minor]->status = M860_BD_EMPTY | M860_BD_WRAP; + + return len; +} + +int +m860_buf_poll_write (int minor, char *buf, int len) +{ + static char *last_buf[6]; + + while (TxBd[minor]->status & M860_BD_READY) + continue; + if (last_buf[minor]) + free(last_buf[minor]); + last_buf[minor] = buf; + TxBd[minor]->buffer = buf; + TxBd[minor]->length = len; + TxBd[minor]->status = M860_BD_READY | M860_BD_WRAP; + return 0; +} + +/* + * This is needed in case we use TERMIOS + */ +void m860_console_reserve_resources(rtems_configuration_table *configuration) +{ + rtems_termios_reserve_resources (configuration, 1); +} + +void m860_console_initialize(void) +{ + int i; + + for (i=0; i < NIFACES; i++) { + rxBufList[i] = malloc(sizeof(Buf_t)); + rxBufListTail[i] = rxBufList[i]; + rxBufList[i]->buf = 0; + rxBufList[i]->len = 0; + rxBufList[i]->pos = 0; + rxBufList[i]->next = 0; + } +} + +rtems_device_driver m860_console_read(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg) +{ + rtems_libio_rw_args_t *rw_args; + char *buffer; + int maximum; + int count; + Buf_t *tmp_buf; + rtems_unsigned32 level; + + /* + * Set up interrupts + * FIXME: DANGER: WARNING: + * CICR and SIMASK must be set in any module that uses + * the CPM. Currently those are console-generic.c and + * network.c. If the registers are not set the same + * in both places, strange things may happen. + * If they are only set in one place, then an application + * that used the other module won't work correctly. + * Put this comment in each module that sets these 2 registers + */ + m860.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, + SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ + m860.simask |= M860_SIMASK_LVM1; + + rw_args = (rtems_libio_rw_args_t *) arg; + buffer = rw_args->buffer; + maximum = rw_args->count; + count = 0; + + while (count == 0) { + if (rxBufList[minor]->len) { + while ((count < maximum) && + (rxBufList[minor]->pos < rxBufList[minor]->len)) { + buffer[count++] = rxBufList[minor]->buf[rxBufList[minor]->pos++]; + } + _CPU_ISR_Disable(level); + if (rxBufList[minor]->pos == rxBufList[minor]->len) { + if (rxBufList[minor]->next) { + tmp_buf=rxBufList[minor]->next; + free (rxBufList[minor]->buf); + free (rxBufList[minor]); + rxBufList[minor]=tmp_buf; + } + else { + free(rxBufList[minor]->buf); + rxBufList[minor]->buf=0; + rxBufList[minor]->len=0; + rxBufList[minor]->pos=0; + } + } + _CPU_ISR_Enable(level); + } + else + if(rxBufList[minor]->next && !rxBufList[minor]->len) { + tmp_buf = rxBufList[minor]; + rxBufList[minor] = rxBufList[minor]->next; + free(tmp_buf); + } + /* sleep(1);*/ + } + rw_args->bytes_moved = count; + return (count >= 0) ? RTEMS_SUCCESSFUL : RTEMS_UNSATISFIED; +} + +rtems_device_driver m860_console_write(rtems_device_major_number major, + rtems_device_minor_number minor, + void *arg) +{ + int count; + int maximum; + rtems_libio_rw_args_t *rw_args; + char *in_buffer; + char *out_buffer; + int n; + + /* + * Set up interrupts + * FIXME: DANGER: WARNING: + * CICR and SIMASK must be set in any module that uses + * the CPM. Currently those are console-generic.c and + * network.c. If the registers are not set the same + * in both places, strange things may happen. + * If they are only set in one place, then an application + * that used the other module won't work correctly. + * Put this comment in each module that sets these 2 registers + */ +/* m860.cicr = 0x00e43e80; /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3, + SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */ +/* m860.simask |= M860_SIMASK_LVM1; */ + + rw_args = (rtems_libio_rw_args_t *) arg; + + in_buffer = rw_args->buffer; + maximum = rw_args->count; + + out_buffer = malloc(maximum*2); /* This is wasteful, but it won't */ + /* be too small */ + + if (!out_buffer) { + rw_args->bytes_moved = 0; + return RTEMS_NO_MEMORY; + } + n=0; + for (count = 0; count < maximum; count++) { + if ( in_buffer[ count ] == '\n') { + out_buffer[count + n] = '\r'; + n++; + } + out_buffer[count + n] = in_buffer[count]; + } + m860_buf_poll_write(minor, out_buffer, maximum+n); + rw_args->bytes_moved = maximum; + return RTEMS_SUCCESSFUL; +} + + +/* + * How to use the console. + * In your BSP, have the following functions: + * + * rtems_device_driver console_initialize(rtems_device_major_number major, + * rtems_device_minor_number minor, + * void *arg) + * rtems_device_driver console_open(rtems_device_major_number major, + * rtems_device_minor_number minor, + * void *arg) + * rtems_device_driver console_close(rtems_device_major_number major, + * rtems_device_minor_number minor, + * void *arg) + * rtems_device_driver console_read(rtems_device_major_number major, + * rtems_device_minor_number minor, + * void *arg) + * rtems_device_driver console_write(rtems_device_major_number major, + * rtems_device_minor_number minor, + * void *arg) + * rtems_device_driver console_control(rtems_device_major_number major, + * rtems_device_minor_number minor, + * void *arg) + * + */ diff --git a/c/src/lib/libcpu/powerpc/mpc860/include/Makefile.in b/c/src/lib/libcpu/powerpc/mpc860/include/Makefile.in new file mode 100644 index 0000000000..faff98bb28 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/include/Makefile.in @@ -0,0 +1,29 @@ +# +# $Id$ +# +# Install any include files needed by libcpu. +# Mainly this just means bsp.h which would normally be installed +# after libcpu is built. +# This is a bit of a hack. + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +H_FILES = $(wildcard $(srcdir)/*.h) +SRCS=$(H_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +all: install + +install: + test -d $(PROJECT_INCLUDE)/mpc860 || $(MKDIR) $(PROJECT_INCLUDE)/mpc860 + $(INSTALL) -m 444 $(H_FILES) $(PROJECT_INCLUDE)/mpc860 + +all: FORCEIT + cd ../../../../libbsp/$(RTEMS_CPU)/$(RTEMS_BSP)/include; $(MAKE) all + diff --git a/c/src/lib/libcpu/powerpc/mpc860/include/console.h b/c/src/lib/libcpu/powerpc/mpc860/include/console.h new file mode 100644 index 0000000000..4ccc642a0d --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/include/console.h @@ -0,0 +1,44 @@ +#ifndef _M860_CONSOLE_H_ +#define _M860_CONSOLE_H_ + +#include + +int m860_smc_set_attributes(int, const struct termios*); +int m860_scc_set_attributes(int, const struct termios*); +void m860_scc_initialize(int); +void m860_smc_initialize(int); +int m860_char_poll_read(int); +int m860_char_poll_write(int, const char*, int); +rtems_isr m860_scc1_console_interrupt_handler(rtems_vector_number); +rtems_isr m860_scc2_console_interrupt_handler(rtems_vector_number); +rtems_isr m860_scc3_console_interrupt_handler(rtems_vector_number); +rtems_isr m860_scc4_console_interrupt_handler(rtems_vector_number); +rtems_isr m860_smc1_console_interrupt_handler(rtems_vector_number); +rtems_isr m860_smc2_console_interrupt_handler(rtems_vector_number); +int m860_buf_poll_read(int, char**); +int m860_buf_poll_write(int, char*, int); +void m860_console_initialize(void); +rtems_device_driver m860_console_read(rtems_device_major_number, + rtems_device_minor_number, + void*); +rtems_device_driver m860_console_write(rtems_device_major_number, + rtems_device_minor_number, + void*); + + +typedef struct Buf_t_ { + struct Buf_t_ *next; + volatile char *buf; + volatile int len; + int pos; +} Buf_t; + +#define SMC1_MINOR 0 +#define SMC2_MINOR 1 +#define SCC1_MINOR 2 +#define SCC2_MINOR 3 +#define SCC3_MINOR 4 +#define SCC4_MINOR 5 + + +#endif diff --git a/c/src/lib/libcpu/powerpc/mpc860/timer/Makefile.in b/c/src/lib/libcpu/powerpc/mpc860/timer/Makefile.in new file mode 100644 index 0000000000..2c423f2a5a --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/timer/Makefile.in @@ -0,0 +1,60 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/timer.rel + +# C source names, if any, go here -- minus the .c +C_PIECES=timer +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES= +S_FILES=$(S_PIECES:%=%.s) +S_O_FILES=$(S_FILES:%.s=${ARCH}/%.o) + +SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += $(CFLAGS_OS_V) + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by +# libbsp/hppa/BSP/wrapup/Makefile +install: all diff --git a/c/src/lib/libcpu/powerpc/mpc860/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc860/timer/timer.c new file mode 100644 index 0000000000..c97439f2d6 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/timer/timer.c @@ -0,0 +1,104 @@ +/* timer.c + * + * This file manages the interval timer on the PowerPC MPC860. + * NOTE: This is not the PIT, but rather the RTEMS interval + * timer + * We shall use the bottom 32 bits of the timebase register, + * + * The following was in the 403 version of this file. I don't + * know what it means. JTM 5/19/98 + * NOTE: It is important that the timer start/stop overhead be + * determined when porting or modifying this code. + * + * Author: Jay Monkman (jmonkman@frasca.com) + * Copywright (C) 1998 by Frasca International, Inc. + * + * Derived from c/src/lib/libcpu/ppc/ppc403/timer/timer.c: + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * Derived from c/src/lib/libcpu/hppa1_1/timer/timer.c: + * + * COPYRIGHT (c) 1989-1998. + * On-Line Applications Research Corporation (OAR). + * Copyright assigned to U.S. Government, 1994. + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.OARcorp.com/rtems/license.html. + * + * $Id$ + */ + +#include +#include +#include + +extern rtems_cpu_table Cpu_table; /* owned by BSP */ + +static volatile rtems_unsigned32 Timer_starting; +static rtems_boolean Timer_driver_Find_average_overhead; + +/* + * This is so small that this code will be reproduced where needed. + */ +static inline rtems_unsigned32 get_itimer(void) +{ + rtems_unsigned32 ret; + + asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */ + + return ret; +} + +void Timer_initialize(void) +{ + /* set interrupt level and enable timebase. This should never */ + /* generate an interrupt however. */ + m860.tbscr |= M860_TBSCR_TBIRQ(4) | M860_TBSCR_TBE; + + Timer_starting = get_itimer(); +} + +int Read_timer(void) +{ + rtems_unsigned32 clicks; + rtems_unsigned32 total; + + clicks = get_itimer(); + + total = clicks - Timer_starting; + + if ( Timer_driver_Find_average_overhead == 1 ) + return total; /* in XXX microsecond units */ + + else { + if ( total < Cpu_table.timer_least_valid ) { + return 0; /* below timer resolution */ + } + return (total - Cpu_table.timer_average_overhead); + } +} + +rtems_status_code Empty_function(void) +{ + return RTEMS_SUCCESSFUL; +} + +void Set_find_average_overhead(rtems_boolean find_flag) +{ + Timer_driver_Find_average_overhead = find_flag; +} diff --git a/c/src/lib/libcpu/powerpc/mpc860/vectors/Makefile.in b/c/src/lib/libcpu/powerpc/mpc860/vectors/Makefile.in new file mode 100644 index 0000000000..9ca5b8d2cf --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/vectors/Makefile.in @@ -0,0 +1,59 @@ +# +# $Id$ +# + +@SET_MAKE@ +srcdir = @srcdir@ +VPATH = @srcdir@ +RTEMS_ROOT = @top_srcdir@ +PROJECT_ROOT = @PROJECT_ROOT@ + +PGM=${ARCH}/vectors.rel + +# C source names, if any, go here -- minus the .c +C_PIECES= +C_FILES=$(C_PIECES:%=%.c) +C_O_FILES=$(C_PIECES:%=${ARCH}/%.o) + +H_FILES= + +# Assembly source names, if any, go here -- minus the .s +S_PIECES=vectors align_h +S_FILES=$(S_PIECES:%=%.S) +S_O_FILES=$(S_FILES:%.S=${ARCH}/%.o) + +SRCS=$(C_FILES) $(CC_FILES) $(H_FILES) $(S_FILES) +OBJS=$(C_O_FILES) $(CC_O_FILES) $(S_O_FILES) + +include $(RTEMS_ROOT)/make/custom/$(RTEMS_BSP).cfg +include $(RTEMS_ROOT)/make/leaf.cfg + +# +# (OPTIONAL) Add local stuff here using += +# + +DEFINES += +CPPFLAGS += +CFLAGS += + +LD_PATHS += +LD_LIBS += +LDFLAGS += + +# +# Add your list of files to delete here. The config files +# already know how to delete some stuff, so you may want +# to just run 'make clean' first to see what gets missed. +# 'make clobber' already includes 'make clean' +# + +CLEAN_ADDITIONS += +CLOBBER_ADDITIONS += + +${PGM}: ${SRCS} ${OBJS} + $(make-rel) + +all: ${ARCH} $(SRCS) $(PGM) + +# the .rel file built here will be put into libbsp.a by ../wrapup/Makefile +install: all diff --git a/c/src/lib/libcpu/powerpc/mpc860/vectors/README b/c/src/lib/libcpu/powerpc/mpc860/vectors/README new file mode 100644 index 0000000000..4081ae2525 --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/vectors/README @@ -0,0 +1,25 @@ +# +# $Id$ +# + +The location of the vectors file object is critical. + +From the comments at the head of vectors.s: + + The issue with this file is getting it loaded at the right place. + The first vector MUST be at address 0x????0100. + How this is achieved is dependant on the tool chain. + + However the basic mechanism for ELF assemblers is to create a + section called ".vectors", which will be loaded to an address + between 0x????0000 and 0x????0100 (inclusive) via a link script. + + The basic mechanism for XCOFF assemblers is to place it in the + normal text section, and arrange for this file to be located + at an appropriate position on the linker command line. + + The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the + offset from 0x????0000 to the first location in the file. This + will usually be 0x0000 or 0x0100. + +Andrew Bray 18/8/1995 diff --git a/c/src/lib/libcpu/powerpc/mpc860/vectors/align_h.S b/c/src/lib/libcpu/powerpc/mpc860/vectors/align_h.S new file mode 100644 index 0000000000..9a785e347d --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/vectors/align_h.S @@ -0,0 +1,435 @@ +/* align_h.s 1.1 - 95/12/04 + * + * This file contains the assembly code for the PowerPC 403 + * alignment exception handler for RTEMS. + * + * Based upon IBM provided code with the following release: + * + * This source code has been made available to you by IBM on an AS-IS + * basis. Anyone receiving this source is licensed under IBM + * copyrights to use it in any way he or she deems fit, including + * copying it, modifying it, compiling it, and redistributing it either + * with or without modifications. No license under IBM patents or + * patent applications is to be implied by the copyright license. + * + * Any user of this software should understand that IBM cannot provide + * technical support for this software and will not be responsible for + * any consequences resulting from the use of this software. + * + * Any person who transfers this source code or any derivative work + * must include the IBM copyright notice, this paragraph, and the + * preceding two paragraphs in the transferred software. + * + * COPYRIGHT I B M CORPORATION 1995 + * LICENSED MATERIAL - PROGRAM PROPERTY OF I B M + * + * Modifications: + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + * $Id$ + */ + +#include "asm.h" +/*#include "bsp.h"*/ +#define ALIGN_REGS 0x0140 + +.set CACHE_SIZE,16 # cache line size of 32 bytes +.set CACHE_SIZE_L2,4 # cache line size, log 2 + +.set Open_gpr0,0 +.set Open_gpr1,4 +.set Open_gpr2,8 +.set Open_gpr3,12 +.set Open_gpr4,16 +.set Open_gpr5,20 +.set Open_gpr6,24 +.set Open_gpr7,28 +.set Open_gpr8,32 +.set Open_gpr9,36 +.set Open_gpr10,40 +.set Open_gpr11,44 +.set Open_gpr12,48 +.set Open_gpr13,52 +.set Open_gpr14,56 +.set Open_gpr15,60 +.set Open_gpr16,64 +.set Open_gpr17,68 +.set Open_gpr18,72 +.set Open_gpr19,76 +.set Open_gpr20,80 +.set Open_gpr21,84 +.set Open_gpr22,88 +.set Open_gpr23,92 +.set Open_gpr24,96 +.set Open_gpr25,100 +.set Open_gpr26,104 +.set Open_gpr27,108 +.set Open_gpr28,112 +.set Open_gpr29,116 +.set Open_gpr30,120 +.set Open_gpr31,124 +.set Open_xer,128 +.set Open_lr,132 +.set Open_ctr,136 +.set Open_cr,140 +.set Open_srr2,144 +.set Open_srr3,148 +.set Open_srr0,152 +.set Open_srr1,156 + + +/* + * This code makes several assumptions for processing efficiency + * * General purpose registers are continuous in the image, beginning with + * Open_gpr0 + * * Hash table is highly dependent on opcodes - opcode changes *will* + * require rework of the instruction decode mechanism. + */ + + .text + .globl align_h + + .align CACHE_SIZE_L2 +align_h: + /*----------------------------------------------------------------------- + * Store GPRs in Open Reg save area + * Set up r2 as base reg, r1 pointing to Open Reg save area + *----------------------------------------------------------------------*/ + stmw r0,ALIGN_REGS(r0) + li r1,ALIGN_REGS + /*----------------------------------------------------------------------- + * Store special purpose registers in reg save area + *----------------------------------------------------------------------*/ + mfxer r7 + mflr r8 + mfcr r9 + mfctr r10 + stw r7,Open_xer(r1) + stw r8,Open_lr(r1) + stw r9,Open_cr(r1) + stw r10,Open_ctr(r1) + mfspr r7, srr2 /* SRR 2 */ + mfspr r8, srr3 /* SRR 3 */ + mfspr r9, srr0 /* SRR 0 */ + mfspr r10, srr1 /* SRR 1 */ + stw r7,Open_srr2(r1) + stw r8,Open_srr3(r1) + stw r9,Open_srr0(r1) + stw r10,Open_srr1(r1) + +/* Set up common registers */ + mfspr r5, dear /* DEAR: R5 is data exception address */ + lwz r9,Open_srr0(r1) /* get faulting instruction */ + addi r7,r9,4 /* bump instruction */ + stw r7,Open_srr0(r1) /* restore to image */ + lwz r9, 0(r9) /* retrieve actual instruction */ + rlwinm r6,r9,18,25,29 /* r6 is RA * 4 field from instruction */ + rlwinm r7,r9,6,26,31 /* r7 is primary opcode */ + bl ref_point /* establish addressibility */ +ref_point: + mflr r11 /* r11 is the anchor point for ref_point */ + addi r10, r7, -31 /* r10 = r7 - 31 */ + rlwinm r10,r10,2,2,31 /* r10 *= 4 */ + add r10, r10, r11 /* r10 += anchor point */ + lwz r10, primary_jt-ref_point(r10) + mtlr r10 + rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ + la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ + blr +primary_jt: + .long xform + .long lwz + .long lwzu + .long 0 + .long 0 + .long stw + .long stwu + .long 0 + .long 0 + .long lhz + .long lhzu + .long lha + .long lhau + .long sth + .long sthu + .long lmw + .long stmw +/* + * handlers + */ +/* + * xform instructions require an additional decode. Fortunately, a relatively + * simple hash step breaks the instructions out with no collisions + */ +xform: + rlwinm r7,r9,31,22,31 /* r7 is secondary opcode */ + rlwinm r10,r7,27,5,31 /* r10 = r7 >> 5 */ + add r10,r7,r10 /* r10 = r7 + r10 */ + rlwinm r10,r10,2,25,29 /* r10 = (r10 & 0x1F) * 4 */ + add r10,r10,r11 /* r10 += anchor point */ + lwz r10, secondary_ht-ref_point(r10) + mtlr r10 + la r7,Open_gpr0(r1) /* r7 is address of GPR 0 in list */ + rlwinm r8,r9,13,25,29 /* r8 is RD * 4 */ + blrl + +secondary_ht: + .long lhzux /* b 0 0x137 */ + .long lhax /* b 1 0x157 */ + .long lhaux /* b 2 0x177 */ + .long sthx /* b 3 0x197 */ + .long sthux /* b 4 0x1b7 */ + .long 0 /* b 5 */ + .long lwbrx /* b 6 0x216 */ + .long 0 /* b 7 */ + .long 0 /* b 8 */ + .long 0 /* b 9 */ + .long stwbrx /* b A 0x296 */ + .long 0 /* b B */ + .long 0 /* b C */ + .long 0 /* b D */ + .long lhbrx /* b E 0x316 */ + .long 0 /* b F */ + .long 0 /* b 10 */ + .long 0 /* b 11 */ + .long sthbrx /* b 12 0x396 */ + .long 0 /* b 13 */ + .long lwarx /* b 14 0x014 */ + .long dcbz /* b 15 0x3f6 */ + .long 0 /* b 16 */ + .long lwzx /* b 17 0x017 */ + .long lwzux /* b 18 0x037 */ + .long 0 /* b 19 */ + .long stwcx /* b 1A 0x096 */ + .long stwx /* b 1B 0x097 */ + .long stwux /* b 1C 0x0B7 */ + .long 0 /* b 1D */ + .long 0 /* b 1E */ + .long lhzx /* b 1F 0x117 */ + +/* + * for all handlers + * r4 - Addressability to interrupt context + * r5 - DEAR address (faulting data address) + * r6 - RA field * 4 + * r7 - Address of GPR 0 in image + * r8 - RD field * 4 + * r9 - Failing instruction + */ + +/* Load halfword algebraic with update */ +lhau: +/* Load halfword algebraic with update indexed */ +lhaux: + stwx r5,r7,r6 /* update RA with effective addr */ + +/* Load halfword algebraic */ +lha: +/* Load halfword algebraic indexed */ +lhax: + lswi r10,r5,2 /* load two bytes into r10 */ + srawi r10,r10,16 /* shift right 2 bytes, extending sign */ + stwx r10,r7,r8 /* update reg image */ + b align_complete /* return */ + +/* Load Half Word Byte-Reversed Indexed */ +lhbrx: + lswi r10,r5,2 /* load two bytes from DEAR into r10 */ + rlwinm r10,r10,0,0,15 /* mask off lower 2 bytes */ + stwbrx r10,r7,r8 /* store reversed in reg image */ + b align_complete /* return */ + +/* Load Half Word and Zero with Update */ +lhzu: +/* Load Half Word and Zero with Update Indexed */ +lhzux: + stwx r5,r7,r6 /* update RA with effective addr */ + +/* Load Half Word and Zero */ +lhz: +/* Load Half Word and Zero Indexed */ +lhzx: + lswi r10,r5,2 /* load two bytes from DEAR into r10 */ + rlwinm r10,r10,16,16,31 /* shift right 2 bytes, with zero fill */ + stwx r10,r7,r8 /* update reg image */ + b align_complete /* return */ + +/* + * Load Multiple Word + */ +lmw: + lwzx r9,r6,r7 /* R9 contains saved value of RA */ + addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ + rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ + subfic r8,r8,32 /* r8 is reg count to load */ + mtctr r8 /* load counter */ + addi r8,r8,-1 /* r8-- */ + rlwinm r8,r8,2,2,31 /* r8 *= 4 */ + add r5,r5,r8 /* update DEAR to point to last reg */ +lwmloop: + lswi r11,r5,4 /* load r11 with 4 bytes from DEAR */ + stwu r11,-4(r10) /* load image and decrement pointer */ + addi r5,r5,-4 /* decrement effective address */ + bdnz lwmloop + stwx r9,r6,r7 /* restore RA (in case it was trashed) */ + b align_complete /* return */ + +/* + * Load Word and Reserve Indexed + */ +lwarx: + lswi r10,r5,4 /* load four bytes from DEAR into r10 */ + stwx r10,r7,r8 /* update reg image */ + rlwinm r5,r5,0,0,29 /* Word align address */ + lwarx r10,0,r5 /* Set reservation */ + b align_complete /* return */ + +/* + * Load Word Byte-Reversed Indexed + */ +lwbrx: + lswi r10,r5,4 /* load four bytes from DEAR into r10 */ + stwbrx r10,r7,r8 /* store reversed in reg image */ + b align_complete /* return */ + +/* Load Word and Zero with Update */ +lwzu: +/* Load Word and Zero with Update Indexed */ +lwzux: + stwx r5,r7,r6 /* update RA with effective addr */ + +/* Load Word and Zero */ +lwz: +/* Load Word and Zero Indexed */ +lwzx: + lswi r10,r5,4 /* load four bytes from DEAR into r10 */ + stwx r10,r7,r8 /* update reg image */ + b align_complete /* return */ + +/* Store instructions */ + +/* */ +/* Store Half Word and Update */ +sthu: +/* Store Half Word and Update Indexed */ +sthux: + stwx r5,r7,r6 /* Update RA with effective address */ + +/* Store Half Word */ +sth: +/* Store Half Word Indexed */ +sthx: + lwzx r10,r8,r7 /* retrieve source register value */ + rlwinm r10,r10,16,0,15 /* move two bytes to high end of reg */ + stswi r10,r5,2 /* store bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Half Word Byte-Reversed Indexed */ +sthbrx: + lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ + stswi r10,r5,2 /* move two bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Multiple Word */ +stmw: + addi r10,r7,32*4 /* r10 points to r31 in image + 4 */ + rlwinm r8,r8,30,2,31 /* r8 >>= 2 (recovers RT) */ + subfic r8,r8,32 /* r8 is reg count to load */ + mtctr r8 /* load counter */ + addi r8,r8,-1 /* r8-- */ + rlwinm r8,r8,2,2,31 /* r8 *= 4 */ + add r5,r5,r8 /* update DEAR to point to last reg */ +stmloop: + lwzu r11,-4(r10) /* get register value */ + stswi r11,r5,4 /* output to DEAR address */ + addi r5,r5,-4 /* decrement effective address */ + bdnz stmloop + b align_complete /* return */ + +/* */ +/* Store Word and Update */ +stwu: +/* Store Word and Update Indexed */ +stwux: + stwx r5,r7,r6 /* Update RA with effective address */ + +/* Store Word */ +stw: +/* Store Word Indexed */ +stwx: + lwzx r10,r8,r7 /* retrieve source register value */ + stswi r10,r5,4 /* store bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Word Byte-Reversed Indexed */ +stwbrx: + lwbrx r10,r8,r7 /* retrieve src reg value byte reversed */ + stswi r10,r5,4 /* move two bytes to DEAR address */ + b align_complete /* return */ + +/* */ +/* Store Word Conditional Indexed */ +stwcx: + rlwinm r10,r5,0,0,29 /* r10 = word aligned DEAR */ + lwz r11,0(r10) /* save original value of store */ + stwcx. r11,r0,r10 /* attempt store to address */ + bne stwcx_moveon /* store failed, move on */ + stw r11,0(r10) /* repair damage */ + lwzx r9,r7,r8 /* get register value */ + stswi r10,r5,4 /* store bytes to DEAR address */ +stwcx_moveon: + mfcr r11 /* get condition reg */ + lwz r9,Open_cr(r1) /* get condition reg image */ + rlwimi r9,r11,0,0,2 /* insert 3 CR bits into cr image */ + lwz r11,Open_xer(r1) /* get XER reg */ + rlwimi r9,r11,29,2,2 /* insert XER SO bit into cr image */ + stw r9,Open_cr(r1) /* store cr image */ + b align_complete /* return */ + +/* */ +/* Data Cache Block Zero */ +dcbz: + rlwinm r5,r5,0,0,31-CACHE_SIZE_L2 + /* get address to nearest Cache line */ + addi r5,r5,-4 /* adjust by a word */ + addi r10,r0,CACHE_SIZE/4 /* set counter value */ + mtctr r10 + addi r11,r0,0 /* r11 = 0 */ +dcbz_loop: + stwu r11,4(r5) /* store a word and update EA */ + bdnz dcbz_loop + b align_complete /* return */ + +align_complete: + /*----------------------------------------------------------------------- + * Restore regs and return from the interrupt + *----------------------------------------------------------------------*/ + lmw r24,Open_xer+ALIGN_REGS(r0) + mtxer r24 + mtlr r25 + mtctr r26 + mtcrf 0xFF, r27 + mtspr srr2, r28 /* SRR 2 */ + mtspr srr3, r29 /* SRR 3 */ + mtspr srr0, r30 /* SRR 0 */ + mtspr srr1, r31 /* SRR 1 */ + lmw r1,Open_gpr1+ALIGN_REGS(r0) + lwz r0,Open_gpr0+ALIGN_REGS(r0) + rfi diff --git a/c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S b/c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S new file mode 100644 index 0000000000..de3739f41a --- /dev/null +++ b/c/src/lib/libcpu/powerpc/mpc860/vectors/vectors.S @@ -0,0 +1,952 @@ +/* vectors.s 1.1 - 95/12/04 + * + * This file contains the assembly code for the PowerPC MPC860 + * interrupt veneers for RTEMS. + * + * Author: Jay Monkman (jmonkman@frasca.com) + * + * Copyright (C) 1998 by Frasca International, Inc. + * + * Derived from c/src/lib/libcpu/ppc/ppc403/vectors/vectors.s: + * + * Author: Andrew Bray + * + * COPYRIGHT (c) 1995 by i-cubed ltd. + * + * To anyone who acknowledges that this file is provided "AS IS" + * without any express or implied warranty: + * permission to use, copy, modify, and distribute this file + * for any purpose is hereby granted without fee, provided that + * the above copyright notice and this notice appears in all + * copies, and that the name of i-cubed limited not be used in + * advertising or publicity pertaining to distribution of the + * software without specific, written prior permission. + * i-cubed limited makes no representations about the suitability + * of this software for any purpose. + * + */ + +/* + * The issue with this file is getting it loaded at the right place. + * The first vector MUST be at address 0x????0100. + * How this is achieved is dependant on the tool chain. + * + * However the basic mechanism for ELF assemblers is to create a + * section called ".vectors", which will be loaded to an address + * between 0x????0000 and 0x????0100 (inclusive) via a link script. + * + * The basic mechanism for XCOFF assemblers is to place it in the + * normal text section, and arrange for this file to be located + * at an appropriate position on the linker command line. + * + * The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the + * offset from 0x????0000 to the first location in the file. This + * will be either 0x0000 or 0xfff0. + * + * $Id$ + */ + +#include "asm.h" +#include + +#ifndef PPC_VECTOR_FILE_BASE +#error "PPC_VECTOR_FILE_BASE is not defined." +#endif + + /* Where this file will be loaded */ + .set file_base, PPC_VECTOR_FILE_BASE + + /* Offset to store reg 0 */ + + .set IP_LINK, 0 +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) + .set IP_0, (IP_LINK + 56) +#else + .set IP_0, (IP_LINK + 8) +#endif + .set IP_2, (IP_0 + 4) + + .set IP_3, (IP_2 + 4) + .set IP_4, (IP_3 + 4) + .set IP_5, (IP_4 + 4) + .set IP_6, (IP_5 + 4) + + .set IP_7, (IP_6 + 4) + .set IP_8, (IP_7 + 4) + .set IP_9, (IP_8 + 4) + .set IP_10, (IP_9 + 4) + + .set IP_11, (IP_10 + 4) + .set IP_12, (IP_11 + 4) + .set IP_13, (IP_12 + 4) + .set IP_28, (IP_13 + 4) + + .set IP_29, (IP_28 + 4) + .set IP_30, (IP_29 + 4) + .set IP_31, (IP_30 + 4) + .set IP_CR, (IP_31 + 4) + + .set IP_CTR, (IP_CR + 4) + .set IP_XER, (IP_CTR + 4) + .set IP_LR, (IP_XER + 4) + .set IP_PC, (IP_LR + 4) + + .set IP_MSR, (IP_PC + 4) + + .set IP_END, (IP_MSR + 16) + + /* Vector offsets */ + .set begin_vector, 0x0000 + .set reset_vector, 0x0100 + .set mach_vector, 0x0200 + .set dsi_vector, 0x0300 + .set isi_vector, 0x0400 + .set ext_vector, 0x0500 + .set align_vector, 0x0600 + .set prog_vector, 0x0700 + .set float_vector, 0x0800 + .set dec_vector, 0x0900 + .set sys_vector, 0x0C00 + .set trace_vector, 0x0d00 + .set syscall_vector, 0x0c00 + .set fpassist_vector, 0x0e00 + .set software_vector, 0x1000 + .set itlbm_vector, 0x1100 + .set dtlbm_vector, 0x1200 + .set itlbe_vector, 0x1300 + .set dtlbe_vector, 0x1400 + .set databkpt_vector, 0x1c00 + .set insbkpt_vector, 0x1d00 + .set perbkpt_vector, 0x1e00 + .set dev_vector, 0x1f00 + .set siu_vector, 0x2000 + .set cpm_vector, 0x2600 + +/* Go to the right section */ +#if PPC_ASM == PPC_ASM_ELF + .section .vectors,"awx",@progbits +#elif PPC_ASM == PPC_ASM_XCOFF + .csect .text[PR] +#endif + + PUBLIC_VAR (__vectors) +SYM (__vectors): + +/* Critical error handling */ + .org reset_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_SYSTEM_RESET + b PROC (_ISR_Handler) + +/* Machine check exception */ + .org mach_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_MCHECK + b PROC (_ISR_Handler) + +/* Protection exception */ + .org dsi_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_PROTECT + b PROC (_ISR_Handler) + +/* Instruction Storage exception */ + .org isi_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_ISI + b PROC (_ISR_Handler) + +/* External interrupt */ +/* When an external interrupt occurs, we must find out what caused it */ +/* before calling the RTEMS handler. First we use SIVEC to decide */ +/* what signalled the interrupt to the SIU. */ + .org ext_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + stw r9, IP_9(r1) /* r9 will be restored in the next level */ + stw r10, IP_10(r1) + + lis r9, m860@ha + addi r9, r9, m860@l + lbz r10, 0x1c(r9) /* SIVEC */ + rlwinm r10, r10, 4, 0, 27 /* each psuedo vector will have */ + /* room for 16 instructions */ + addis r10, r10, siu_vectors@ha + addi r10, r10, siu_vectors@l + mflr r0 + mtlr r10 + lwz r10, IP_10(r1) + blr + +/* Align exception */ + .org align_vector - file_base + .extern align_h + b align_h + +/* Program exception */ + .org prog_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_PROGRAM + b PROC (_ISR_Handler) + +/* Float exception */ + .org float_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_NOFP + b PROC (_ISR_Handler) + +/* Decrementer exception */ + .org dec_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_PROGRAM + b PROC (_ISR_Handler) + +/* System call */ + .org sys_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_SCALL + b PROC (_ISR_Handler) + +/* Trace interrupt */ + .org trace_vector - file_base +#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27) +#if (PPC_HAS_FPU) + stwu r1, -(20*4 + 18*8 + IP_END)(r1) +#else + stwu r1, -(20*4 + IP_END)(r1) +#endif +#else + stwu r1, -(IP_END)(r1) +#endif + stw r0, IP_0(r1) + + li r0, PPC_IRQ_TRACE + b PROC (_ISR_Handler) + + .org itlbm_vector - file_base +itlbm_vectors: + mfspr r2, 784 /* MI_CTR */ + mfspr r3, 792 /* MD_CTR */ + mfspr r4, 787 /* MI_EPN */ + mfspr r5, 789 /* MI_TWC */ + mfspr r6, 797 /* MD_TWC */ + mfspr r7, 789 /* MI_TWC */ + mfspr r8, 790 /* MI_RPN */ + mfspr r9, 798 /* MD_RPN */ + mfspr r10, 796 /* M_TWB */ + mfspr r11, 793 /* M_CASID */ + mfspr r12, 786 /* MI_AP */ + mfspr r13, 794 /* MD_AP */ + mfspr r14, 799 /* M_TW */ + mfspr r15, 816 /* MI_CAM */ + mfspr r16, 817 /* MI_RAM0 */ + mfspr r17, 818 /* MI_RAM1 */ + mfspr r18, 824 /* MD_CAM */ + mfspr r19, 825 /* M_RAM0 */ + mfspr r20, 826 /* M_RAM1 */ + .long 0 + + .org dtlbm_vector - file_base +dtlbm_vectors: + mfspr r1, 0x1a + mfspr r2, 784 /* MI_CTR */ + mfspr r3, 792 /* MD_CTR */ + lis r3, 0x400 + mtspr 792, r3 + mfspr r4, 787 /* MI_EPN */ + mfspr r5, 789 /* MI_TWC */ + mfspr r6, 797 /* MD_TWC */ + mfspr r7, 789 /* MI_TWC */ + mfspr r8, 790 /* MI_RPN */ + mfspr r9, 798 /* MD_RPN */ + mfspr r10, 796 /* M_TWB */ + mfspr r11, 793 /* M_CASID */ + mfspr r12, 786 /* MI_AP */ + mfspr r13, 794 /* MD_AP */ + mfspr r14, 799 /* M_TW */ + mfspr r15, 816 /* MI_CAM */ + mfspr r16, 817 /* MI_RAM0 */ + mfspr r17, 818 /* MI_RAM1 */ + mtspr 824, r18 + mfspr r18, 824 /* MD_CAM */ + mfspr r19, 825 /* M_RAM0 */ + mfspr r20, 826 /* M_RAM1 */ + .long 0 + + .org itlbe_vector - file_base +itlbe_vectors: + mfspr r2, 784 /* MI_CTR */ + mfspr r3, 792 /* MD_CTR */ + mfspr r4, 787 /* MI_EPN */ + mfspr r5, 789 /* MI_TWC */ + mfspr r6, 797 /* MD_TWC */ + mfspr r7, 789 /* MI_TWC */ + mfspr r8, 790 /* MI_RPN */ + mfspr r9, 798 /* MD_RPN */ + mfspr r10, 796 /* M_TWB */ + mfspr r11, 793 /* M_CASID */ + mfspr r12, 786 /* MI_AP */ + mfspr r13, 794 /* MD_AP */ + mfspr r14, 799 /* M_TW */ + mfspr r15, 816 /* MI_CAM */ + mfspr r16, 817 /* MI_RAM0 */ + mfspr r17, 818 /* MI_RAM1 */ + mfspr r18, 824 /* MD_CAM */ + mfspr r19, 825 /* M_RAM0 */ + mfspr r20, 826 /* M_RAM1 */ + .long 0 + + .org dtlbe_vector - file_base +dtlbe_vectors: + mfspr r2, 784 /* MI_CTR */ + mfspr r3, 792 /* MD_CTR */ + mfspr r4, 787 /* MI_EPN */ + mfspr r5, 789 /* MI_TWC */ + mfspr r6, 797 /* MD_TWC */ + mfspr r7, 789 /* MI_TWC */ + mfspr r8, 790 /* MI_RPN */ + mfspr r9, 798 /* MD_RPN */ + mfspr r10, 796 /* M_TWB */ + mfspr r11, 793 /* M_CASID */ + mfspr r12, 786 /* MI_AP */ + mfspr r13, 794 /* MD_AP */ + mfspr r14, 799 /* M_TW */ + mfspr r15, 816 /* MI_CAM */ + mfspr r16, 817 /* MI_RAM0 */ + mfspr r17, 818 /* MI_RAM1 */ + mfspr r18, 824 /* MD_CAM */ + mfspr r19, 825 /* M_RAM0 */ + mfspr r20, 826 /* M_RAM1 */ + .long 0 + + + +/* Now we look at what signaled the interrupt to the SIU. */ +/* I needed to do this in order to decode the CPM interrupts before */ +/* calling _ISR_Handler */ + +/* *IRQ0 */ + .org siu_vector - file_base +siu_vectors: + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_IRQ0 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* Level 0 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_LVL0 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* *IRQ1 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_IRQ1 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* This is probably not the "correct" way to do this. I need to have a + * way of calling _ISR_Handler for the CPM interrupts and this is the + * simplest way I can think of. Since I have the CPM interrupt mapped + * to the SIU interrupt level 1 on the eth-comm board, I put it here. + * It would probably be ok if I moved this directory to under libbsp + * instead of libcpu. For now, deal with it. +*/ +/* Level 1 - CPM */ +/* Now we need to get the CPM interrupt vector */ + /* Registers: */ + /* R0 - has stored value of LR */ + /* R9 - pointer to m860 struct */ + /* R10 has already been saved and restored */ + li r10, 1 + sth r10, 0x930(r9) /* CIVR */ + lbz r10, 0x930(r9) /* if we use this as an offset into a */ + rlwinm r10, r10, 1, 0, 31 /* table, each entry will have room */ + /* 4 instructions. */ + addis r10, r10, cpm_vectors@ha + addi r10, r10, cpm_vectors@l + + mtlr r10 + lwz r10, IP_10(r1) + blr + + nop + nop + nop + nop + nop + nop + nop + +#if 0 +/* Level 1 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_LVL1 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop +#endif + +/* *IRQ2 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_IRQ2 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* Level 2 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_LVL2 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* *IRQ3 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_IRQ3 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* Level 3 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_LVL3 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* *IRQ4 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_IRQ4 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* Level 4 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_LVL4 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* *IRQ5 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_IRQ5 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* Level 5 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_LVL5 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* *IRQ6 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_IRQ6 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* Level 6 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_LVL6 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* *IRQ7 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_IRQ7 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + +/* Level 7 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_LVL7 + b PROC (_ISR_Handler) + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + + +/* .org cpm_vector - file_base*/ +cpm_vectors: + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_RESERVED_0 + .long 0 + + /* PC4 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC4 + b PROC (_ISR_Handler) + + /* PC5 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC5 + b PROC (_ISR_Handler) + + /* SMC2 / PIP */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_SMC2 + b PROC (_ISR_Handler) + + /* SMC1 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_SMC1 + b PROC (_ISR_Handler) + + /* SPI */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_SPI + b PROC (_ISR_Handler) + + /* PC6 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC6 + b PROC (_ISR_Handler) + + /* Timer 4 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_TIMER4 + b PROC (_ISR_Handler) + + /* Reserved - we should never see this */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_RESERVED_8 + .long 0 + + /* PC7 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC7 + b PROC (_ISR_Handler) + + /* PC8 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC8 + b PROC (_ISR_Handler) + + /* PC9 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC9 + b PROC (_ISR_Handler) + + /* Timer 3 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_TIMER3 + b PROC (_ISR_Handler) + + /* Reserved - we should never get here */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_RESERVED_D + .long 0 + + /* PC10 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC10 + b PROC (_ISR_Handler) + + /* PC11 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC11 + b PROC (_ISR_Handler) + + /* I2C */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_I2C + b PROC (_ISR_Handler) + + /* RISC Timer Table */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_RISC_TIMER + b PROC (_ISR_Handler) + + /* Timer 2 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_TIMER2 + b PROC (_ISR_Handler) + + /* Reserved - we should never get here */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_RESERVED_13 + .long 0 + + /* IDMA2 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_IDMA2 + b PROC (_ISR_Handler) + + /* IDMA1 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_IDMA1 + b PROC (_ISR_Handler) + + /* SDMA Channel Bus Error */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_SDMA_ERROR + b PROC (_ISR_Handler) + + /* PC12 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC12 + b PROC (_ISR_Handler) + + /* PC13 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC13 + b PROC (_ISR_Handler) + + /* Timer 1 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_TIMER1 + b PROC (_ISR_Handler) + + /* PC14 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC14 + b PROC (_ISR_Handler) + + /* SCC4 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_SCC4 + b PROC (_ISR_Handler) + + /* SCC3 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_SCC3 + b PROC (_ISR_Handler) + + /* SCC2 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_SCC2 + b PROC (_ISR_Handler) + + /* SCC1 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_SCC1 + b PROC (_ISR_Handler) + + /* PC15 */ + mtlr r0 + lwz r9, IP_9(r1) + li r0, PPC_IRQ_CPM_PC15 + b PROC (_ISR_Handler) + + + -- cgit v1.2.3