From 5018894ee176d1b05daf156a8b858b3db0d457f4 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Mon, 20 Nov 2017 07:45:15 +0100 Subject: bsps/powerpc: Fix PPC_EXC_CONFIG_USE_FIXED_HANDLER For the SPE support we must store the upper half of r3 as well. Update #3085. --- .../powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'c/src/lib/libcpu/powerpc') diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S index 32b867b735..4b318e5e16 100644 --- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S +++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_async_normal.S @@ -88,6 +88,13 @@ ppc_exc_interrupt: oris FRAME_REGISTER, FRAME_REGISTER, MSR_SPE >> 16 mtmsr FRAME_REGISTER isync + + /* + * Save high order part of SCRATCH_1_REGISTER here. The low order part + * was saved in the minimal prologue. + */ + evmergehi SCRATCH_1_REGISTER, SCRATCH_1_REGISTER, FRAME_REGISTER + PPC_REG_STORE FRAME_REGISTER, GPR3_OFFSET(r1) #endif #if defined(PPC_MULTILIB_FPU) || defined(PPC_MULTILIB_ALTIVEC) -- cgit v1.2.3