From 359e5374164ccb2a66833354b412a859c144ea2f Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Mon, 30 Nov 2009 05:09:41 +0000 Subject: Whitespace removal. --- c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c | 20 ++++---- .../mpc5xx/console-generic/console-generic.c | 44 +++++++++--------- .../powerpc/mpc5xx/exceptions/raw_exception.c | 22 ++++----- .../powerpc/mpc5xx/exceptions/raw_exception.h | 10 ++-- c/src/lib/libcpu/powerpc/mpc5xx/include/console.h | 2 +- c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h | 20 ++++---- c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c | 44 +++++++++--------- c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h | 20 ++++---- c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S | 54 +++++++++++----------- c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c | 8 ++-- c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c | 2 +- c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.S | 14 +++--- c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h | 8 ++-- .../libcpu/powerpc/mpc5xx/vectors/vectors_init.c | 6 +-- 14 files changed, 137 insertions(+), 137 deletions(-) (limited to 'c/src/lib/libcpu/powerpc/mpc5xx') diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c b/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c index bdb915fb29..6fedc70bd8 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/clock/clock.c @@ -58,10 +58,10 @@ void Clock_exit( void ); /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; - + /* * ISR Handler */ @@ -70,7 +70,7 @@ rtems_isr Clock_isr(rtems_vector_number vector) usiu.piscrk = USIU_UNLOCK_KEY; usiu.piscr |= USIU_PISCR_PS; /* acknowledge interrupt */ usiu.piscrk = 0; - + Clock_driver_ticks++; rtems_clock_tick(); } @@ -81,10 +81,10 @@ void clockOn(void* unused) uint32_t pit_value; extern uint32_t bsp_clicks_per_usec; - /* calculate and set modulus */ + /* calculate and set modulus */ pit_value = (rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_usec) - 1 ; - + if (pit_value > 0xffff) { /* pit is only 16 bits long */ rtems_fatal_error_occurred(-1); } @@ -114,13 +114,13 @@ clockOff(void* unused) { /* disable PIT and PIT interrupts */ usiu.piscrk = USIU_UNLOCK_KEY; - usiu.piscr &= ~(USIU_PISCR_PTE | USIU_PISCR_PIE); + usiu.piscr &= ~(USIU_PISCR_PTE | USIU_PISCR_PIE); usiu.piscrk = 0; } int clockIsOn(void* unused) { - if (usiu.piscr & USIU_PISCR_PIE) + if (usiu.piscr & USIU_PISCR_PIE) return 1; return 0; } @@ -157,13 +157,13 @@ rtems_device_driver Clock_initialize( ) { Install_clock( Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c b/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c index 43c371248f..19072a3781 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/console-generic/console-generic.c @@ -14,7 +14,7 @@ * MPC5xx port sponsored by Defence Research and Development Canada - Suffield * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) * - * Derived from + * Derived from * c/src/lib/libcpu/powerpc/mpc8xx/console_generic/console_generic.c: * Author: Jay Monkman (jmonkman@frasca.com) * Copyright (C) 1998 by Frasca International, Inc. @@ -84,15 +84,15 @@ static struct termios default_termios = { { 0 } /* control characters */ }; - + /* * Termios callback functions */ int m5xx_uart_firstOpen( - int major, - int minor, + int major, + int minor, void *arg ) { @@ -109,7 +109,7 @@ m5xx_uart_firstOpen( int m5xx_uart_lastClose( - int major, + int major, int minor, void* arg ) @@ -129,7 +129,7 @@ m5xx_uart_pollRead( { volatile m5xxSCIRegisters_t *regs = sci_descs[minor].regs; int c = -1; - + if ( regs ) { while ( (regs->scsr & QSMCM_SCI_RDRF) == 0 ) ; @@ -139,7 +139,7 @@ m5xx_uart_pollRead( return c; } -int +int m5xx_uart_write( int minor, const char *buf, @@ -170,7 +170,7 @@ m5xx_uart_pollWrite( return 0; } -int +int m5xx_uart_setAttributes( int minor, const struct termios *t @@ -179,11 +179,11 @@ m5xx_uart_setAttributes( uint16_t sccr0 = sci_descs[minor].regs->sccr0; uint16_t sccr1 = sci_descs[minor].regs->sccr1; int baud; - + /* * Check that port number is valid */ - if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) + if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) return RTEMS_INVALID_NUMBER; /* Baud rate */ @@ -212,10 +212,10 @@ m5xx_uart_setAttributes( if (baud > 0) { extern uint32_t bsp_clock_speed; sccr0 &= ~QSMCM_SCI_BAUD(-1); - sccr0 |= + sccr0 |= QSMCM_SCI_BAUD((bsp_clock_speed + (16 * baud)) / (32 * baud)); } - + /* Number of data bits -- not available with MPC5xx SCI */ switch ( t->c_cflag & CSIZE ) { case CS5: break; @@ -236,7 +236,7 @@ m5xx_uart_setAttributes( sccr1 |= QSMCM_SCI_PE; else sccr1 &= ~QSMCM_SCI_PE; - + if ( t->c_cflag & PARODD ) sccr1 |= QSMCM_SCI_PT; else @@ -248,29 +248,29 @@ m5xx_uart_setAttributes( sccr1 |= QSMCM_SCI_RE; else sccr1 &= ~QSMCM_SCI_RE; - + /* Write hardware registers */ sci_descs[minor].regs->sccr0 = sccr0; sci_descs[minor].regs->sccr1 = sccr1; - + return RTEMS_SUCCESSFUL; } -/* +/* * Interrupt handling. */ static void m5xx_sci_interrupt_handler (rtems_irq_hdl_param unused) { int minor; - + for ( minor = 0; minor < NUM_PORTS; minor++ ) { sci_desc *desc = &sci_descs[minor]; int sccr1 = desc->regs->sccr1; int scsr = desc->regs->scsr; - - /* + + /* * Character received? */ if ((sccr1 & QSMCM_SCI_RIE) && (scsr & QSMCM_SCI_RDRF)) { @@ -306,14 +306,14 @@ m5xx_uart_initialize (int minor) /* * Check that minor number is valid. */ - if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) + if ( (minor < SCI1_MINOR) || (minor > SCI2_MINOR) ) return; /* * Configure and enable receiver and transmitter. */ m5xx_uart_setAttributes(minor, &default_termios); - + /* * Connect interrupt if not yet done. */ @@ -325,7 +325,7 @@ m5xx_uart_initialize (int minor) irq_data.on = m5xx_sci_nop; /* can't enable both channels here */ irq_data.off = m5xx_sci_nop; /* can't disable both channels here */ irq_data.isOn = m5xx_sci_isOn; - + if (!CPU_install_rtems_irq_handler (&irq_data)) { printk("Unable to connect SCI Irq handler\n"); rtems_fatal_error_occurred(1); diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.c b/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.c index 7c131cc7b7..d88e9787ac 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.c @@ -61,7 +61,7 @@ int mpc5xx_vector_is_valid(rtems_vector vector) case ASM_MEBREAK_VECTOR: case ASM_NMEBREAK_VECTOR: return 1; - default: + default: return 0; } default: @@ -85,19 +85,19 @@ int mpc5xx_set_exception (const rtems_raw_except_connect_data* except) * RATIONALE : to always have the same transition by forcing the user * to get the previous handler before accepting to disconnect. */ - if (exception_handler_table[except->exceptIndex] != + if (exception_handler_table[except->exceptIndex] != default_raw_except_entry.hdl.raw_hdl) { return 0; } rtems_interrupt_disable(level); - + raw_except_table[except->exceptIndex] = *except; exception_handler_table[except->exceptIndex] = except->hdl.raw_hdl; if (except->on) except->on(except); - + rtems_interrupt_enable(level); return 1; } @@ -107,16 +107,16 @@ int mpc5xx_get_current_exception (rtems_raw_except_connect_data* except) if (!mpc5xx_vector_is_valid(except->exceptIndex)){ return 0; } - + *except = raw_except_table[except->exceptIndex]; - + return 1; } int mpc5xx_delete_exception (const rtems_raw_except_connect_data* except) { rtems_interrupt_level level; - + if (!mpc5xx_vector_is_valid(except->exceptIndex)){ return 0; } @@ -135,14 +135,14 @@ int mpc5xx_delete_exception (const rtems_raw_except_connect_data* except) if (except->off) except->off(except); - exception_handler_table[except->exceptIndex] = + exception_handler_table[except->exceptIndex] = default_raw_except_entry.hdl.raw_hdl; - + raw_except_table[except->exceptIndex] = default_raw_except_entry; raw_except_table[except->exceptIndex].exceptIndex = except->exceptIndex; rtems_interrupt_enable(level); - + return 1; } @@ -156,7 +156,7 @@ int mpc5xx_init_exceptions (rtems_raw_except_global_settings* config) { unsigned i; rtems_interrupt_level level; - + /* * store various accelerators */ diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h b/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h index 6d8f7e2714..8388a4d4bc 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/exceptions/raw_exception.h @@ -62,7 +62,7 @@ #ifndef ASM /* - * Type definition for raw exceptions. + * Type definition for raw exceptions. */ typedef unsigned char rtems_vector; @@ -73,7 +73,7 @@ typedef struct { rtems_vector vector; rtems_exception_handler_t* raw_hdl; }rtems_raw_except_hdl; - + typedef void (*rtems_raw_except_enable) (const struct __rtems_raw_except_connect_data__*); typedef void (*rtems_raw_except_disable) (const struct __rtems_raw_except_connect_data__*); typedef int (*rtems_raw_except_is_enabled) (const struct __rtems_raw_except_connect_data__*); @@ -93,16 +93,16 @@ typedef struct __rtems_raw_except_connect_data__{ * libcpu library, this library should have no knowledge of * board specific hardware to manage exceptions and thus the * "on" routine must enable the except at processor level only. - * + * */ - rtems_raw_except_enable on; + rtems_raw_except_enable on; /* * function for disabling raw exceptions. In order to be consistent * with the fact that the raw connexion can defined in the * libcpu library, this library should have no knowledge of * board specific hardware to manage exceptions and thus the * "on" routine must disable the except both at device and PIC level. - * + * */ rtems_raw_except_disable off; /* diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h b/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h index 9c933ffb6b..027754b709 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/include/console.h @@ -8,7 +8,7 @@ * The license and distribution terms for this file may be * found in found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. - * + * * $Id$ */ diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h b/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h index a2c34a3141..8edeaa186e 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/include/mpc5xx.h @@ -44,7 +44,7 @@ * * * Corrections/additions: * * Copyright (c) 1999, National Research Council of Canada * - * + * * MPC5xx port sponsored by Defence Research and Development Canada - Suffield * Copyright (C) 2004, Real-Time Systems Inc. (querbach@realtime.bc.ca) * @@ -340,14 +340,14 @@ do { \ #define UIMB_UMCR_STOP (1<<31) #define UIMB_UMCR_IRQMUX(x) ((x)<<29) #define UIMB_UMCR_HSPEED (1<<28) - + /* ************************************************************************* * QSMCM Serial Communications Interface (SCI) * ************************************************************************* */ - - + + #define QSMCM_ILDSCI(x) ((x)<<8) /* SCI interrupt level */ #define QSMCM_SCI_BAUD(x) ((x)&0x1FFF) /* Baud rate field */ @@ -417,7 +417,7 @@ typedef struct usiu_ { uint8_t _pad71[0x03C-0x034]; uint32_t pdmcr; uint8_t _pad2[0x100-0x40]; - + /* * MEMC Block */ @@ -428,7 +428,7 @@ typedef struct usiu_ { uint8_t _pad8[0x178-0x148]; uint16_t mstat; uint8_t _pad9[0x200-0x17A]; - + /* * System integration timers */ @@ -450,7 +450,7 @@ typedef struct usiu_ { uint16_t pitr; uint16_t _pad_14_2; uint8_t _pad15[0x280-0x24c]; - + /* * Clocks and Reset */ @@ -462,7 +462,7 @@ typedef struct usiu_ { uint16_t _pad73; uint16_t vsrmcr; uint8_t _pad16[0x300-0x292]; - + /* * System integration timers keys */ @@ -479,7 +479,7 @@ typedef struct usiu_ { uint32_t piscrk; uint32_t pitck; uint8_t _pad19[0x380-0x348]; - + /* * Clocks and Reset Keys */ @@ -541,7 +541,7 @@ typedef struct m5xxSPIRegisters_ { /* * Queued Serial Multi-Channel Module (QSMCM) - */ + */ typedef struct m5xxQSMCMRegisters_ { uint16_t qsmcmmcr; uint16_t qtest; diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c index c109bc35b2..443340a914 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.c @@ -16,7 +16,7 @@ * * $Id$ */ - + #include #include #include @@ -28,12 +28,12 @@ * Convert an rtems_irq_number constant to an interrupt level * suitable for programming into an I/O device's interrupt level field. */ - + int CPU_irq_level_from_symbolic_name(const rtems_irq_number name) { if (CPU_USIU_EXT_IRQ_0 <= name && name <= CPU_USIU_INT_IRQ_7) return (name - CPU_USIU_EXT_IRQ_0) / 2; - + if (CPU_UIMB_IRQ_8 <= name && name <= CPU_UIMB_IRQ_31) return 8 + (name - CPU_UIMB_IRQ_8); @@ -84,9 +84,9 @@ static inline int is_proc_irq(const rtems_irq_number irqLine) /* - * Masks used to mask off the interrupts. For exmaple, for ILVL2, the - * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 - * and ILVL7. + * Masks used to mask off the interrupts. For exmaple, for ILVL2, the + * mask is used to mask off interrupts ILVL2, IRQ3, ILVL3, ... IRQ7 + * and ILVL7. * */ const static unsigned int USIU_IvectMask[CPU_USIU_IRQ_COUNT] = @@ -134,7 +134,7 @@ static void compute_USIU_IvectMask_from_prio () */ static int isValidInterrupt(int irq) { - if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET) + if ( (irq < CPU_MIN_OFFSET) || (irq > CPU_MAX_OFFSET) || (irq == CPU_UIMB_INTERRUPT) ) return 0; return 1; @@ -164,7 +164,7 @@ int CPU_irq_enabled_at_uimb(const rtems_irq_number irqLine) int CPU_irq_enable_at_usiu(const rtems_irq_number irqLine) { int usiu_irq_index; - + if (!is_usiu_irq(irqLine)) return 1; @@ -181,7 +181,7 @@ int CPU_irq_disable_at_usiu(const rtems_irq_number irqLine) if (!is_usiu_irq(irqLine)) return 1; - + usiu_irq_index = ((int) (irqLine) - CPU_USIU_IRQ_MIN_OFFSET); ppc_cached_irq_mask &= ~(1 << (31-usiu_irq_index)); usiu.simask = ppc_cached_irq_mask; @@ -207,7 +207,7 @@ int CPU_irq_enabled_at_usiu(const rtems_irq_number irqLine) int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -228,14 +228,14 @@ int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq) * store the data provided by user */ rtems_hdl_tbl[irq->name] = *irq; - + if (is_uimb_irq(irq->name)) { /* * Enable interrupt at UIMB level */ CPU_irq_enable_at_uimb (irq->name); } - + if (is_usiu_irq(irq->name)) { /* * Enable interrupt at USIU level @@ -254,7 +254,7 @@ int CPU_install_rtems_irq_handler (const rtems_irq_connect_data* irq) */ if (irq->on) irq->on(irq); - + rtems_interrupt_enable(level); return 1; @@ -273,7 +273,7 @@ int CPU_get_current_rtems_irq_handler (rtems_irq_connect_data* irq) int CPU_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) { rtems_interrupt_level level; - + if (!isValidInterrupt(irq->name)) { return 0; } @@ -311,7 +311,7 @@ int CPU_remove_rtems_irq_handler (const rtems_irq_connect_data* irq) /* * disable exception at processor level */ - } + } /* * restore the default irq value @@ -424,7 +424,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[CPU_DECREMENTER].hdl(rtems_hdl_tbl[CPU_DECREMENTER].handle); _CPU_MSR_SET(msr); @@ -448,20 +448,20 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) * interrupts. */ usiu.sipend = (1 << (31 - irq)); - + if (uimbIntr) { /* * Look at the bits set in the UIMB interrupt-pending register. The - * highest-order set bit indicates the handler we will run. + * highest-order set bit indicates the handler we will run. * * Unfortunately, we can't easily mask individual UIMB interrupts * unless they use USIU levels 0 to 6, so we must mask all low-level * (level > 7) UIMB interrupts while we service any interrupt. */ int uipend = imb.uimb.uipend << 8; - + if (uipend == 0) { /* spurious interrupt? use last vector */ - irq = CPU_UIMB_IRQ_MAX_OFFSET; + irq = CPU_UIMB_IRQ_MAX_OFFSET; } else { irq = CPU_UIMB_IRQ_MIN_OFFSET; @@ -473,7 +473,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) _CPU_MSR_GET(msr); new_msr = msr | MSR_EE; _CPU_MSR_SET(new_msr); - + rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle); _CPU_MSR_SET(msr); @@ -482,7 +482,7 @@ void C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum) usiu.simask = ppc_cached_irq_mask; } } - + void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx) { /* diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h index 6086db8e65..87c6593e10 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq.h @@ -1,4 +1,4 @@ -/* +/* * irq.h * * This include file describe the data structure and the functions implemented @@ -40,8 +40,8 @@ extern volatile unsigned int ppc_cached_irq_mask; * Symblolic IRQ names and related definitions. */ - /* - * Base vector for our USIU IRQ handlers. + /* + * Base vector for our USIU IRQ handlers. */ #define CPU_USIU_VECTOR_BASE (CPU_ASM_IRQ_VECTOR_BASE) /* @@ -71,7 +71,7 @@ extern volatile unsigned int ppc_cached_irq_mask; #define CPU_MAX_OFFSET (CPU_PROC_IRQ_MAX_OFFSET) /* * USIU IRQ symbolic name definitions. - */ + */ #define CPU_USIU_EXT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 0) #define CPU_USIU_INT_IRQ_0 (CPU_USIU_IRQ_MIN_OFFSET + 1) @@ -80,19 +80,19 @@ extern volatile unsigned int ppc_cached_irq_mask; #define CPU_USIU_EXT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 4) #define CPU_USIU_INT_IRQ_2 (CPU_USIU_IRQ_MIN_OFFSET + 5) - + #define CPU_USIU_EXT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 6) #define CPU_USIU_INT_IRQ_3 (CPU_USIU_IRQ_MIN_OFFSET + 7) - + #define CPU_USIU_EXT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 8) #define CPU_USIU_INT_IRQ_4 (CPU_USIU_IRQ_MIN_OFFSET + 9) #define CPU_USIU_EXT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 10) #define CPU_USIU_INT_IRQ_5 (CPU_USIU_IRQ_MIN_OFFSET + 11) - + #define CPU_USIU_EXT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 12) #define CPU_USIU_INT_IRQ_6 (CPU_USIU_IRQ_MIN_OFFSET + 13) - + #define CPU_USIU_EXT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 14) #define CPU_USIU_INT_IRQ_7 (CPU_USIU_IRQ_MIN_OFFSET + 15) @@ -101,7 +101,7 @@ extern volatile unsigned int ppc_cached_irq_mask; */ #define CPU_PERIODIC_TIMER (CPU_USIU_INT_IRQ_6) #define CPU_UIMB_INTERRUPT (CPU_USIU_INT_IRQ_7) - + /* * UIMB IRQ symbolic name definitions. The first 8 sources are aliases to * the USIU interrupts of the same number, because they are detected in @@ -140,7 +140,7 @@ extern volatile unsigned int ppc_cached_irq_mask; #define CPU_UIMB_IRQ_29 (CPU_UIMB_IRQ_MIN_OFFSET+21) #define CPU_UIMB_IRQ_30 (CPU_UIMB_IRQ_MIN_OFFSET+22) #define CPU_UIMB_IRQ_31 (CPU_UIMB_IRQ_MIN_OFFSET+23) - + /* * Symbolic names for UIMB interrupt sources. */ diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S index 9271a83f1d..cf79c13ed9 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_asm.S @@ -1,7 +1,7 @@ /* * irq_asm.S * - * This file contains the assembly code for the PowerPC + * This file contains the assembly code for the PowerPC * IRQ veneers for RTEMS. * * The license and distribution terms for this file may be @@ -23,7 +23,7 @@ * * $Id$ */ - + #include #include #include @@ -33,7 +33,7 @@ #define SYNC \ sync; \ isync - + /* * Common handler for interrupt exceptions. * @@ -46,22 +46,22 @@ * LR have been saved. R4 holds the exception number. */ PUBLIC_VAR(C_dispatch_irq_handler) - + PUBLIC_VAR(dispatch_irq_handler) SYM (dispatch_irq_handler): /* - * Save SRR0/SRR1 As soon As possible as it is the minimal needed + * Save SRR0/SRR1 As soon As possible as it is the minimal needed * to re-enable exception processing. - * + * * Note that R2 should never change (it's the EABI pointer to - * .sdata2), but we save it just in case. + * .sdata2), but we save it just in case. */ stw r0, GPR0_OFFSET(r1) stw r2, GPR2_OFFSET(r1) - + mfsrr0 r0 mfsrr1 r3 - + stw r0, SRR0_FRAME_OFFSET(r1) stw r3, SRR1_FRAME_OFFSET(r1) @@ -93,11 +93,11 @@ SYM (dispatch_irq_handler): mfcr r5 mfctr r6 mfxer r7 - + stw r5, EXC_CR_OFFSET(r1) stw r6, EXC_CTR_OFFSET(r1) stw r7, EXC_XER_OFFSET(r1) - + /* * Add some non volatile registers to store information that will be * used when returning from C handler. @@ -128,9 +128,9 @@ SYM (dispatch_irq_handler): bne nested mfspr r1, SPRG1 /* switch to interrupt stack */ -nested: +nested: - /* + /* * Start Incrementing nesting level in R3 */ addi r3, r3, 1 @@ -153,11 +153,11 @@ nested: /* * We are now running on the interrupt stack. External and decrementer * exceptions are still disabled. I see no purpose trying to optimize - * further assembler code. + * further assembler code. */ /* - * Call C exception handler for decrementer or external interrupt. + * Call C exception handler for decrementer or external interrupt. * Pass frame along just in case.. * * C_dispatch_irq_handler(cpu_interrupt_frame* r3, vector r4) @@ -166,7 +166,7 @@ nested: bl C_dispatch_irq_handler /* - * start decrementing nesting level. Note : do not test result against 0 + * start decrementing nesting level. Note : do not test result against 0 * value as an easy exit condition because if interrupt nesting level > 1 * then _Thread_Dispatch_disable_level > 1 */ @@ -187,7 +187,7 @@ nested: cmpwi r3, 0 /* - * switch back to original stack (done here just optimize registers + * switch back to original stack (done here just optimize registers * contention. Could have been done before...) */ addi r1, r14, 0 @@ -196,14 +196,14 @@ nested: /* * Here we are running again on the thread system stack. * We have interrupt nesting level = _Thread_Dispatch_disable_level = 0. - * Interrupt are still disabled. Time to check if scheduler request to + * Interrupt are still disabled. Time to check if scheduler request to * do something with the current thread... */ addis r4, 0, _Context_Switch_necessary@ha lbz r5, _Context_Switch_necessary@l(r4) cmpwi r5, 0 bne switch - + addis r6, 0, _ISR_Signals_to_thread_executing@ha lbz r7, _ISR_Signals_to_thread_executing@l(r6) cmpwi r7, 0 @@ -241,12 +241,12 @@ nested: lwz r30, EXC_XER_OFFSET(r1) lwz r29, EXC_CR_OFFSET(r1) lwz r28, EXC_LR_OFFSET(r1) - + mtctr r31 mtxer r30 mtcr r29 mtlr r28 - + lmw r4, GPR4_OFFSET(r1) lwz r2, GPR2_OFFSET(r1) lwz r0, GPR0_OFFSET(r1) @@ -260,22 +260,22 @@ nested: /* * Restore rfi related settings */ - + lwz r3, SRR1_FRAME_OFFSET(r1) mtsrr1 r3 lwz r3, SRR0_FRAME_OFFSET(r1) mtsrr0 r3 - + lwz r3, GPR3_OFFSET(r1) addi r1,r1, EXCEPTION_FRAME_END SYNC rfi - + switch: bl SYM (_Thread_Dispatch) - -easy_exit: + +easy_exit: /* * start restoring interrupt frame */ @@ -283,7 +283,7 @@ easy_exit: lwz r4, EXC_XER_OFFSET(r1) lwz r5, EXC_CR_OFFSET(r1) lwz r6, EXC_LR_OFFSET(r1) - + mtctr r3 mtxer r4 mtcr r5 diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c index 9f2488a012..009443cca2 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/irq/irq_init.c @@ -1,4 +1,4 @@ -/* +/* * irq_init.c * * This file contains the implementation of rtems initialization @@ -90,7 +90,7 @@ void CPU_USIU_irq_init() usiu.siel = usiu.siel; } -/* +/* * Initialize UIMB interrupt management */ void @@ -102,7 +102,7 @@ void CPU_rtems_irq_mng_init(unsigned cpuId) { rtems_raw_except_connect_data vectorDesc; int i; - + CPU_USIU_irq_init(); CPU_UIMB_irq_init(); /* @@ -130,7 +130,7 @@ void CPU_rtems_irq_mng_init(unsigned cpuId) */ BSP_panic("Unable to initialize RTEMS interrupt Management\n"); } - + /* * We must connect the raw irq handler for the two * expected interrupt sources : decrementer and external interrupts. diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c b/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c index 98460cafea..7aa0c6be92 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/timer/timer.c @@ -75,7 +75,7 @@ void benchmark_timer_initialize(void) | USIU_TBSCR_TBF /* freeze timebase during debug */ | USIU_TBSCR_TBE; /* enable timebase */ usiu.tbscrk = 0; - + Timer_starting = get_itimer(); } diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.S b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.S index 2177186969..7dc3434c57 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.S +++ b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.S @@ -14,7 +14,7 @@ * * $Id$ */ - + #include #include #include @@ -22,7 +22,7 @@ #define SYNC \ sync; \ isync - + /* * Hardware exception vector table. @@ -92,7 +92,7 @@ common_prologue: lwz r3, 0(r3) /* get entry */ mtlr r3 /* run it */ blr - + /* * Default exception handler. @@ -106,7 +106,7 @@ common_prologue: * LR have been saved. R4 holds the exception number. */ .text - + PUBLIC_VAR(default_exception_handler) SYM (default_exception_handler): /* @@ -129,7 +129,7 @@ SYM (default_exception_handler): * the frame. * * Note that R2 should never change (it's the EABI pointer to - * .sdata2), but we save it just in case. + * .sdata2), but we save it just in case. * * Recall that R3 and R4 were saved by the specific- and * common-exception handlers before entry to this routine. @@ -153,7 +153,7 @@ SYM (default_exception_handler): /* * Call C-language portion of the default exception handler, passing - * in the address of the frame. + * in the address of the frame. * * To simplify things a bit, we assume that the target routine is * within +/- 32 Mbyte from here, which is a reasonable assumption @@ -192,7 +192,7 @@ SYM (default_exception_handler): mtsrr1 r0 lwz r0, SRR0_FRAME_OFFSET(r1) mtsrr0 r0 - + /* * Restore the final GPR, close the stack frame, and return to the * interrupted code. diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h index 53ae416969..438562a8a3 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h +++ b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors.h @@ -1,4 +1,4 @@ -/* +/* * vectors.h Exception frame related contant and API. * * This include file describe the data structure and the functions implemented @@ -28,10 +28,10 @@ #define NUM_EXCEPTIONS 0x20 /* - * The callee (high level exception code written in C) + * The callee (high level exception code written in C) * will store the Link Registers (return address) at entry r1 + 4 !!!. * So let room for it!!!. - */ + */ #define LINK_REGISTER_CALLEE_UPDATE_ROOM 4 #define SRR0_FRAME_OFFSET 8 #define SRR1_FRAME_OFFSET 12 @@ -140,7 +140,7 @@ typedef void rtems_exception_handler_t (CPU_Exception_frame* excPtr); /* * Exception handler table. * - * This table contains pointers to assembly-language exception handlers. + * This table contains pointers to assembly-language exception handlers. * The common exception prologue in vectors.S looks up an entry in this * table and jumps to it. No return address is saved, so the handlers in * this table must return directly to the interrupted code. diff --git a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c index e5314ee50a..66bc729852 100644 --- a/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c +++ b/c/src/lib/libcpu/powerpc/mpc5xx/vectors/vectors_init.c @@ -1,4 +1,4 @@ -/* +/* * vectors_init.c Exception hanlding initialisation (and generic handler). * * This include file describe the data structure and the functions implemented @@ -32,7 +32,7 @@ rtems_exception_handler_t* exception_handler_table[NUM_EXCEPTIONS]; void C_default_exception_handler(CPU_Exception_frame* excPtr) { int recoverable = 0; - + printk("exception handler called for exception %d\n", excPtr->_EXC_number); printk("\t Next PC or Address of fault = %x\n", excPtr->EXC_SRR0); printk("\t Saved MSR = %x\n", excPtr->EXC_SRR1); @@ -76,7 +76,7 @@ void C_default_exception_handler(CPU_Exception_frame* excPtr) if (excPtr->_EXC_number == ASM_DEC_VECTOR) recoverable = 1; if (excPtr->_EXC_number == ASM_SYS_VECTOR) -#ifdef TEST_RAW_EXCEPTION_CODE +#ifdef TEST_RAW_EXCEPTION_CODE recoverable = 1; #else recoverable = 0; -- cgit v1.2.3