From 359e5374164ccb2a66833354b412a859c144ea2f Mon Sep 17 00:00:00 2001 From: Ralf Corsepius Date: Mon, 30 Nov 2009 05:09:41 +0000 Subject: Whitespace removal. --- c/src/lib/libcpu/mips/au1x00/include/au1x00.h | 22 ++++++------- .../lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c | 4 +-- .../lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c | 20 ++++++------ c/src/lib/libcpu/mips/clock/ckinit.c | 10 +++--- c/src/lib/libcpu/mips/clock/clock.S | 2 +- c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c | 36 +++++++++++----------- .../lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c | 4 +-- .../lib/libcpu/mips/mongoosev/include/mongoose-v.h | 10 +++--- .../libcpu/mips/mongoosev/vectorisrs/maxvectors.c | 8 ++--- .../libcpu/mips/mongoosev/vectorisrs/vectorisrs.c | 18 +++++------ .../lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c | 4 +-- .../lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c | 4 +-- .../lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c | 2 +- .../libcpu/mips/shared/interrupts/isr_entries.S | 8 ++--- c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c | 4 +-- c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c | 4 +-- c/src/lib/libcpu/mips/tx49/include/tx4925.h | 4 +-- c/src/lib/libcpu/mips/tx49/include/tx4938.h | 4 +-- c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c | 4 +-- c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c | 8 ++--- 20 files changed, 90 insertions(+), 90 deletions(-) (limited to 'c/src/lib/libcpu/mips') diff --git a/c/src/lib/libcpu/mips/au1x00/include/au1x00.h b/c/src/lib/libcpu/mips/au1x00/include/au1x00.h index 7f027119cf..5a489fa959 100644 --- a/c/src/lib/libcpu/mips/au1x00/include/au1x00.h +++ b/c/src/lib/libcpu/mips/au1x00/include/au1x00.h @@ -3,7 +3,7 @@ * * Copyright (c) 2005 by Cogent Computer Systems * Written by Jay Monkman - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -189,15 +189,15 @@ #define MEM_STADDR3 0x11003f00 /* - * SDCS0 - - * SDCS1 - - * SDCS2 - + * SDCS0 - + * SDCS1 - + * SDCS2 - */ #define MEM_SDMODE0 0x00552229 #define MEM_SDMODE1 0x00552229 #define MEM_SDMODE2 0x00552229 -#define MEM_SDADDR0 0x001003F8 +#define MEM_SDADDR0 0x001003F8 #define MEM_SDADDR1 0x001023F8 #define MEM_SDADDR2 0x001043F8 @@ -245,7 +245,7 @@ -#define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00)) +#define AU1X00_SYS_TOYTRIM(x) (*(volatile uint32_t*)(x + 0x00)) #define AU1X00_SYS_TOYWRITE(x) (*(volatile uint32_t*)(x + 0x04)) #define AU1X00_SYS_TOYMATCH0(x) (*(volatile uint32_t*)(x + 0x08)) #define AU1X00_SYS_TOYMATCH1(x) (*(volatile uint32_t*)(x + 0x0c)) @@ -315,7 +315,7 @@ typedef struct { uint32_t _rsv0; uint32_t _rsv1; } au1x00_macdma_rx_t; - + typedef struct { volatile uint32_t stat; @@ -323,7 +323,7 @@ typedef struct { volatile uint32_t len; uint32_t _rsv0; } au1x00_macdma_tx_t; - + #define AU1X00_MAC_CTRL_RA (bit(31)) #define AU1X00_MAC_CTRL_EM (bit(30)) #define AU1X00_MAC_CTRL_DO (bit(23)) @@ -392,7 +392,7 @@ typedef struct { #define AU1X00_MAC_DMA_TXSTAT_PR (bit(31)) -#define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10) +#define AU1X00_MAC_DMA_TXSTAT_CC_MASK (0xf << 10) #define AU1X00_MAC_DMA_TXSTAT_LO (bit(9)) #define AU1X00_MAC_DMA_TXSTAT_DF (bit(8)) #define AU1X00_MAC_DMA_TXSTAT_UR (bit(7)) @@ -425,8 +425,8 @@ typedef struct { volatile uint32_t enable; } au1x00_uart_t; -extern au1x00_uart_t *uart0; -extern au1x00_uart_t *uart3; +extern au1x00_uart_t *uart0; +extern au1x00_uart_t *uart3; /* * Interrupt Vector Numbers diff --git a/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c index f006a21999..6830656577 100644 --- a/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c index f301567181..4d6da36da3 100644 --- a/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c +++ b/c/src/lib/libcpu/mips/au1x00/vectorisrs/vectorisrs.c @@ -1,9 +1,9 @@ /* - * Au1x00 Interrupt Vectoring + * Au1x00 Interrupt Vectoring * * Copyright (c) 2005 by Cogent Computer Systems * Written by Jay Monkman - * + * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * @@ -44,7 +44,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) if ( cause & 0x80 ) { unsigned long zero = 0; /* - * I don't see a good way to disable the compare + * I don't see a good way to disable the compare * interrupt, so let's just ignore it. */ asm volatile ("mtc0 %0, $11\n" :: "r" (zero)); @@ -56,23 +56,23 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) if ( cause & 0x40 ) { CALL_ISR( AU1X00_IRQ_PERF, frame ); } - + /* Interrupt controller 0 */ if ( cause & 0x0c ) { call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR); } - + /* Interrupt controller 1 */ if ( cause & 0x30 ) { call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR); } - + /* SW[0] */ if ( cause & 0x01 ) CALL_ISR( AU1X00_IRQ_SW0, frame ); - + /* SW[1] */ - if ( cause & 0x02 ) + if ( cause & 0x02 ) CALL_ISR( AU1X00_IRQ_SW1, frame ); } @@ -90,8 +90,8 @@ void mips_default_isr( int vector ) } static void call_vectored_isr( - CPU_Interrupt_frame *frame, - uint32_t cause, + CPU_Interrupt_frame *frame, + uint32_t cause, void *ctrlr ) { diff --git a/c/src/lib/libcpu/mips/clock/ckinit.c b/c/src/lib/libcpu/mips/clock/ckinit.c index c2d170ba2e..54ab69d1e0 100644 --- a/c/src/lib/libcpu/mips/clock/ckinit.c +++ b/c/src/lib/libcpu/mips/clock/ckinit.c @@ -84,7 +84,7 @@ uint32_t Clock_isrs; /* ISRs until next tick */ /* * These are set by clock driver during its init */ - + rtems_device_major_number rtems_clock_major = ~0; rtems_device_minor_number rtems_clock_minor; @@ -160,7 +160,7 @@ void Install_clock( * Hardware specific initialize goes here */ - mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * + mips_timer_rate = rtems_configuration_get_microseconds_per_tick() * bsp_clicks_per_microsecond; mips_set_timer( mips_timer_rate ); mips_enable_in_interrupt_mask(CLOCK_VECTOR_MASK); @@ -195,13 +195,13 @@ rtems_device_driver Clock_initialize( ) { Install_clock( Clock_isr ); - + /* * make major/minor avail to others such as shared memory driver */ - + rtems_clock_major = major; rtems_clock_minor = minor; - + return RTEMS_SUCCESSFUL; } diff --git a/c/src/lib/libcpu/mips/clock/clock.S b/c/src/lib/libcpu/mips/clock/clock.S index cd535bdf63..de62337faa 100644 --- a/c/src/lib/libcpu/mips/clock/clock.S +++ b/c/src/lib/libcpu/mips/clock/clock.S @@ -1,4 +1,4 @@ -/* clock.s +/* clock.s * * This file contains the assembly code for the IDT 4650 clock driver. * diff --git a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c index 5b284bc463..af832cfdbd 100644 --- a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c +++ b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c @@ -172,8 +172,8 @@ MG5UART_STATIC int mg5uart_set_attributes( cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER ); - MG5UART_SETREG( pMG5UART, - MG5UART_COMMAND_REGISTER, + MG5UART_SETREG( pMG5UART, + MG5UART_COMMAND_REGISTER, (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd ); @@ -305,8 +305,8 @@ MG5UART_STATIC int mg5uart_open( MG5UART_SETREG( pMG5UART_port, MG5UART_BAUD_RATE, baudcmd ); - MG5UART_SETREG( pMG5UART, - MG5UART_COMMAND_REGISTER, + MG5UART_SETREG( pMG5UART, + MG5UART_COMMAND_REGISTER, cmd = (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); rtems_interrupt_enable(Irql); @@ -352,8 +352,8 @@ MG5UART_STATIC int mg5uart_close( rtems_interrupt_disable(Irql); cmdSave = MG5UART_GETREG( pMG5UART, MG5UART_COMMAND_REGISTER ); - MG5UART_SETREG( pMG5UART, - MG5UART_COMMAND_REGISTER, + MG5UART_SETREG( pMG5UART, + MG5UART_COMMAND_REGISTER, (cmdSave & ~(MONGOOSEV_UART_ALL_STATUS_BITS << shift)) | (cmd << shift) ); rtems_interrupt_enable(Irql); @@ -393,7 +393,7 @@ MG5UART_STATIC void mg5uart_write_polled( */ timeout = 2000; - while( --timeout ) + while( --timeout ) { status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift; @@ -411,7 +411,7 @@ MG5UART_STATIC void mg5uart_write_polled( */ #if 0 - if(_System_state_Is_up(_System_state_Get())) + if(_System_state_Is_up(_System_state_Get())) { rtems_task_wake_after(RTEMS_YIELD_PROCESSOR); } @@ -473,8 +473,8 @@ __ISR(rx_ready, MG5UART_IRQ_RX_READY) MG5UART_STATIC void mg5uart_process_isr_rx_error( - int minor, - uint32_t mask + int minor, + uint32_t mask ) { uint32_t pMG5UART; @@ -524,7 +524,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr( { uint32_t pMG5UART; int shift; - + pMG5UART = Console_Port_Tbl[minor].ulCtrlPort1; mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); @@ -533,7 +533,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr( shift = MONGOOSEV_UART0_IRQ_SHIFT; else shift = MONGOOSEV_UART1_IRQ_SHIFT; - + MG5UART_SETREG( pMG5UART, MG5UART_STATUS_REGISTER, @@ -549,7 +549,7 @@ MG5UART_STATIC void mg5uart_process_tx_isr( * There are no more characters to transmit. The tx interrupts are be cleared * by writing data to the uart, so just disable the tx interrupt sources. */ - + Console_Port_Data[minor].bActive = FALSE; /* mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); */ @@ -659,7 +659,7 @@ MG5UART_STATIC int mg5uart_write_support_int( MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, *buf); - if( Console_Port_Data[minor].bActive == FALSE ) + if( Console_Port_Data[minor].bActive == FALSE ) { Console_Port_Data[minor].bActive = TRUE; mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL); @@ -690,7 +690,7 @@ MG5UART_STATIC int mg5uart_write_support_polled( /* * poll each byte in the string out of the port. */ - while (nwrite < len) + while (nwrite < len) { mg5uart_write_polled(minor, *buf++); nwrite++; @@ -734,11 +734,11 @@ MG5UART_STATIC int mg5uart_inbyte_nonblocking_polled( status = MG5UART_GETREG(pMG5UART, MG5UART_STATUS_REGISTER) >> shift; } - if ( status & MONGOOSEV_UART_RX_READY ) + if ( status & MONGOOSEV_UART_RX_READY ) { return (int) MG5UART_GETREG(pMG5UART_port, MG5UART_RX_BUFFER); - } - else + } + else { return -1; } diff --git a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c index b81d851fb2..316896665a 100644 --- a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c +++ b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart_reg.c @@ -20,13 +20,13 @@ #ifndef _MG5UART_MULTIPLIER #define _MG5UART_MULTIPLIER 1 #define _MG5UART_NAME(_X) _X -#define _MG5UART_TYPE uint32_t +#define _MG5UART_TYPE uint32_t #endif #define CALCULATE_REGISTER_ADDRESS( _base, _reg ) \ (_MG5UART_TYPE *)((_base) + ((_reg) * _MG5UART_MULTIPLIER )) -/* +/* * MG5UART Get Register Routine */ diff --git a/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h b/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h index 57fa593a91..b4e6403b6f 100644 --- a/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h +++ b/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h @@ -122,10 +122,10 @@ #define MONGOOSEV_UART_ALL_RX_STATUS_BITS 0x0013 #define MONGOOSEV_UART_ALL_STATUS_BITS 0x001F -/* - * The Peripheral Interrupt Status, Cause, and Mask registers have the - * same bit assignments although some revisions of the document have - * the Cause and Status registers incorrect. +/* + * The Peripheral Interrupt Status, Cause, and Mask registers have the + * same bit assignments although some revisions of the document have + * the Cause and Status registers incorrect. */ #define MONGOOSEV_UART0_IRQ_SHIFT 11 @@ -193,7 +193,7 @@ ** Peripheral Command bits (non-uart, those are defined above) */ #define MONGOOSEV_COMMAND_ENABLE_EDAC MONGOOSEV_EDAC_SERR_BIT -#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT +#define MONGOOSEV_COMMAND_OVERRIDE_EDAC MONGOOSEV_EDAC_MERR_BIT diff --git a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c index 6f40a79df9..6933eb7553 100644 --- a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). @@ -17,9 +17,9 @@ */ /* - * The Synova Mongoose-V attached one of the eight interrupt bits + * The Synova Mongoose-V attached one of the eight interrupt bits * to a Peripheral Function Interrupt Cause Register on-CPU. - * This results in: 2 software interrupts, 5 interrupts + * This results in: 2 software interrupts, 5 interrupts * through the IP bits, and 32 more from the PFICR. Some of * these are reserved but for simplicity in processing, we * reserve slots for those bits anyway. diff --git a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c index ba1499433d..421f95da58 100644 --- a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c +++ b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c @@ -91,7 +91,7 @@ int assertSoftwareInterrupt( uint32_t n ) static volatile uint32_t _ivcause, _ivsr; -static uint32_t READ_CAUSE(void) +static uint32_t READ_CAUSE(void) { mips_get_cause( _ivcause ); _ivcause &= SR_IMASK; /* mask off everything other than the interrupt bits */ @@ -140,7 +140,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) if ( cshifted & 0x01 ) /* SW[0] */ { CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_1, frame ); - } + } if ( cshifted & 0x02 ) /* SW[1] */ { CALL_ISR( MONGOOSEV_IRQ_SOFTWARE_2, frame ); @@ -156,7 +156,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) CLR_ISR_FLAG( 0x4 ); if( (cshifted = READ_CAUSE()) & 0x3 ) goto intvect; } - + if ( cshifted & 0x08 ) /* IP[1] ==> INT1 == TIMER2*/ { SET_ISR_FLAG( 0x8 ); @@ -164,7 +164,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) CLR_ISR_FLAG( 0x8 ); if( (cshifted = READ_CAUSE()) & 0x7 ) goto intvect; } - + if ( cshifted & 0x10 ) /* IP[2] ==> INT2 */ { SET_ISR_FLAG( 0x10 ); @@ -172,7 +172,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) CLR_ISR_FLAG( 0x10 ); if( (cshifted = READ_CAUSE()) & 0xf ) goto intvect; } - + if ( cshifted & 0x20 ) /* IP[3] ==> INT3 == FPU interrupt */ { SET_ISR_FLAG( 0x20 ); @@ -180,7 +180,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) CLR_ISR_FLAG( 0x20 ); if( (cshifted = READ_CAUSE()) & 0x1f ) goto intvect; } - + if ( cshifted & 0x40 ) /* IP[4] ==> INT4, external interrupt */ { SET_ISR_FLAG( 0x40 ); @@ -198,7 +198,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) pf_icr = MONGOOSEV_READ( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_CAUSE_REGISTER ); /* - for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 ) + for (bit=0, pf_mask = 1; bit < 32; bit++, pf_mask <<= 1 ) { if ( pf_icr & pf_mask ) { @@ -208,7 +208,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) pf_reset |= pf_mask; if( (cshifted = READ_CAUSE()) & 0xff ) break; } - } + } */ /* @@ -217,7 +217,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) * way thru a full 32 bits. pf_mask shifts left 8 bits at a time * to serve as a interrupt cause test mask. */ - for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) ) + for( bit=0, pf_mask = 0xff; (bit < 32 && pf_icr); (bit+=8, pf_mask <<= 8) ) { if ( pf_icr & pf_mask ) { diff --git a/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c index 86cd89f8d3..c7ef845e60 100644 --- a/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c index d72273c582..79c509ca21 100644 --- a/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c index 070884228b..511b8fe4c4 100644 --- a/c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c +++ b/c/src/lib/libcpu/mips/rm52xx/vectorisrs/vectorisrs.c @@ -1,5 +1,5 @@ /* - * RM5231 Interrupt Vectoring + * RM5231 Interrupt Vectoring * * vectorisrs.c,v 1.6 2004/06/23 18:16:36 */ diff --git a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S index 89fc538e49..6c1f4a1637 100644 --- a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S +++ b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.S @@ -32,7 +32,7 @@ FRAME(exc_dbg_code,sp,0,ra) j k0 nop ENDFRAME(exc_dbg_code) - + /* XXX this is dependent on IDT/SIM and needs to be addressed */ FRAME(exc_utlb_code,sp,0,ra) la k0, (R_VEC+((48)*8)) @@ -40,7 +40,7 @@ FRAME(exc_utlb_code,sp,0,ra) nop ENDFRAME(exc_utlb_code) -/* +/* * MIPS ISA Level 32 * XXX Again, reliance on SIM. Not good.?????????? */ @@ -69,8 +69,8 @@ FRAME(exc_norm_code,sp,0,ra) j k0 nop ENDFRAME(exc_norm_code) - -/* + +/* * MIPS ISA Level 3 * XXX Again, reliance on SIM. Not good. */ diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c index c3e41251eb..5a4fb9ca73 100644 --- a/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c index dae7aa2b32..a5b4e182eb 100644 --- a/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c +++ b/c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c @@ -1,5 +1,5 @@ /* - * TX3904 Interrupt Vectoring + * TX3904 Interrupt Vectoring * * $Id$ */ @@ -38,7 +38,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) unsigned int v = (cause >> 2) & 0x0f; CALL_ISR( MIPS_INTERRUPT_BASE + v, frame ); } - + if ( cause & 0x02 ) /* SW[0] */ CALL_ISR( TX3904_IRQ_SOFTWARE_1, frame ); diff --git a/c/src/lib/libcpu/mips/tx49/include/tx4925.h b/c/src/lib/libcpu/mips/tx49/include/tx4925.h index 38985e5fe4..a55107b8c1 100644 --- a/c/src/lib/libcpu/mips/tx49/include/tx4925.h +++ b/c/src/lib/libcpu/mips/tx49/include/tx4925.h @@ -26,7 +26,7 @@ #define TX4925_CFG_RAMP 0xE030 /* Register Address Mapping Register */ /* Pin Configuration register bits */ -#define SELCHI 0x00100000 +#define SELCHI 0x00100000 #define SELTMR0 0x00000200 @@ -64,7 +64,7 @@ #define TWIS 0x8 -/* +/* * Interrupt Controller Registers */ #define TX4925_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */ diff --git a/c/src/lib/libcpu/mips/tx49/include/tx4938.h b/c/src/lib/libcpu/mips/tx49/include/tx4938.h index 2f2b340937..3264784ddd 100644 --- a/c/src/lib/libcpu/mips/tx49/include/tx4938.h +++ b/c/src/lib/libcpu/mips/tx49/include/tx4938.h @@ -41,7 +41,7 @@ #define TX4938_CFG_RAMP 0xE048 /* Register Address Mapping Register */ /* Pin Configuration register bits */ -#define SELCHI 0x00100000 +#define SELCHI 0x00100000 #define SELTMR0 0x00000200 @@ -79,7 +79,7 @@ #define TWIS 0x8 -/* +/* * Interrupt Controller Registers */ #define TX4938_IRQCTL_DEN 0xF600 /* Interrupt Detection Enable Register */ diff --git a/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c index 43fa34f8d1..e56989a297 100644 --- a/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c +++ b/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c @@ -1,6 +1,6 @@ -/* +/* * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. + * be determined without knowing the RTEMS CPU model. * * COPYRIGHT (c) 1989-2000. * On-Line Applications Research Corporation (OAR). diff --git a/c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c b/c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c index b43e08dbf0..1f6b811224 100644 --- a/c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c +++ b/c/src/lib/libcpu/mips/tx49/vectorisrs/vectorisrs.c @@ -1,5 +1,5 @@ /* - * TX4925 Interrupt Vectoring + * TX4925 Interrupt Vectoring * * vectorisrs.c,v 1.6 2004/06/23 18:16:36 */ @@ -35,7 +35,7 @@ void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ) unsigned int v = (cause >> (CAUSE_IPSHIFT + 3)) & 0x1f; CALL_ISR( MIPS_INTERRUPT_BASE + v, frame ); } - + if ( pending & 0x01 ) /* IP[0] */ CALL_ISR( TX4925_IRQ_SOFTWARE_1, frame ); @@ -53,9 +53,9 @@ void mips_default_isr( int vector ) printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr ); - + while(1); /* Lock it up */ - + rtems_fatal_error_occurred(1); } -- cgit v1.2.3