From 0c0181dee26d64835f0cd4f47ef81f681ea553e8 Mon Sep 17 00:00:00 2001 From: Jennifer Averett Date: Wed, 4 Apr 2012 08:39:46 -0500 Subject: PR 1993 - Convert MIPS to PIC IRQ model --- c/src/lib/libcpu/mips/ChangeLog | 13 ++ c/src/lib/libcpu/mips/Makefile.am | 34 ----- c/src/lib/libcpu/mips/au1x00/include/au1x00.h | 100 ++---------- .../lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c | 23 --- c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c | 170 ++++++++++++++------- .../lib/libcpu/mips/mongoosev/include/mongoose-v.h | 68 +-------- .../libcpu/mips/mongoosev/vectorisrs/maxvectors.c | 31 ---- .../lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c | 19 --- c/src/lib/libcpu/mips/rm52xx/include/rm5231.h | 17 ++- .../lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c | 24 --- .../libcpu/mips/shared/interrupts/isr_entries.h | 13 ++ .../mips/shared/interrupts/vectorexceptions.c | 128 ---------------- c/src/lib/libcpu/mips/tx39/include/tx3904.h | 41 ++--- c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c | 29 ---- c/src/lib/libcpu/mips/tx49/include/tx4925.h | 56 ++----- c/src/lib/libcpu/mips/tx49/include/tx4938.h | 56 ++----- c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c | 30 ---- 17 files changed, 205 insertions(+), 647 deletions(-) delete mode 100644 c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c delete mode 100644 c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c delete mode 100644 c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c delete mode 100644 c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c delete mode 100644 c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c delete mode 100644 c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c delete mode 100644 c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c (limited to 'c/src/lib/libcpu/mips') diff --git a/c/src/lib/libcpu/mips/ChangeLog b/c/src/lib/libcpu/mips/ChangeLog index d34fa6497e..9121fa437f 100644 --- a/c/src/lib/libcpu/mips/ChangeLog +++ b/c/src/lib/libcpu/mips/ChangeLog @@ -1,3 +1,16 @@ +2012-02-23 Jennifer Averett + + PR 1993/bsps + * Makefile.am, au1x00/include/au1x00.h, + mongoosev/duart/mg5uart.c, mongoosev/include/mongoose-v.h, + rm52xx/include/rm5231.h, shared/interrupts/isr_entries.h, + tx39/include/tx3904.h, tx49/include/tx4925.h, + tx49/include/tx4938.h: + Mips conversion to PIC IRQ model. + * au1x00/vectorisrs/maxvectors.c,mongoosev/vectorisrs/maxvectors.c + rm52xx/vectorisrs/maxvectors.c, tx39/vectorisrs/maxvectors.c, + tx49/vectorisrs/maxvectors.c: Removed. + 2011-12-10 Ralf Corsépius * shared/interrupts/vectorexceptions.c: Make diff --git a/c/src/lib/libcpu/mips/Makefile.am b/c/src/lib/libcpu/mips/Makefile.am index ffaf95cc01..931cca73a3 100644 --- a/c/src/lib/libcpu/mips/Makefile.am +++ b/c/src/lib/libcpu/mips/Makefile.am @@ -41,7 +41,6 @@ endif noinst_PROGRAMS += shared/interrupts.rel shared_interrupts_rel_SOURCES = shared/interrupts/installisrentries.c \ - shared/interrupts/vectorexceptions.c shared/interrupts/interruptmask.c \ shared/interrupts/isr_entries.S shared/interrupts/isr_entries.h shared_interrupts_rel_CPPFLAGS = $(AM_CPPFLAGS) $(interrupts_CPPFLAGS) shared_interrupts_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) @@ -62,32 +61,15 @@ mongoosev_duart_rel_SOURCES = mongoosev/duart/mg5uart.c \ mongoosev_duart_rel_CPPFLAGS = $(AM_CPPFLAGS) mongoosev_duart_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) -## mongoosev/vectorisrs - -noinst_PROGRAMS += mongoosev/vectorisrs.rel -mongoosev_vectorisrs_rel_SOURCES = mongoosev/vectorisrs/maxvectors.c \ - mongoosev/vectorisrs/vectorisrs.c -mongoosev_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS) -mongoosev_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif if tx39 include_libcpu_HEADERS += tx39/include/tx3904.h - -noinst_PROGRAMS += tx39/vectorisrs.rel -tx39_vectorisrs_rel_SOURCES = tx39/vectorisrs/maxvectors.c tx39/vectorisrs/vectorisrs.c -tx39_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS) -tx39_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif if tx49 include_libcpu_HEADERS += tx49/include/tx4925.h tx49/include/tx4938.h -noinst_PROGRAMS += tx49/vectorisrs.rel -tx49_vectorisrs_rel_SOURCES = tx49/vectorisrs/maxvectors.c tx49/vectorisrs/vectorisrs.c -tx49_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS) -tx49_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - noinst_PROGRAMS += tx49/timer.rel tx49_timer_rel_SOURCES = timer/timer.c timer/gettime.S tx49_timer_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -97,20 +79,9 @@ endif if au1x00 include_libcpu_HEADERS += au1x00/include/au1x00.h -noinst_PROGRAMS += au1x00/vectorisrs.rel -au1x00_vectorisrs_rel_SOURCES = au1x00/vectorisrs/maxvectors.c \ - au1x00/vectorisrs/vectorisrs.c -au1x00_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS) -au1x00_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) endif if r46xx -noinst_PROGRAMS += r46xx/vectorisrs.rel -r46xx_vectorisrs_rel_SOURCES = r46xx/vectorisrs/maxvectors.c \ - r46xx/vectorisrs/vectorisrs.c -r46xx_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS) -r46xx_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - noinst_PROGRAMS += r46xx/timer.rel r46xx_timer_rel_SOURCES = timer/timer.c timer/gettime.S r46xx_timer_rel_CPPFLAGS = $(AM_CPPFLAGS) @@ -125,11 +96,6 @@ endif if rm52xx include_libcpu_HEADERS += rm52xx/include/rm5231.h -noinst_PROGRAMS += rm52xx/vectorisrs.rel -rm52xx_vectorisrs_rel_SOURCES = rm52xx/vectorisrs/maxvectors.c rm52xx/vectorisrs/vectorisrs.c -rm52xx_vectorisrs_rel_CPPFLAGS = $(AM_CPPFLAGS) -rm52xx_vectorisrs_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) - noinst_PROGRAMS += rm52xx/timer.rel rm52xx_timer_rel_SOURCES = timer/timer.c timer/gettime.S rm52xx_timer_rel_CPPFLAGS = $(AM_CPPFLAGS) diff --git a/c/src/lib/libcpu/mips/au1x00/include/au1x00.h b/c/src/lib/libcpu/mips/au1x00/include/au1x00.h index 6704b82b7c..ce84e9803a 100644 --- a/c/src/lib/libcpu/mips/au1x00/include/au1x00.h +++ b/c/src/lib/libcpu/mips/au1x00/include/au1x00.h @@ -1,16 +1,18 @@ -/* +/** + * @file + * * AMD AU1X00 specific information - * - * Copyright (c) 2005 by Cogent Computer Systems - * Written by Jay Monkman + */ + +/* + * Copyright (c) 2005 by Cogent Computer Systems + * Written by Jay Monkman * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at - * * http://www.rtems.com/license/LICENSE. - * + * * $Id$ - * */ #ifndef __AU1X00_H__ @@ -428,90 +430,6 @@ typedef struct { extern au1x00_uart_t *uart0; extern au1x00_uart_t *uart3; -/* - * Interrupt Vector Numbers - * - */ -/* MIPS_INTERRUPT_BASE should be 32 (0x20) */ -#define AU1X00_IRQ_SW0 (MIPS_INTERRUPT_BASE + 0) -#define AU1X00_IRQ_SW1 (MIPS_INTERRUPT_BASE + 1) -#define AU1X00_IRQ_IC0_REQ0 (MIPS_INTERRUPT_BASE + 2) -#define AU1X00_IRQ_IC0_REQ1 (MIPS_INTERRUPT_BASE + 3) -#define AU1X00_IRQ_IC1_REQ0 (MIPS_INTERRUPT_BASE + 4) -#define AU1X00_IRQ_IC1_REQ1 (MIPS_INTERRUPT_BASE + 5) -#define AU1X00_IRQ_PERF (MIPS_INTERRUPT_BASE + 6) -#define AU1X00_IRQ_CNT (MIPS_INTERRUPT_BASE + 7) - -#define AU1X00_IRQ_IC0_BASE (MIPS_INTERRUPT_BASE + 8) -#define AU1X00_IRQ_UART0 (MIPS_INTERRUPT_BASE + 8) -#define AU1X00_IRQ_INTA (MIPS_INTERRUPT_BASE + 9) -#define AU1X00_IRQ_INTB (MIPS_INTERRUPT_BASE + 10) -#define AU1X00_IRQ_UART3 (MIPS_INTERRUPT_BASE + 11) -#define AU1X00_IRQ_INTC (MIPS_INTERRUPT_BASE + 12) -#define AU1X00_IRQ_INTD (MIPS_INTERRUPT_BASE + 13) -#define AU1X00_IRQ_DMA0 (MIPS_INTERRUPT_BASE + 14) -#define AU1X00_IRQ_DMA1 (MIPS_INTERRUPT_BASE + 15) -#define AU1X00_IRQ_DMA2 (MIPS_INTERRUPT_BASE + 16) -#define AU1X00_IRQ_DMA3 (MIPS_INTERRUPT_BASE + 17) -#define AU1X00_IRQ_DMA4 (MIPS_INTERRUPT_BASE + 18) -#define AU1X00_IRQ_DMA5 (MIPS_INTERRUPT_BASE + 19) -#define AU1X00_IRQ_DMA6 (MIPS_INTERRUPT_BASE + 20) -#define AU1X00_IRQ_DMA7 (MIPS_INTERRUPT_BASE + 21) -#define AU1X00_IRQ_TOY_TICK (MIPS_INTERRUPT_BASE + 22) -#define AU1X00_IRQ_TOY_MATCH0 (MIPS_INTERRUPT_BASE + 23) -#define AU1X00_IRQ_TOY_MATCH1 (MIPS_INTERRUPT_BASE + 24) -#define AU1X00_IRQ_TOY_MATCH2 (MIPS_INTERRUPT_BASE + 25) -#define AU1X00_IRQ_RTC_TICK (MIPS_INTERRUPT_BASE + 26) -#define AU1X00_IRQ_RTC_MATCH0 (MIPS_INTERRUPT_BASE + 27) -#define AU1X00_IRQ_RTC_MATCH1 (MIPS_INTERRUPT_BASE + 28) -#define AU1X00_IRQ_RTC_MATCH2 (MIPS_INTERRUPT_BASE + 29) -#define AU1X00_IRQ_PCI_ERR (MIPS_INTERRUPT_BASE + 30) -#define AU1X00_IRQ_RSV0 (MIPS_INTERRUPT_BASE + 31) -#define AU1X00_IRQ_USB_DEV (MIPS_INTERRUPT_BASE + 32) -#define AU1X00_IRQ_USB_SUSPEND (MIPS_INTERRUPT_BASE + 33) -#define AU1X00_IRQ_USB_HOST (MIPS_INTERRUPT_BASE + 34) -#define AU1X00_IRQ_AC97_ACSYNC (MIPS_INTERRUPT_BASE + 35) -#define AU1X00_IRQ_MAC0 (MIPS_INTERRUPT_BASE + 36) -#define AU1X00_IRQ_MAC1 (MIPS_INTERRUPT_BASE + 37) -#define AU1X00_IRQ_RSV1 (MIPS_INTERRUPT_BASE + 38) -#define AU1X00_IRQ_AC97_CMD (MIPS_INTERRUPT_BASE + 39) - -#define AU1X00_IRQ_IC1_BASE (MIPS_INTERRUPT_BASE + 40) -#define AU1X00_IRQ_GPIO0 (MIPS_INTERRUPT_BASE + 40) -#define AU1X00_IRQ_GPIO1 (MIPS_INTERRUPT_BASE + 41) -#define AU1X00_IRQ_GPIO2 (MIPS_INTERRUPT_BASE + 42) -#define AU1X00_IRQ_GPIO3 (MIPS_INTERRUPT_BASE + 43) -#define AU1X00_IRQ_GPIO4 (MIPS_INTERRUPT_BASE + 44) -#define AU1X00_IRQ_GPIO5 (MIPS_INTERRUPT_BASE + 45) -#define AU1X00_IRQ_GPIO6 (MIPS_INTERRUPT_BASE + 46) -#define AU1X00_IRQ_GPIO7 (MIPS_INTERRUPT_BASE + 47) -#define AU1X00_IRQ_GPIO8 (MIPS_INTERRUPT_BASE + 48) -#define AU1X00_IRQ_GPIO9 (MIPS_INTERRUPT_BASE + 49) -#define AU1X00_IRQ_GPIO10 (MIPS_INTERRUPT_BASE + 50) -#define AU1X00_IRQ_GPIO11 (MIPS_INTERRUPT_BASE + 51) -#define AU1X00_IRQ_GPIO12 (MIPS_INTERRUPT_BASE + 52) -#define AU1X00_IRQ_GPIO13 (MIPS_INTERRUPT_BASE + 53) -#define AU1X00_IRQ_GPIO14 (MIPS_INTERRUPT_BASE + 54) -#define AU1X00_IRQ_GPIO15 (MIPS_INTERRUPT_BASE + 55) -#define AU1X00_IRQ_GPIO200 (MIPS_INTERRUPT_BASE + 56) -#define AU1X00_IRQ_GPIO201 (MIPS_INTERRUPT_BASE + 57) -#define AU1X00_IRQ_GPIO202 (MIPS_INTERRUPT_BASE + 58) -#define AU1X00_IRQ_GPIO203 (MIPS_INTERRUPT_BASE + 59) -#define AU1X00_IRQ_GPIO20 (MIPS_INTERRUPT_BASE + 60) -#define AU1X00_IRQ_GPIO204 (MIPS_INTERRUPT_BASE + 61) -#define AU1X00_IRQ_GPIO205 (MIPS_INTERRUPT_BASE + 62) -#define AU1X00_IRQ_GPIO23 (MIPS_INTERRUPT_BASE + 63) -#define AU1X00_IRQ_GPIO24 (MIPS_INTERRUPT_BASE + 64) -#define AU1X00_IRQ_GPIO25 (MIPS_INTERRUPT_BASE + 65) -#define AU1X00_IRQ_GPIO26 (MIPS_INTERRUPT_BASE + 66) -#define AU1X00_IRQ_GPIO27 (MIPS_INTERRUPT_BASE + 67) -#define AU1X00_IRQ_GPIO28 (MIPS_INTERRUPT_BASE + 68) -#define AU1X00_IRQ_GPIO206 (MIPS_INTERRUPT_BASE + 69) -#define AU1X00_IRQ_GPIO207 (MIPS_INTERRUPT_BASE + 70) -#define AU1X00_IRQ_GPIO208_215 (MIPS_INTERRUPT_BASE + 71) - -#define AU1X00_MAXIMUM_VECTORS (MIPS_INTERRUPT_BASE + 72) - void static inline au_sync(void) { __asm__ volatile ("sync"); diff --git a/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c deleted file mode 100644 index 6830656577..0000000000 --- a/c/src/lib/libcpu/mips/au1x00/vectorisrs/maxvectors.c +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. - * - * COPYRIGHT (c) 1989-2000. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * maxvectors.c,v 1.1 2001/05/24 19:54:22 joel Exp - */ - -/* - * Reserve first 32 for exceptions. - */ - -#include -#include - -unsigned int mips_interrupt_number_of_vectors = AU1X00_MAXIMUM_VECTORS; - diff --git a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c index 96bef23708..d7fb5ece7b 100644 --- a/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c +++ b/c/src/lib/libcpu/mips/mongoosev/duart/mg5uart.c @@ -1,14 +1,18 @@ -/* +/** + * @file + * * This file contains the termios TTY driver for the UART found * on the Synova Mongoose-V. - * - * COPYRIGHT (c) 1989-2001. + */ + +/* + * COPYRIGHT (c) 1989-2012. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. - * + * * $Id$ */ @@ -21,7 +25,8 @@ #include #include -extern void set_vector( rtems_isr_entry, rtems_vector_number, int ); +#include +#include /* * Indices of registers @@ -69,6 +74,48 @@ MG5UART_STATIC void mg5uart_enable_interrupts( int mask ); +/* + * mg5uart_isr_XXX + * + * This is the single interrupt entry point which parcels interrupts + * out to the handlers for specific sources and makes sure that the + * shared handler gets the right arguments. + * + * NOTE: Yes .. this is ugly but it provides 5 interrupt source + * wrappers which are nearly functionally identical. + */ + + +extern void mips_default_isr(int vector); + +#define __ISR(_TYPE, _OFFSET) \ + MG5UART_STATIC void mg5uart_process_isr_ ## _TYPE ( \ + int minor \ + ); \ + \ + MG5UART_STATIC rtems_isr mg5uart_isr_ ## _TYPE ( \ + void *arg \ + ) \ + { \ + rtems_vector_number vector = (rtems_vector_number) arg; \ + int minor; \ + \ + for(minor=0 ; minordeviceType == SERIAL_MG5UART && \ + vector == Console_Port_Tbl[minor]->ulIntVector + _OFFSET ) { \ + mg5uart_process_isr_ ## _TYPE (minor); \ + return; \ + } \ + } \ + mips_default_isr( vector ); \ + } + +__ISR(rx_frame_error, MG5UART_IRQ_RX_FRAME_ERROR) +__ISR(rx_overrun_error, MG5UART_IRQ_RX_OVERRUN_ERROR) +__ISR(tx_empty, MG5UART_IRQ_TX_EMPTY) +__ISR(tx_ready, MG5UART_IRQ_TX_READY) +__ISR(rx_ready, MG5UART_IRQ_RX_READY) + /* * mg5uart_set_attributes * @@ -425,51 +472,6 @@ MG5UART_STATIC void mg5uart_write_polled( MG5UART_SETREG(pMG5UART_port, MG5UART_TX_BUFFER, c); } - - - -/* - * mg5uart_isr_XXX - * - * This is the single interrupt entry point which parcels interrupts - * out to the handlers for specific sources and makes sure that the - * shared handler gets the right arguments. - * - * NOTE: Yes .. this is ugly but it provides 5 interrupt source - * wrappers which are nearly functionally identical. - */ - - -extern void mips_default_isr(int vector); - -#define __ISR(_TYPE, _OFFSET) \ - MG5UART_STATIC void mg5uart_process_isr_ ## _TYPE ( \ - int minor \ - ); \ - \ - MG5UART_STATIC rtems_isr mg5uart_isr_ ## _TYPE ( \ - rtems_vector_number vector \ - ) \ - { \ - int minor; \ - \ - for(minor=0 ; minordeviceType == SERIAL_MG5UART && \ - vector == Console_Port_Tbl[minor]->ulIntVector + _OFFSET ) { \ - mg5uart_process_isr_ ## _TYPE (minor); \ - return; \ - } \ - } \ - mips_default_isr( vector ); \ - } - -__ISR(rx_frame_error, MG5UART_IRQ_RX_FRAME_ERROR) -__ISR(rx_overrun_error, MG5UART_IRQ_RX_OVERRUN_ERROR) -__ISR(tx_empty, MG5UART_IRQ_TX_EMPTY) -__ISR(tx_ready, MG5UART_IRQ_TX_READY) -__ISR(rx_ready, MG5UART_IRQ_RX_READY) - - MG5UART_STATIC void mg5uart_process_isr_rx_error( int minor, uint32_t mask @@ -591,9 +593,50 @@ MG5UART_STATIC void mg5uart_process_isr_rx_ready( &c, 1 ); } +static rtems_irq_connect_data mg5uart_rx_frame_error_cd = { \ + 0, /* filled in at initialization */ + mg5uart_isr_rx_frame_error, /* filled in at initialization */ + NULL, /* (void *) minor */ + NULL, + NULL, + NULL +}; + +static rtems_irq_connect_data mg5uart_rx_overrun_error_cd = { \ + 0, /* filled in at initialization */ + mg5uart_isr_rx_overrun_error, /* filled in at initialization */ + NULL, /* (void *) minor */ + NULL, + NULL, + NULL +}; +static rtems_irq_connect_data mg5uart_tx_empty_cd = { \ + 0, /* filled in at initialization */ + mg5uart_isr_tx_empty, /* filled in at initialization */ + NULL, /* (void *) minor */ + NULL, + NULL, + NULL +}; +static rtems_irq_connect_data mg5uart_tx_ready_cd = { \ + 0, /* filled in at initialization */ + mg5uart_isr_tx_ready, /* filled in at initialization */ + NULL, /* (void *) minor */ + NULL, + NULL, + NULL +}; +static rtems_irq_connect_data mg5uart_rx_ready_cd = { \ + 0, /* filled in at initialization */ + mg5uart_isr_rx_ready, /* filled in at initialization */ + NULL, /* (void *) minor */ + NULL, + NULL, + NULL +}; /* @@ -611,19 +654,28 @@ MG5UART_STATIC void mg5uart_initialize_interrupts(int minor) Console_Port_Data[minor].bActive = FALSE; v = Console_Port_Tbl[minor]->ulIntVector; - set_vector(mg5uart_isr_rx_frame_error, v + MG5UART_IRQ_RX_FRAME_ERROR, 1); - set_vector(mg5uart_isr_rx_overrun_error, v + MG5UART_IRQ_RX_OVERRUN_ERROR, 1); - set_vector(mg5uart_isr_tx_empty, v + MG5UART_IRQ_TX_EMPTY, 1); - set_vector(mg5uart_isr_tx_ready, v + MG5UART_IRQ_TX_READY, 1); - set_vector(mg5uart_isr_rx_ready, v + MG5UART_IRQ_RX_READY, 1); + mg5uart_rx_frame_error_cd.name = v + MG5UART_IRQ_RX_FRAME_ERROR; + mg5uart_rx_overrun_error_cd.name = v + MG5UART_IRQ_RX_OVERRUN_ERROR; + mg5uart_tx_empty_cd.name = v + MG5UART_IRQ_TX_EMPTY; + mg5uart_tx_ready_cd.name = v + MG5UART_IRQ_TX_READY; + mg5uart_rx_ready_cd.name = v + MG5UART_IRQ_RX_READY; + + mg5uart_rx_frame_error_cd.handle = (void *)mg5uart_rx_frame_error_cd.name; + mg5uart_rx_overrun_error_cd.handle = (void *)mg5uart_rx_overrun_error_cd.name; + mg5uart_tx_empty_cd.handle = (void *)mg5uart_tx_empty_cd.name; + mg5uart_tx_ready_cd.handle = (void *)mg5uart_tx_ready_cd.name; + mg5uart_rx_ready_cd.handle = (void *)mg5uart_rx_ready_cd.name; + + + BSP_install_rtems_irq_handler( &mg5uart_rx_frame_error_cd ); + BSP_install_rtems_irq_handler( &mg5uart_rx_overrun_error_cd ); + BSP_install_rtems_irq_handler( &mg5uart_tx_empty_cd ); + BSP_install_rtems_irq_handler( &mg5uart_tx_ready_cd ); + BSP_install_rtems_irq_handler( &mg5uart_rx_ready_cd ); mg5uart_enable_interrupts(minor, MG5UART_ENABLE_ALL_EXCEPT_TX); } - - - - /* * mg5uart_write_support_int * diff --git a/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h b/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h index b4e6403b6f..8ad030e5f4 100644 --- a/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h +++ b/c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h @@ -1,13 +1,17 @@ -/* +/** + * @file + * * MIPS Mongoose-V specific information - * - * COPYRIGHT (c) 1989-2001. + */ + +/* + * COPYRIGHT (c) 1989-2012. * On-Line Applications Research Corporation (OAR). * * The license and distribution terms for this file may be * found in the file LICENSE in this distribution or at * http://www.rtems.com/license/LICENSE. - * + * * $Id$ */ @@ -249,62 +253,6 @@ #define MONGOOSEV_TX_BUFFER 4 #define MONGOOSEV_BAUD_RATE 8 -/* - * Interrupt Vector Numbers - * - * NOTE: IRQ INT5 is logical or of peripheral cause register - * per p. 5-22 of Mongoose-V manual. - */ - -#define MONGOOSEV_IRQ_INT0 MIPS_INTERRUPT_BASE+0 -#define MONGOOSEV_IRQ_TIMER1 MONGOOSEV_IRQ_INT0 -#define MONGOOSEV_IRQ_INT1 MIPS_INTERRUPT_BASE+1 -#define MONGOOSEV_IRQ_TIMER2 MONGOOSEV_IRQ_INT1 -#define MONGOOSEV_IRQ_INT2 MIPS_INTERRUPT_BASE+2 -#define MONGOOSEV_IRQ_INT3 MIPS_INTERRUPT_BASE+3 -#define MONGOOSEV_IRQ_FPU MONGOOSEV_IRQ_INT3 - -#define MONGOOSEV_IRQ_INT4 MIPS_INTERRUPT_BASE+4 - -/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */ -#define MONGOOSEV_IRQ_PERIPHERAL_BASE MIPS_INTERRUPT_BASE+5 -#define MONGOOSEV_IRQ_XINT0 MONGOOSEV_IRQ_PERIPHERAL_BASE + 0 -#define MONGOOSEV_IRQ_XINT1 MONGOOSEV_IRQ_PERIPHERAL_BASE + 1 -#define MONGOOSEV_IRQ_XINT2 MONGOOSEV_IRQ_PERIPHERAL_BASE + 2 -#define MONGOOSEV_IRQ_XINT3 MONGOOSEV_IRQ_PERIPHERAL_BASE + 3 -#define MONGOOSEV_IRQ_XINT4 MONGOOSEV_IRQ_PERIPHERAL_BASE + 4 -#define MONGOOSEV_IRQ_XINT5 MONGOOSEV_IRQ_PERIPHERAL_BASE + 5 -#define MONGOOSEV_IRQ_XINT6 MONGOOSEV_IRQ_PERIPHERAL_BASE + 6 -#define MONGOOSEV_IRQ_XINT7 MONGOOSEV_IRQ_PERIPHERAL_BASE + 7 -#define MONGOOSEV_IRQ_XINT8 MONGOOSEV_IRQ_PERIPHERAL_BASE + 8 -#define MONGOOSEV_IRQ_XINT9 MONGOOSEV_IRQ_PERIPHERAL_BASE + 9 -#define MONGOOSEV_IRQ_RESERVED_BIT_10 MONGOOSEV_IRQ_PERIPHERAL_BASE + 10 -#define MONGOOSEV_IRQ_UART0_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 11 -#define MONGOOSEV_IRQ_UART0_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 12 -#define MONGOOSEV_IRQ_UART0_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 13 -#define MONGOOSEV_IRQ_UART0_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 14 -#define MONGOOSEV_IRQ_UART0_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 15 -#define MONGOOSEV_IRQ_RESERVED_BIT_16 MONGOOSEV_IRQ_PERIPHERAL_BASE + 16 -#define MONGOOSEV_IRQ_UART1_RX_FRAME_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 17 -#define MONGOOSEV_IRQ_UART1_RX_OVERRUN_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 18 -#define MONGOOSEV_IRQ_UART1_TX_EMPTY MONGOOSEV_IRQ_PERIPHERAL_BASE + 19 -#define MONGOOSEV_IRQ_UART1_TX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 20 -#define MONGOOSEV_IRQ_UART1_RX_READY MONGOOSEV_IRQ_PERIPHERAL_BASE + 21 -#define MONGOOSEV_IRQ_READ_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 22 -#define MONGOOSEV_IRQ_WRITE_ACCESS_VIOLATION MONGOOSEV_IRQ_PERIPHERAL_BASE + 23 -#define MONGOOSEV_IRQ_RESERVED_24 MONGOOSEV_IRQ_PERIPHERAL_BASE + 24 -#define MONGOOSEV_IRQ_RESERVED_25 MONGOOSEV_IRQ_PERIPHERAL_BASE + 25 -#define MONGOOSEV_IRQ_RESERVED_26 MONGOOSEV_IRQ_PERIPHERAL_BASE + 26 -#define MONGOOSEV_IRQ_RESERVED_27 MONGOOSEV_IRQ_PERIPHERAL_BASE + 27 -#define MONGOOSEV_IRQ_RESERVED_28 MONGOOSEV_IRQ_PERIPHERAL_BASE + 28 -#define MONGOOSEV_IRQ_RESERVED_29 MONGOOSEV_IRQ_PERIPHERAL_BASE + 29 -#define MONGOOSEV_IRQ_UNCORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 30 -#define MONGOOSEV_IRQ_CORRECTABLE_ERROR MONGOOSEV_IRQ_PERIPHERAL_BASE + 31 - -#define MONGOOSEV_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+37 -#define MONGOOSEV_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+38 -#define MONGOOSEV_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+39 - /* * Status Register Bits diff --git a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c deleted file mode 100644 index 6933eb7553..0000000000 --- a/c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. - * - * COPYRIGHT (c) 1989-2000. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -/* - * Reserve first 32 for exceptions. - */ - -/* - * The Synova Mongoose-V attached one of the eight interrupt bits - * to a Peripheral Function Interrupt Cause Register on-CPU. - * This results in: 2 software interrupts, 5 interrupts - * through the IP bits, and 32 more from the PFICR. Some of - * these are reserved but for simplicity in processing, we - * reserve slots for those bits anyway. - */ - -#include -#include - -unsigned int mips_interrupt_number_of_vectors = MONGOOSEV_MAXIMUM_VECTORS; diff --git a/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c deleted file mode 100644 index c7ef845e60..0000000000 --- a/c/src/lib/libcpu/mips/r46xx/vectorisrs/maxvectors.c +++ /dev/null @@ -1,19 +0,0 @@ -/* - * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. - * - * COPYRIGHT (c) 1989-2000. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -/* - * Reserve first 32 for exceptions. - */ - -unsigned int mips_interrupt_number_of_vectors = 32 + 8; diff --git a/c/src/lib/libcpu/mips/rm52xx/include/rm5231.h b/c/src/lib/libcpu/mips/rm52xx/include/rm5231.h index a10837c396..9982ac2c2c 100644 --- a/c/src/lib/libcpu/mips/rm52xx/include/rm5231.h +++ b/c/src/lib/libcpu/mips/rm52xx/include/rm5231.h @@ -1,12 +1,21 @@ -/* +/** + * @file + * * MIPS RM5231 specific information + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). * - * rm5231.h,v 1.0 2004/06/23 19:54:22 + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ */ #ifndef __RM5231_h #define __RM5231_h -#define RM5231_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+8 - #endif diff --git a/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c deleted file mode 100644 index 79c509ca21..0000000000 --- a/c/src/lib/libcpu/mips/rm52xx/vectorisrs/maxvectors.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. - * - * COPYRIGHT (c) 1989-2000. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * maxvectors.c,v 1.1.6.1 2003/09/04 18:45:49 joel Exp - */ - -/* - * Reserve first 32 for exceptions. - */ - - -#include -#include - -unsigned int mips_interrupt_number_of_vectors = RM5231_MAXIMUM_VECTORS; - diff --git a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h index 7c66a9e0bc..9f5bd276b9 100644 --- a/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h +++ b/c/src/lib/libcpu/mips/shared/interrupts/isr_entries.h @@ -1,4 +1,16 @@ +/** + * @file + * + */ + /* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * * $Id$ */ @@ -6,6 +18,7 @@ #define _ISR_ENTRIES_H 1 extern void mips_install_isr_entries( void ); +extern void mips_vector_isr_handlers( CPU_Interrupt_frame *frame ); #if __mips == 1 extern void exc_utlb_code(void); diff --git a/c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c b/c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c deleted file mode 100644 index 483f86f511..0000000000 --- a/c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c +++ /dev/null @@ -1,128 +0,0 @@ -/* - * Common Code for Vectoring MIPS Exceptions - * - * The actual decoding of the cause register and vector number assignment - * is CPU model specific. - * - * $Id$ - */ - -#include -#include -#include -#include -#include -#include - -static const char *cause_strings[32] = -{ - /* 0 */ "Int", - /* 1 */ "TLB Mods", - /* 2 */ "TLB Load", - /* 3 */ "TLB Store", - /* 4 */ "Address Load", - /* 5 */ "Address Store", - /* 6 */ "Instruction Bus Error", - /* 7 */ "Data Bus Error", - /* 8 */ "Syscall", - /* 9 */ "Breakpoint", - /* 10 */ "Reserved Instruction", - /* 11 */ "Coprocessor Unuseable", - /* 12 */ "Overflow", - /* 13 */ "Trap", - /* 14 */ "Instruction Virtual Coherency Error", - /* 15 */ "FP Exception", - /* 16 */ "Reserved 16", - /* 17 */ "Reserved 17", - /* 18 */ "Reserved 18", - /* 19 */ "Reserved 19", - /* 20 */ "Reserved 20", - /* 21 */ "Reserved 21", - /* 22 */ "Reserved 22", - /* 23 */ "Watch", - /* 24 */ "Reserved 24", - /* 25 */ "Reserved 25", - /* 26 */ "Reserved 26", - /* 27 */ "Reserved 27", - /* 28 */ "Reserved 28", - /* 29 */ "Reserved 29", - /* 30 */ "Reserved 30", - /* 31 */ "Data Virtual Coherency Error" -}; - -struct regdef -{ - int offset; - char *name; -}; - -static const struct regdef dumpregs[]= { - { R_RA, "R_RA" }, { R_V0, "R_V0" }, { R_V1, "R_V1" }, - { R_A0, "R_A0" }, { R_A1, "R_A1" }, { R_A2, "R_A2" }, - { R_A3, "R_A3" }, { R_T0, "R_T0" }, { R_T1, "R_T1" }, - { R_T2, "R_T2" }, { R_T3, "R_T3" }, { R_T4, "R_T4" }, - { R_T5, "R_T5" }, { R_T6, "R_T6" }, { R_T7, "R_T7" }, - { R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" }, - { R_GP, "R_GP" }, { R_FP, "R_FP" }, { R_AT, "R_AT" }, - { R_EPC,"R_EPC"}, { -1, NULL } -}; - -static void mips_dump_exception_frame( CPU_Interrupt_frame *frame ) -{ - uint32_t *frame_u32; - int i, j; - - frame_u32 = (uint32_t *)frame; - for(i=0; dumpregs[i].offset > -1; i++) - { - printk(" %s", dumpregs[i].name); - for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" "); -#if (__mips == 1 ) || (__mips == 32) - printk(" %08X%c", frame_u32[dumpregs[i].offset], (i%3) ? '\t' : '\n' ); -#elif __mips == 3 - printk(" %08X", frame_u32[2 * dumpregs[i].offset + 1] ); - printk("%08X%c", frame_u32[2 * dumpregs[i].offset], (i%2) ? '\t' : '\n' ); -#endif - } - printk( "\n" ); -} - -static void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame ) -{ - uint32_t sr; - uint32_t cause; - - mips_get_sr( sr ); - mips_get_cause( cause ); - - printk( "Unhandled exception %d\n", exc ); - printk( "sr: 0x%08x cause: 0x%08x --> %s\n", sr, cause, - cause_strings[(cause >> 2) &0x1f] ); - mips_dump_exception_frame( frame ); - - rtems_fatal_error_occurred(1); -} - -#define CALL_EXC(_vector,_frame) \ - do { \ - if ( _ISR_Vector_table[_vector] ) \ - (_ISR_Vector_table[_vector])(_vector,_frame); \ - else \ - mips_default_exception_code_handler( _vector, _frame ); \ - } while(0) - -/* - * There are constants defined for these but they should basically - * all be close to the same set. - */ - -void mips_vector_exceptions( CPU_Interrupt_frame *frame ) -{ - uint32_t cause; - uint32_t exc; - - mips_get_cause( cause ); - exc = (cause >> 2) & 0x1f; - - CALL_EXC( exc, frame ); -} diff --git a/c/src/lib/libcpu/mips/tx39/include/tx3904.h b/c/src/lib/libcpu/mips/tx39/include/tx3904.h index 6da4d24c61..c55a3222ea 100644 --- a/c/src/lib/libcpu/mips/tx39/include/tx3904.h +++ b/c/src/lib/libcpu/mips/tx39/include/tx3904.h @@ -1,8 +1,19 @@ -/* +/** + * @file + * * MIPS Tx3904 specific information * * NOTE: This is far from complete. --joel (13 Dec 2000) + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * * $Id$ */ @@ -33,32 +44,4 @@ #define TX3904_TIMER_WRITE( _base, _register, _value ) \ *((volatile uint32_t*)((_base) + (_register))) = (_value) -/* - * Interrupt Vector Numbers - * - * NOTE: Numbers 0-15 directly map to levels on the IRC. - * Number 16 is "1xxxx" per p. 164 of the TX3904 manual. - */ - -#define TX3904_IRQ_INT1 MIPS_INTERRUPT_BASE+0 -#define TX3904_IRQ_INT2 MIPS_INTERRUPT_BASE+1 -#define TX3904_IRQ_INT3 MIPS_INTERRUPT_BASE+2 -#define TX3904_IRQ_INT4 MIPS_INTERRUPT_BASE+3 -#define TX3904_IRQ_INT5 MIPS_INTERRUPT_BASE+4 -#define TX3904_IRQ_INT6 MIPS_INTERRUPT_BASE+5 -#define TX3904_IRQ_INT7 MIPS_INTERRUPT_BASE+6 -#define TX3904_IRQ_DMAC3 MIPS_INTERRUPT_BASE+7 -#define TX3904_IRQ_DMAC2 MIPS_INTERRUPT_BASE+8 -#define TX3904_IRQ_DMAC1 MIPS_INTERRUPT_BASE+9 -#define TX3904_IRQ_DMAC0 MIPS_INTERRUPT_BASE+10 -#define TX3904_IRQ_SIO0 MIPS_INTERRUPT_BASE+11 -#define TX3904_IRQ_SIO1 MIPS_INTERRUPT_BASE+12 -#define TX3904_IRQ_TMR0 MIPS_INTERRUPT_BASE+13 -#define TX3904_IRQ_TMR1 MIPS_INTERRUPT_BASE+14 -#define TX3904_IRQ_TMR2 MIPS_INTERRUPT_BASE+15 -#define TX3904_IRQ_INT0 MIPS_INTERRUPT_BASE+16 -#define TX3904_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+17 -#define TX3904_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+18 -#define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19 - #endif diff --git a/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c deleted file mode 100644 index 5a4fb9ca73..0000000000 --- a/c/src/lib/libcpu/mips/tx39/vectorisrs/maxvectors.c +++ /dev/null @@ -1,29 +0,0 @@ -/* - * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. - * - * COPYRIGHT (c) 1989-2000. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * $Id$ - */ - -/* - * Reserve first 32 for exceptions. - */ - -/* - * The Toshiba TX3904 attaches 4 of the eight interrupt bits to an - * on-CPU interrupt controller so that these four bits map to 16 - * unique interrupts. So you have: 2 software interrupts, an NMI, - * and 16 others. - */ - -#include -#include - -unsigned int mips_interrupt_number_of_vectors = TX3904_MAXIMUM_VECTORS; diff --git a/c/src/lib/libcpu/mips/tx49/include/tx4925.h b/c/src/lib/libcpu/mips/tx49/include/tx4925.h index a55107b8c1..925da94fef 100644 --- a/c/src/lib/libcpu/mips/tx49/include/tx4925.h +++ b/c/src/lib/libcpu/mips/tx49/include/tx4925.h @@ -1,7 +1,18 @@ -/* +/** + * @file + * * MIPS Tx4925 specific information + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). * - * tx4925.h,v 1.0 2004/06/23 19:54:22 + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ */ #ifndef __TX4925_h @@ -95,45 +106,4 @@ #define TX4925_REG_WRITE( _base, _register, _value ) \ *((volatile uint32_t *)((_base) + (_register))) = (_value) -/* - * Interrupt Vector Numbers - * - */ -#define TX4925_IRQ_RSV1 MIPS_INTERRUPT_BASE+0 -#define TX4925_IRQ_WTE MIPS_INTERRUPT_BASE+1 -#define TX4925_IRQ_INT0 MIPS_INTERRUPT_BASE+2 -#define TX4925_IRQ_INT1 MIPS_INTERRUPT_BASE+3 -#define TX4925_IRQ_INT2 MIPS_INTERRUPT_BASE+4 -#define TX4925_IRQ_INT3 MIPS_INTERRUPT_BASE+5 -#define TX4925_IRQ_INT4 MIPS_INTERRUPT_BASE+6 -#define TX4925_IRQ_INT5 MIPS_INTERRUPT_BASE+7 -#define TX4925_IRQ_INT6 MIPS_INTERRUPT_BASE+8 -#define TX4925_IRQ_INT7 MIPS_INTERRUPT_BASE+9 -#define TX4925_IRQ_RSV2 MIPS_INTERRUPT_BASE+10 -#define TX4925_IRQ_NAND MIPS_INTERRUPT_BASE+11 -#define TX4925_IRQ_SIO0 MIPS_INTERRUPT_BASE+12 -#define TX4925_IRQ_SIO1 MIPS_INTERRUPT_BASE+13 -#define TX4925_IRQ_DMAC0 MIPS_INTERRUPT_BASE+14 -#define TX4925_IRQ_DMAC1 MIPS_INTERRUPT_BASE+15 -#define TX4925_IRQ_DMAC2 MIPS_INTERRUPT_BASE+16 -#define TX4925_IRQ_DMAC3 MIPS_INTERRUPT_BASE+17 -#define TX4925_IRQ_IRC MIPS_INTERRUPT_BASE+18 -#define TX4925_IRQ_PDMAC MIPS_INTERRUPT_BASE+19 -#define TX4925_IRQ_PCIC MIPS_INTERRUPT_BASE+20 -#define TX4925_IRQ_TMR0 MIPS_INTERRUPT_BASE+21 -#define TX4925_IRQ_TMR1 MIPS_INTERRUPT_BASE+22 -#define TX4925_IRQ_TMR2 MIPS_INTERRUPT_BASE+23 -#define TX4925_IRQ_SPI MIPS_INTERRUPT_BASE+24 -#define TX4925_IRQ_RTC MIPS_INTERRUPT_BASE+25 -#define TX4925_IRQ_ACLC MIPS_INTERRUPT_BASE+26 -#define TX4925_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27 -#define TX4925_IRQ_CHI MIPS_INTERRUPT_BASE+28 -#define TX4925_IRQ_PCIERR MIPS_INTERRUPT_BASE+29 -#define TX4925_IRQ_PCIPME MIPS_INTERRUPT_BASE+30 -#define TX4925_IRQ_RSV3 MIPS_INTERRUPT_BASE+31 - -#define TX4925_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32 -#define TX4925_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33 -#define TX4925_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34 - #endif diff --git a/c/src/lib/libcpu/mips/tx49/include/tx4938.h b/c/src/lib/libcpu/mips/tx49/include/tx4938.h index 3264784ddd..07733075f4 100644 --- a/c/src/lib/libcpu/mips/tx49/include/tx4938.h +++ b/c/src/lib/libcpu/mips/tx49/include/tx4938.h @@ -1,7 +1,18 @@ -/* +/** + * @file + * * MIPS Tx4938 specific information + */ + +/* + * COPYRIGHT (c) 1989-2012. + * On-Line Applications Research Corporation (OAR). * - * tx4938.h,v 1.0 2004/06/23 19:54:22 + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.com/license/LICENSE. + * + * $Id$ */ #ifndef __TX4938_h @@ -110,47 +121,6 @@ #define TX4938_REG_WRITE( _base, _register, _value ) \ *((volatile uint32_t *)((_base) + (_register))) = (_value) -/* - * Interrupt Vector Numbers - * - */ -#define TX4938_IRQ_ECC MIPS_INTERRUPT_BASE+0 -#define TX4938_IRQ_WTE MIPS_INTERRUPT_BASE+1 -#define TX4938_IRQ_INT0 MIPS_INTERRUPT_BASE+2 -#define TX4938_IRQ_INT1 MIPS_INTERRUPT_BASE+3 -#define TX4938_IRQ_INT2 MIPS_INTERRUPT_BASE+4 -#define TX4938_IRQ_INT3 MIPS_INTERRUPT_BASE+5 -#define TX4938_IRQ_INT4 MIPS_INTERRUPT_BASE+6 -#define TX4938_IRQ_INT5 MIPS_INTERRUPT_BASE+7 -#define TX4938_IRQ_SIO0 MIPS_INTERRUPT_BASE+8 -#define TX4938_IRQ_SIO1 MIPS_INTERRUPT_BASE+9 -#define TX4938_IRQ_DMAC00 MIPS_INTERRUPT_BASE+10 -#define TX4938_IRQ_DMAC01 MIPS_INTERRUPT_BASE+11 -#define TX4938_IRQ_DMAC02 MIPS_INTERRUPT_BASE+12 -#define TX4938_IRQ_DMAC03 MIPS_INTERRUPT_BASE+13 -#define TX4938_IRQ_IRC MIPS_INTERRUPT_BASE+14 -#define TX4938_IRQ_PDMAC MIPS_INTERRUPT_BASE+15 -#define TX4938_IRQ_PCIC MIPS_INTERRUPT_BASE+16 -#define TX4938_IRQ_TMR0 MIPS_INTERRUPT_BASE+17 -#define TX4938_IRQ_TMR1 MIPS_INTERRUPT_BASE+18 -#define TX4938_IRQ_TMR2 MIPS_INTERRUPT_BASE+19 -#define TX4938_IRQ_RSV1 MIPS_INTERRUPT_BASE+20 -#define TX4938_IRQ_NDFMC MIPS_INTERRUPT_BASE+21 -#define TX4938_IRQ_PCIERR MIPS_INTERRUPT_BASE+22 -#define TX4938_IRQ_PCIPMC MIPS_INTERRUPT_BASE+23 -#define TX4938_IRQ_ACLC MIPS_INTERRUPT_BASE+24 -#define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+25 -#define TX4938_IRQ_PCIC1NT MIPS_INTERRUPT_BASE+26 -#define TX4938_IRQ_ACLCPME MIPS_INTERRUPT_BASE+27 -#define TX4938_IRQ_DMAC10 MIPS_INTERRUPT_BASE+28 -#define TX4938_IRQ_DMAC11 MIPS_INTERRUPT_BASE+29 -#define TX4938_IRQ_DMAC12 MIPS_INTERRUPT_BASE+30 -#define TX4938_IRQ_DMAC13 MIPS_INTERRUPT_BASE+31 - -#define TX4938_IRQ_SOFTWARE_1 MIPS_INTERRUPT_BASE+32 -#define TX4938_IRQ_SOFTWARE_2 MIPS_INTERRUPT_BASE+33 -#define TX4938_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+34 - /************************************************************************ * TX49 Register field encodings *************************************************************************/ diff --git a/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c b/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c deleted file mode 100644 index e56989a297..0000000000 --- a/c/src/lib/libcpu/mips/tx49/vectorisrs/maxvectors.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file contains the maximum number of vectors. This can not - * be determined without knowing the RTEMS CPU model. - * - * COPYRIGHT (c) 1989-2000. - * On-Line Applications Research Corporation (OAR). - * - * The license and distribution terms for this file may be - * found in the file LICENSE in this distribution or at - * http://www.rtems.com/license/LICENSE. - * - * maxvectors.c,v 1.1.6.1 2003/09/04 18:45:49 joel Exp - */ - -/* - * Reserve first 32 for exceptions. - */ - -/* - * The Toshiba TX4925 attaches 5 of the eight interrupt bits to an - * on-CPU interrupt controller so that these five bits map to 32 - * unique interrupts. So you have: 2 software interrupts, an NMI, - * and 32 others. - */ - -#include -#include - -unsigned int mips_interrupt_number_of_vectors = TX4925_MAXIMUM_VECTORS; - -- cgit v1.2.3