From b4d0d18eeda3ee81816c33140de46bb6bc724d43 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Wed, 13 Dec 2000 17:52:53 +0000 Subject: 2000-12-13 Joel Sherrill * shared/.cvsignore, shared/Makefile.am, shared/cache/.cvsignore, shared/cache/Makefile.am, shared/cache/cache.c, shared/cache/cache_.h, shared/interrupts/.cvsignore, shared/interrupts/Makefile.am, shared/interrupts/installisrentries.c, shared/interrupts/isr_entries.S, shared/interrupts/maxvectors.c, tx39/.cvsignore, tx39/Makefile.am, tx39/include/.cvsignore, tx39/include/Makefile.am, tx39/include/tx3904.h: New file. Moved some pieces of interrupt processing from score/cpu to libcpu/mips since many interrupt servicing characteristics are CPU model dependent. This patch addresses the number of interrupt sources and where the ISR prologues are located. The only way to currently install the ISR prologues requires that the prologues be installed into RAM. --- c/src/lib/libcpu/mips/configure.in | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'c/src/lib/libcpu/mips/configure.in') diff --git a/c/src/lib/libcpu/mips/configure.in b/c/src/lib/libcpu/mips/configure.in index 822592cdc0..70e45bc664 100644 --- a/c/src/lib/libcpu/mips/configure.in +++ b/c/src/lib/libcpu/mips/configure.in @@ -29,8 +29,15 @@ RTEMS_CHECK_BSP_CACHE(RTEMS_BSP) AM_CONDITIONAL(r46xx, test "$RTEMS_CPU_MODEL" = "R4600" \ || test "$RTEMS_CPU_MODEL" = "R4650" ) +AM_CONDITIONAL(tx39, test "$RTEMS_CPU_MODEL" = "tx3904") + # Explicitly list all Makefiles here AC_OUTPUT( Makefile clock/Makefile +shared/Makefile +shared/cache/Makefile +shared/interrupts/Makefile +tx39/Makefile +tx39/include/Makefile timer/Makefile) -- cgit v1.2.3