From a114f99bd28cd534b1446d2d85ea681ef1832955 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Sun, 3 Jul 2016 17:26:50 +0200 Subject: bsps/arm: Change code to explicit selection of cache implementation for ARM BSPs. The original ARM architecture wide cache_.h is changed to dummy version for targets not implementing/enablig cache at all. The ARM targets equipped by cache should include appropriate implementation. Next options are available for now c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h basic ARM cache integrated on the CPU core directly which requires only CP15 oparations c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h support for case where ARM L2C-310 cache controller is used. It is accessible as mmaped peripheral. c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h Cortex-M specific cache support Updates #2782 Updates #2783 --- c/src/lib/libcpu/arm/shared/include/cache_.h | 134 ++++++--------------------- 1 file changed, 30 insertions(+), 104 deletions(-) (limited to 'c/src/lib/libcpu/arm/shared/include/cache_.h') diff --git a/c/src/lib/libcpu/arm/shared/include/cache_.h b/c/src/lib/libcpu/arm/shared/include/cache_.h index a31fc11fc4..9db399edf7 100644 --- a/c/src/lib/libcpu/arm/shared/include/cache_.h +++ b/c/src/lib/libcpu/arm/shared/include/cache_.h @@ -3,7 +3,7 @@ * * @ingroup arm * - * @brief ARM cache defines and implementation. + * @brief ARM cache dummy include for chips without cache */ /* @@ -23,110 +23,36 @@ #ifndef LIBCPU_ARM_CACHE__H #define LIBCPU_ARM_CACHE__H -#ifdef __ARM_ARCH_5TEJ__ - #include - - #define CPU_DATA_CACHE_ALIGNMENT 32 - #define CPU_INSTRUCTION_CACHE_ALIGNMENT 32 - - static inline void _CPU_cache_flush_1_data_line(const void *d_addr) - { - arm_cp15_data_cache_clean_line(d_addr); - } - - static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr) - { - arm_cp15_data_cache_invalidate_line(d_addr); - } - - static inline void _CPU_cache_freeze_data(void) - { - /* TODO */ - } - - static inline void _CPU_cache_unfreeze_data(void) - { - /* TODO */ - } - - static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr) - { - arm_cp15_instruction_cache_invalidate_line(d_addr); - } - - static inline void _CPU_cache_freeze_instruction(void) - { - /* TODO */ - } - - static inline void _CPU_cache_unfreeze_instruction(void) - { - /* TODO */ - } - - static inline void _CPU_cache_flush_entire_data(void) - { - arm_cp15_data_cache_test_and_clean(); - } - - static inline void _CPU_cache_invalidate_entire_data(void) - { - arm_cp15_data_cache_invalidate(); - } - - static inline void _CPU_cache_enable_data(void) - { - rtems_interrupt_level level; - uint32_t ctrl; - - rtems_interrupt_disable(level); - ctrl = arm_cp15_get_control(); - ctrl |= ARM_CP15_CTRL_C; - arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); - } - - static inline void _CPU_cache_disable_data(void) - { - rtems_interrupt_level level; - uint32_t ctrl; - - rtems_interrupt_disable(level); - arm_cp15_data_cache_test_and_clean_and_invalidate(); - ctrl = arm_cp15_get_control(); - ctrl &= ~ARM_CP15_CTRL_C; - arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); - } - - static inline void _CPU_cache_invalidate_entire_instruction(void) - { - arm_cp15_instruction_cache_invalidate(); - } - - static inline void _CPU_cache_enable_instruction(void) - { - rtems_interrupt_level level; - uint32_t ctrl; - - rtems_interrupt_disable(level); - ctrl = arm_cp15_get_control(); - ctrl |= ARM_CP15_CTRL_I; - arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); - } - - static inline void _CPU_cache_disable_instruction(void) - { - rtems_interrupt_level level; - uint32_t ctrl; +/* + * The ARM targets equipped by cache should include + * which kind and implementation they support. + * Next options are available + * + * c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h + * basic ARM cache integrated on the CPU core directly + * which requires only CP15 oparations + * + * c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h + * support for case where ARM L2C-310 cache controller + * is used. It is accessible as mmaped peripheral. + * + * c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h + * Cortex-M specific cache support + * + * Cache support should be included in BSP Makefile.am + * + * Example how to include cache support + * + * # Cache + * libbsp_a_SOURCES += ../../../libcpu/shared/src/cache_manager.c + * libbsp_a_SOURCES += ../shared/include/arm-cache-l1.h + * libbsp_a_SOURCES += ../shared/armv467ar-basic-cache/cache_.h + * libbsp_a_CPPFLAGS += -I$(srcdir)/../shared/armv467ar-basic-cache + */ - rtems_interrupt_disable(level); - ctrl = arm_cp15_get_control(); - ctrl &= ~ARM_CP15_CTRL_I; - arm_cp15_set_control(ctrl); - rtems_interrupt_enable(level); - } +#if defined(__ARM_ARCH_5TEJ__) || defined(__ARM_ARCH_7A__) +#warning ARM 5TEJ and ARMv7/Cortex-A cores include usually cache +#warning change BSP to include appropriate cache implementation #endif #endif /* LIBCPU_ARM_CACHE__H */ -- cgit v1.2.3