From 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52 Mon Sep 17 00:00:00 2001 From: Joel Sherrill Date: Mon, 12 Jun 2000 19:57:02 +0000 Subject: Patch from John Cotton , Charles-Antoine Gauthier , and Darlene A. Stewart to add support for a number of very significant things: + BSPs for many variations on the Motorola MBX8xx board series + Cache Manager including initial support for m68040 and PowerPC + Rework of mpc8xx libcpu code so all mpc8xx CPUs now use same code base. + Rework of eth_comm BSP to utiltize above. John reports this works on the 821 and 860 --- c/src/lib/libc/malloc.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) (limited to 'c/src/lib/libc/malloc.c') diff --git a/c/src/lib/libc/malloc.c b/c/src/lib/libc/malloc.c index 08660d75cc..dc6824891a 100644 --- a/c/src/lib/libc/malloc.c +++ b/c/src/lib/libc/malloc.c @@ -418,5 +418,27 @@ void _free_r( { free( ptr ); } + + +/* + * rtems_cache_aligned_malloc + * + * DESCRIPTION: + * + * This function is used to allocate storage that spans an + * integral number of cache blocks. + */ +RTEMS_INLINE_ROUTINE void * rtems_cache_aligned_malloc ( + size_t nbytes +) +{ + /* + * Arrange to have the user storage start on the first cache + * block beyond the header. + */ + return (void *) ((((unsigned long) malloc( nbytes + _CPU_DATA_CACHE_ALIGNMENT - 1 )) + + _CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(_CPU_DATA_CACHE_ALIGNMENT - 1)) ); +} + #endif -- cgit v1.2.3